arxiv: 2605.03494 · v2 · submitted 2026-05-05 · 💻 cs.CR · cs.ET

Recognition: no theorem link

Design of Memristive Lightweight Encryption For In-Memory Image Steganography

Seyed Erfan Fatemieh , Reza Shahdi Alizadeh , Esmail Zarezadeh

Authors on Pith no claims yet

Pith reviewed 2026-05-13 07:39 UTC · model grok-4.3

classification 💻 cs.CR cs.ET

keywords memristive arrayslightweight cryptographyTriviumGrain-128aIMPLY logicin-memory computingshift registersimage steganography

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The pith

A new data-shifting technique in memristive arrays implements Trivium and Grain-128a ciphers with up to 42 percent fewer steps and 44 percent less energy.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

Data movement between processor and memory drives high energy use and leaves information exposed during transfer. The paper places lightweight stream ciphers inside memristive arrays so computation stays local. It redesigns Trivium and Grain-128a using stateful IMPLY logic and adds an efficient shifting method for their registers. This change lowers computational steps by up to 42 percent and energy consumption by up to 44 percent compared with standard IMPLY designs. The resulting circuits are tested inside an image steganography task to confirm they deliver both security and efficiency in practice.

Core claim

The authors implement the Trivium and Grain-128a stream ciphers in memristive computation-in-memory arrays using stateful IMPLY logic. They introduce a data-shifting method for the ciphers' shift registers that reduces the number of computational steps and energy consumption by up to 42 percent and 44 percent, respectively, relative to conventional IMPLY-based realizations. These circuits are evaluated within an image steganography application to demonstrate their ability to secure data while limiting movement between memory and processor.

What carries the argument

The proposed efficient data-shifting method applied to the shift registers of Trivium and Grain-128a implemented with stateful IMPLY logic in memristive CIM-A architectures.

If this is right

Encryption occurs with lower overhead in hardware-constrained devices because data no longer moves repeatedly between memory and processor.
Security improves for data in transit since all operations remain inside the memory array.
The same shifting approach can be applied to other register-based lightweight ciphers implemented with IMPLY logic.
Secure in-memory image processing becomes feasible without exposing plaintext during steganography operations.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

The shifting optimization could reduce energy in any shift-register cipher mapped to memristive arrays beyond the two examples shown.
Edge devices that perform secure image handling would see lower total power draw if the in-memory design replaces conventional processor-memory transfers.
Physical prototypes must be tested to confirm the energy figures hold once memristor variability and wiring parasitics are included.

Load-bearing premise

Stateful IMPLY logic in physical memristive arrays will deliver the modeled step counts and energy savings without extra costs from device variations or interconnect overhead.

What would settle it

Fabricate the proposed memristive circuits for Trivium and Grain-128a, run the ciphers on actual hardware, and measure whether the observed step counts and energy consumption match the simulated reductions of 42 percent and 44 percent.

Figures

Figures reproduced from arXiv: 2605.03494 by Esmail Zarezadeh, Reza Shahdi Alizadeh, Seyed Erfan Fatemieh.

**Figure 1.** Figure 1: Architecture of the stream cipher Trivium (Paar u. a., 2024; De Canni`ere und Preneel, 2008). 4 view at source ↗

**Figure 2.** Figure 2: Architecture of Grain-128a: (a) the pre-output generator, and (b) the key initiaization (˚Agren u. a., 2011). 5 view at source ↗

**Figure 3.** Figure 3: (a) Memristor symbol, and (b) memristive IMPLY gate (Fatemieh und Reshadinezhad, 2026). no voltage/current is applied to its terminals, making it an emerging non-volatile memory cell. Memristive CIM has another fundamental aspect: the execution of logic and arithmetic operations. Researchers have proposed several methods for implementing logic and arithmetic functions using memristors, which are generally … view at source ↗

**Figure 4.** Figure 4: The serial architecture of IMPLY-based logical and arithmetic circuits (Fatemieh u. a., 2025b; Fatemieh und Reshadinezhad, 2026; Bagheralmoosavi u. a., 2025). 2.3 Memristive cryptography Memristors can be applied in cryptography due to their electrical properties. This subsection briefly discusses a few of these applications. In (Yang u. a., 2021), an architecture is introduced that generates random number… view at source ↗

**Figure 4.** Figure 4: The serial architecture of IMPLY-based logical and arithmetic circuits [2, 4, 6]. to memrsitors ‘p’ and ‘q’ in [PITH_FULL_IMAGE:figures/full_fig_p006_4.png] view at source ↗

**Figure 5.** Figure 5: The output waveform of a destructive IMPLY-based serial two-input XOR gate introduced in (Bagheralmoosavi u. a., 2025) for input state “00”. To analyze the functionality of the simulated circuits, note that, since all logic and arithmetic blocks are stateful, the input and output logical values are determined by the memristors’ resistance. The maximum and minimum resistance values of the memristor are equ… view at source ↗

**Figure 6.** Figure 6: The output waveform of a non-destructive IMPLY-based serial two-input XOR gate for input state “00” view at source ↗

**Figure 7.** Figure 7: The output waveform of a IMPLY-based serial three-input AND gate for input state “111”. and presenting a number of simulation outputs, the results of the circuit evaluation criteria for the IMPLY-based basic logic gates required in the implementation of the Trivium and Grain-128a, lightweight stream ciphers, are summarized in view at source ↗

**Figure 8.** Figure 8: Functionality analysis of IMPLY-based lightweight stream ciphers in steganography:(a) Cover image (“boat”), (b) Trivium-based stego image, and (c) Grain-128a stego image. (a) (b) (c) view at source ↗

**Figure 9.** Figure 9: Functionality analysis of IMPLY-based lightweight stream ciphers in steganography:(a) Cover image (“circuit”), (b) Trivium-based stego image, and (c) Grain-128a stego image view at source ↗

**Figure 10.** Figure 10: Histograms of (a) view at source ↗

**Figure 10.** Figure 10: Histograms of (a) [PITH_FULL_IMAGE:figures/full_fig_p021_10.png] view at source ↗

**Figure 11.** Figure 11: Histograms of (a) view at source ↗

read the original abstract

With the expansion of data-intensive applications and increasing data volumes, providing an efficient solution to address growing energy consumption and performance degradation caused by the transfer of large amounts of data between the processor and the main memory has become a severe challenge. The frequent transfer of large amounts of data between internal chip units, memories, and their interconnections exacerbates the vulnerability of the data being accessed. Employing a memristive Computation In-Memory-Array (CIM-A) architecture limits data transfer, thereby addressing both challenges. Furthermore, by integrating lightweight cryptography, developed to secure data in hardware-constrained devices, with CIM-A architectures, the security of data in transit, especially across interconnections, can be ensured. This paper implements two standard lightweight stream ciphers, Trivium and Grain-128a, for CIM using stateful material implication (IMPLY) logic to address these combined security and performance challenges. In addition to redesigning the cryptographic structures, we reduce the hardware complexity of conventional IMPLY-based implementations by proposing an efficient method for shifting data within the shift registers. Applying the proposed data-shifting method to the registers of these ciphers reduces the number of computational steps and decreases energy consumption by up to 42% and 44%, respectively, compared to conventional implementations. Finally, the performance of the proposed circuits is evaluated in a steganography application, demonstrating their practical efficiency.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Desk Editor's Note private letter to a colleague

The paper maps Trivium and Grain-128a onto IMPLY logic in memristive CIM-A arrays and adds a data-shifting method for registers that claims 42-44% fewer steps and lower energy, but the gains rest on idealized operation counts with no variability or interconnect modeling shown.

read the letter

The core contribution is taking two standard lightweight stream ciphers and adapting their structures for stateful IMPLY operations inside computation-in-memory arrays, plus a targeted tweak for moving data through shift registers more efficiently. This produces the quoted reductions in computational steps and energy for an image steganography workload. The work is a direct hardware-level extension rather than a new cipher or framework, and the shifting method looks like a useful, incremental optimization for register-heavy designs in this logic family. It does give a concrete example of how to limit data movement while adding encryption in constrained hardware, which aligns with the stated goal of cutting processor-memory traffic and securing it at the same time. The steganography evaluation at least shows the circuits can be plugged into a real application without obvious breakage. The soft spot is that the performance numbers come from step counting and energy estimates under perfect gate behavior. No device models, Monte Carlo runs, resistance drift, threshold variation, or line-resistance overheads appear in the description, so the 42% and 44% figures could shrink or disappear once parasitics and non-idealities are included. There are also no baseline circuit diagrams or simulation waveforms to cross-check against the claims. This is a design proposal that stays at the architectural level. It is aimed at people already working on memristive in-memory security or lightweight crypto for edge devices; someone building similar CIM-A blocks might borrow the shifting trick. It is coherent on its own terms and engages the relevant prior work on IMPLY logic and the two ciphers, so it deserves a serious referee to verify the circuit details and request more realistic hardware modeling before any stronger claims are made.

Referee Report

2 major / 1 minor

Summary. The manuscript describes the design of memristive implementations of the Trivium and Grain-128a lightweight stream ciphers using stateful IMPLY logic within a Computation In-Memory Array (CIM-A) architecture. The authors propose a novel data-shifting method for the shift registers that is claimed to reduce the number of computational steps by up to 42% and energy consumption by up to 44% relative to conventional IMPLY-based designs. These optimized circuits are then evaluated within an image steganography application to illustrate their utility in securing data transfers while mitigating energy and performance bottlenecks in data-intensive systems.

Significance. If substantiated with detailed validation, the work would offer a promising approach to combining lightweight cryptography with in-memory computing to enhance both security and efficiency in hardware-constrained environments. The integration addresses key challenges in data movement between processor and memory, potentially impacting applications in IoT and embedded systems. The specific reductions in steps and energy, if robust, represent a tangible improvement over standard implementations, though their practical impact depends on validation against hardware non-idealities.

major comments (2)

Abstract: The headline performance claims of up to 42% fewer computational steps and 44% lower energy consumption are presented without any accompanying details on the calculation methodology, the conventional baseline implementations, the memristor device models employed, or the simulation framework used. This lack of supporting information renders the quantitative results impossible to assess or reproduce.
Evaluation (steganography application): The assessment of the proposed circuits does not include any analysis of the effects of memristor variability (e.g., 10-20% threshold-voltage spreads or resistance drift), interconnect parasitic RC delays, or sneak-path currents. Without Monte-Carlo or corner-case simulations, it is unclear whether the reported efficiency gains would survive in physical hardware.

minor comments (1)

Abstract: The acronym CIM-A is introduced without expansion; spelling out 'Computation In-Memory Array' on first use would improve readability.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the constructive feedback on our manuscript. We address each major comment point by point below, indicating the revisions we will incorporate in the next version.

read point-by-point responses

Referee: Abstract: The headline performance claims of up to 42% fewer computational steps and 44% lower energy consumption are presented without any accompanying details on the calculation methodology, the conventional baseline implementations, the memristor device models employed, or the simulation framework used. This lack of supporting information renders the quantitative results impossible to assess or reproduce.

Authors: We agree that the abstract should provide more context for the headline claims to improve clarity and reproducibility. The detailed calculation methodology (step counting and energy estimation via SPICE), conventional IMPLY-based baseline shift-register designs, VTEAM memristor model parameters, and simulation framework are fully described in Sections III and IV of the manuscript. We will revise the abstract to include a brief summary of these elements, for example by adding a clause such as 'using SPICE simulations with the VTEAM model and conventional IMPLY shift registers as baseline'. revision: yes
Referee: Evaluation (steganography application): The assessment of the proposed circuits does not include any analysis of the effects of memristor variability (e.g., 10-20% threshold-voltage spreads or resistance drift), interconnect parasitic RC delays, or sneak-path currents. Without Monte-Carlo or corner-case simulations, it is unclear whether the reported efficiency gains would survive in physical hardware.

Authors: We acknowledge the importance of evaluating robustness under non-ideal conditions. The current results use ideal device models to isolate the benefits of the proposed shift-register method. In the revised manuscript we will add a dedicated subsection discussing the potential impact of variability and include preliminary Monte-Carlo results assuming 10-15% Gaussian variation in threshold voltage and resistance. A full treatment of interconnect RC delays and sneak-path currents would require an extended circuit-level model that goes beyond the scope of the present architectural study; we will note this explicitly as a limitation and direction for future work. revision: partial

Circularity Check

0 steps flagged

No circularity: step and energy reductions obtained by direct operation counting on proposed shift-register redesign

full rationale

The paper redesigns Trivium and Grain-128a registers for stateful IMPLY logic and introduces a data-shifting method. The headline performance numbers (up to 42% fewer steps, 44% lower energy) are produced by enumerating the IMPLY operations required by the new shifting sequence versus a conventional baseline. No equation is defined in terms of its own output, no parameter is fitted to a subset of results and then re-used as a prediction, and no load-bearing uniqueness theorem or ansatz is imported via self-citation. The derivation therefore remains a straightforward combinatorial count on explicitly stated logic primitives and is self-contained.

Axiom & Free-Parameter Ledger

0 free parameters · 2 axioms · 0 invented entities

The central claim rests on the feasibility of mapping standard stream-cipher operations onto stateful IMPLY logic in memristive crossbars and on the accuracy of the energy models used to compute the 42% and 44% savings. No new physical particles or forces are introduced.

axioms (2)

domain assumption Stateful material implication logic can be reliably implemented with memristive devices for sequential logic operations
Invoked when mapping cipher state machines to CIM-A arrays
domain assumption Energy consumption scales linearly with the number of IMPLY steps in the shift-register implementation
Used to translate step reduction into the reported percentage savings

pith-pipeline@v0.9.0 · 5559 in / 1367 out tokens · 50398 ms · 2026-05-13T07:39:18.113678+00:00 · methodology

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discussion (0)

Reference graph

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