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arxiv: 2605.10679 · v2 · submitted 2026-05-11 · 💻 cs.NE

Recognition: 2 theorem links

· Lean Theorem

Energy-Efficient Implementation of Spiking Recurrent Cells on FPGA

Pascal Harmeling , Florent De Geeter , Guillaume Drion
Authors on Pith no claims yet

Pith reviewed 2026-05-13 06:50 UTC · model grok-4.3

classification 💻 cs.NE
keywords Spiking Neural NetworksFPGA ImplementationSpiking Recurrent CellsEnergy EfficiencyMNIST ClassificationQuantizationHardware Approximation
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The pith

Spiking Recurrent Cells can be simplified for efficient FPGA implementation while retaining richer dynamics than LIF models.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper develops an FPGA accelerator for spiking neural networks that uses Spiking Recurrent Cell neurons instead of simpler models. Mathematical simplifications replace expensive operations like tanh and exp with piecewise approximations and scaling, allowing fixed-point arithmetic and direct storage of offline weights in LUT registers. On an Artix-7 FPGA running at 100 MHz, the design reaches 96.31 percent accuracy on MNIST spiking traces in 1.74 milliseconds per digit. Quantized versions with 4-bit weights and shorter traces still deliver 92.89 percent accuracy at 0.45 millijoules per image. This shows SRC neurons can balance biological plausibility with hardware cost for energy-efficient SNNs.

Core claim

SRC-based SNNs can deliver competitive performance with reduced energy consumption while preserving richer neuronal dynamics than standard LIF/IR models. The complete network is implemented in VHDL after removing unary operators through scaling and piecewise approximations, with offline weights stored directly in LUT registers. Reference implementation achieves 96.31 percent accuracy with 220-image traces at 1.7424 ms per digit; quantized 4-bit version reaches 92.89 percent at 0.45 mJ with 44 images.

What carries the argument

Spiking Recurrent Cell (SRC) neuron model simplified via piecewise approximations and fixed-point scaling to eliminate tanh, exp, and floating-point operations.

If this is right

  • SRC neurons enable SNNs on FPGA that use richer temporal dynamics than LIF or IR models at comparable hardware cost.
  • Quantization to 4 bits and trace lengths down to 44 spikes cut energy to 0.45 mJ per MNIST digit while retaining over 92 percent accuracy.
  • Offline weight matrices can be loaded directly into LUT registers without runtime adaptation and still support high accuracy.
  • The 100 MHz Artix-7 implementation processes each digit in under 2 ms with sparse spiking activity.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • SRC simplifications may transfer to other neuromorphic platforms where avoiding floating-point units reduces power draw.
  • The robustness to quantization suggests SRC cells could support longer sequences or multi-task learning without retraining overhead.
  • Energy numbers position SRC-based SNNs as candidates for always-on edge devices that need more than binary spike integration.
  • Extending the piecewise method to other biologically detailed neuron models could widen the set of hardware-feasible SNNs.

Load-bearing premise

The piecewise approximations and scaling preserve enough SRC dynamics that offline-computed weights stay effective without on-chip adaptation or retraining under the chosen MNIST spike encoding.

What would settle it

A direct comparison experiment showing that replacing the approximated SRC with exact floating-point dynamics or retraining the 4-bit quantized weights on-chip raises accuracy by more than 3 percentage points while keeping energy under 0.5 mJ per digit.

Figures

Figures reproduced from arXiv: 2605.10679 by Florent De Geeter, Guillaume Drion, Pascal Harmeling.

Figure 1
Figure 1. Figure 1: Simplification of the tanh function using Stanh. Tanh() - Stanh() - Error The operator exp() used in zs[t] cannot be easily simplified, and its use within a fraction further increases the complexity.However, one can observe that zs[t] acts as a switching mechanism between a slow and a fast dynamical regime, as shown in [PITH_FULL_IMAGE:figures/full_fig_p004_1.png] view at source ↗
Figure 1
Figure 1. Figure 1: Simplification of the tanh function using Stanh. Tanh() - Stanh() - Error Vth H[t] Z[t] [PITH_FULL_IMAGE:figures/full_fig_p005_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: Simplification of the function z[t] into a threshold rule with detection threshold Vth(z) Finally, the parameter rs is adjusted from −7 to −8. This modification yields even-valued parameters, enabling multiplications to be implemented using shift operations, without affecting model dynamics. This also makes it possible to remove the explicit parameters r and rs and to adjust bh (which becomes 3000 after sc… view at source ↗
Figure 2
Figure 2. Figure 2: Simplification of the function z[t] into a threshold rule with detection threshold Vth(z) model dynamics. This also makes it possible to remove the explicit parameters r and rs and to adjust bh (which becomes 3000 after scaling). Likewise, factoring out zs[t] allows us to merge two multiplications into a single operation. The simplified SRC equations are written as    W ork = I[t] + (h[t − 1] … view at source ↗
Figure 3
Figure 3. Figure 3: (a) Behavior of the output h[t] as a function of the implementation, Julia and PsV, (b) with a zoomed comparison of spikes generated in Julia and PsV. Inferences of the complete PsV network implementation are first carried out in Julia in order to compare the original SRC network with our simplified version. To ensure a fair comparison, it is essential to use exactly the same Spiking Trace (SpT) sequences.… view at source ↗
Figure 3
Figure 3. Figure 3: (a) Behavior of the output h[t] as a function of the implementation, Julia and PsV, (b) with a zoomed comparison of spikes generated in Julia and PsV. Inferences of the complete PsV network implementation are first carried out in Julia in order to compare the original SRC network with our simplified version. To ensure a fair comparison, it is essential to use exactly the same Spiking Trace (SpT) sequences.… view at source ↗
Figure 4
Figure 4. Figure 4: MNIST dataset processed by a Julia code, spiking traces. (a) (b) [PITH_FULL_IMAGE:figures/full_fig_p006_4.png] view at source ↗
Figure 4
Figure 4. Figure 4: MNIST dataset processed by a Julia code, spiking traces. cases, both models show very similar output dynamics, the only difference occurs when the classifi￾cation decision is unclear ( [PITH_FULL_IMAGE:figures/full_fig_p007_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: (a) Spike generation frequency at the output of hs as a function of the value of z hyp s . (b) Stability results and accuracy layer (Neuron LIfB pkg), and finally a comparator that outputs a value between 0 and 9 (Neuron Cmp pkg) [PITH_FULL_IMAGE:figures/full_fig_p006_5.png] view at source ↗
Figure 5
Figure 5. Figure 5: (a) Spike generation frequency at the output of hs as a function of the value of z hyp s . (b) Stability results and accuracy is activated at the end of the trace to enable the comparison between the discriminator output and CMP VAL. 4.2 SRC layer and IR layer The SRC layer receives an input vector of 784 spikes along with 2 neuromodulatory bits. It is composed of 100 fully connected SRC neurons. The input… view at source ↗
Figure 6
Figure 6. Figure 6: Architecture of the neural network on FPGA. is an Alinx AX7A200B equipped with an AMD Xilinx Artix-7 XC7A200T shown in [PITH_FULL_IMAGE:figures/full_fig_p007_6.png] view at source ↗
Figure 6
Figure 6. Figure 6: Architecture of the neural network on FPGA. 14 [PITH_FULL_IMAGE:figures/full_fig_p014_6.png] view at source ↗
Figure 7
Figure 7. Figure 7: Internal structure of a neural network layer. signals. The µ-RESET signal is activated at the beginning of each spiking trace to reset the neurons, while µ-CMP is activated at the end of the trace to enable the comparison between the discriminator output and CMP VAL. 4.2 SRC layer and IR layer The SRC layer receives an input vector of 784 spikes along with 2 neuromodulatory bits. It is composed of 100 full… view at source ↗
Figure 7
Figure 7. Figure 7: Internal structure of a neural network layer. 15 [PITH_FULL_IMAGE:figures/full_fig_p015_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: Stability results and accuracy (the two true solutions) [PITH_FULL_IMAGE:figures/full_fig_p013_8.png] view at source ↗
Figure 8
Figure 8. Figure 8: Stability results and accuracy (the two true solutions) [PITH_FULL_IMAGE:figures/full_fig_p016_8.png] view at source ↗
Figure 9
Figure 9. Figure 9: Stability results and accuracy (one true - one false solution). 13 [PITH_FULL_IMAGE:figures/full_fig_p013_9.png] view at source ↗
Figure 9
Figure 9. Figure 9: Stability results and accuracy (one true - one false solution). 16 [PITH_FULL_IMAGE:figures/full_fig_p016_9.png] view at source ↗
Figure 10
Figure 10. Figure 10: Test setup using the Alinx XC7A200 board. 14 [PITH_FULL_IMAGE:figures/full_fig_p014_10.png] view at source ↗
Figure 10
Figure 10. Figure 10: Test setup using the Alinx XC7A200 board. 17 [PITH_FULL_IMAGE:figures/full_fig_p017_10.png] view at source ↗
read the original abstract

Spiking Neural Networks (SNNs) can reduce energy consumption compared to conventional Artificial Neural Networks (ANNs) when spiking activity is sparse and the neuron model is hardware-friendly. However, biologically faithful models are often too costly to implement on FPGAs, whereas very simple models (e.g., IR/LIF) sacrifice part of the neuronal dynamics. In this work, we present an FPGA accelerator for an SNN using Spiking Recurrent Cell (SRC) neurons, providing a trade-off between biological plausibility and hardware cost. We propose a set of mathematical simplifications that remove costly unary operators (\textit{tanh}, \textit{exp}) and avoid floating-point arithmetic through scaling and piecewise-defined approximations. The complete network is implemented in VHDL and validated using spiking traces derived from the MNIST dataset. The weight matrices computed off-line are stored directly in LUT-registers without any adaptation. This demonstrates the robustness of SRC cells. Experiments were conducted on an Artix-7 XC7A200T clocked at 100 MHz. The reference implementation achieves 96.31\% accuracy with a 220-image spiking trace and a processing time of 1.7424 ms per digit. We then investigate accuracy/energy trade-offs by reducing the spiking trace length and quantizing synaptic weights down to 4 bits, achieving 93.32\% accuracy at 0.55 mJ per digit (55 images, 5-bit weights) and 92.89\% at 0.45 mJ (44 images, 4-bit weights). These results show that SRC-based SNNs can deliver competitive performance with reduced energy consumption, while preserving richer neuronal dynamics than standard LIF/IR models.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

3 major / 2 minor

Summary. The paper presents an FPGA accelerator for spiking neural networks using Spiking Recurrent Cell (SRC) neurons. It proposes piecewise-linear approximations to eliminate tanh and exp operations along with fixed-point scaling to enable efficient VHDL implementation on an Artix-7 FPGA at 100 MHz. Using offline-trained weights stored in LUTs and MNIST-derived spiking traces, the reference design achieves 96.31% accuracy at 1.7424 ms per digit; quantized variants reach 92.89% accuracy at 0.45 mJ per digit. The work claims this provides a favorable trade-off between biological plausibility and hardware cost while preserving richer dynamics than standard LIF/IR models.

Significance. If the approximations are shown to retain SRC's distinguishing recurrent behavior and the performance claims are supported by direct baselines, the result would demonstrate a practical, hardware-friendly neuron model that improves on both overly simple LIF implementations and biologically detailed but costly alternatives, with direct relevance to energy-constrained neuromorphic edge devices.

major comments (3)
  1. [Results] Results section: the manuscript reports absolute accuracy and energy figures (96.31% reference, 92.89% at 4-bit weights) but supplies neither error bars across multiple runs nor a side-by-side LIF/IR baseline synthesized on the identical Artix-7 device with matching clock, quantization, trace length, and spike encoding; without this comparison the claim that SRC delivers 'richer neuronal dynamics' and competitive performance cannot be evaluated.
  2. [Methods] Methods / Implementation: no state-trajectory, bifurcation, or internal-state comparison is provided between the original SRC, the piecewise-linear approximation, and LIF under identical inputs; the central positioning of SRC as preserving richer dynamics therefore rests on the untested assumption that the approximations (removing tanh/exp) do not collapse the recurrent behavior.
  3. [Abstract] Abstract and Experiments: details on how the MNIST spike traces were generated (encoding scheme, trace length mapping to image count, preprocessing) are absent, and the reported numbers (220-image trace vs. 55/44 images in quantized cases) are not cross-referenced, preventing assessment of whether the accuracy reflects the claimed SRC advantage or the specific trace properties.
minor comments (2)
  1. [Implementation] Clarify the exact piecewise breakpoints, slopes, and global scaling factor used for the tanh/exp approximations, as these are free parameters affecting reproducibility.
  2. [Abstract] The abstract states '220-image spiking trace' for the reference run but later cites '55 images' and '44 images' for quantized cases; explicitly state the relationship between trace length and number of processed digits.

Simulated Author's Rebuttal

3 responses · 0 unresolved

We thank the referee for the constructive and detailed comments. We address each major point below, agreeing where revisions are needed to improve clarity and support for our claims, and we will update the manuscript accordingly.

read point-by-point responses

  1. Referee: [Results] Results section: the manuscript reports absolute accuracy and energy figures (96.31% reference, 92.89% at 4-bit weights) but supplies neither error bars across multiple runs nor a side-by-side LIF/IR baseline synthesized on the identical Artix-7 device with matching clock, quantization, trace length, and spike encoding; without this comparison the claim that SRC delivers 'richer neuronal dynamics' and competitive performance cannot be evaluated.

    Authors: We agree that direct baselines and statistical measures would strengthen the evaluation. The reported accuracies are deterministic given fixed offline-trained weights and a specific spike trace; however, we will generate error bars by averaging over multiple independent Poisson spike encodings of the MNIST test set (varying random seeds for spike generation while keeping the same image sequence). We will also synthesize a LIF-based SNN on the identical Artix-7 device at 100 MHz, using the same quantization, trace lengths, and encoding scheme, and include side-by-side tables for accuracy, energy per classification, latency, and resource utilization. This will enable a quantitative assessment of the claimed advantages. revision: yes

  2. Referee: [Methods] Methods / Implementation: no state-trajectory, bifurcation, or internal-state comparison is provided between the original SRC, the piecewise-linear approximation, and LIF under identical inputs; the central positioning of SRC as preserving richer dynamics therefore rests on the untested assumption that the approximations (removing tanh/exp) do not collapse the recurrent behavior.

    Authors: We acknowledge that explicit dynamical comparisons are necessary to support the claim of richer dynamics. The piecewise-linear approximations were constructed to match the original SRC nullclines and fixed-point structure within the relevant input range, but we did not include validation plots. In the revised manuscript we will add a new subsection with numerical simulations showing state trajectories (membrane potential and recurrent state) and bifurcation diagrams for the original SRC, the hardware approximation, and a standard LIF model under identical step and sinusoidal inputs. These will demonstrate that the approximation retains the SRC's ability to exhibit more complex firing patterns than LIF. revision: yes

  3. Referee: [Abstract] Abstract and Experiments: details on how the MNIST spike traces were generated (encoding scheme, trace length mapping to image count, preprocessing) are absent, and the reported numbers (220-image trace vs. 55/44 images in quantized cases) are not cross-referenced, preventing assessment of whether the accuracy reflects the claimed SRC advantage or the specific trace properties.

    Authors: We apologize for the missing details. The spike traces are generated via Poisson rate coding: each MNIST pixel intensity is normalized to [0,1] and converted to a spike probability per time step; the trace length equals the number of time steps (and thus images) presented sequentially to the network. The reference uses a 220-step trace (220 images), while the quantized variants use shorter traces of 55 and 44 steps (images) to reduce energy. We will insert a dedicated paragraph in the Experiments section (and update the abstract if space permits) that fully describes the encoding, preprocessing (no additional filtering), and explicitly cross-references each reported accuracy to its corresponding trace length and image count. revision: yes

Circularity Check

0 steps flagged

No circularity: results are direct hardware measurements, not reductions of fitted parameters

full rationale

The manuscript describes piecewise-linear approximations to remove tanh/exp, fixed-point scaling, and a VHDL implementation on Artix-7. Accuracy (96.31 % reference, 92.89 % quantized) and energy (0.45 mJ) figures are obtained by synthesizing the network, loading offline-computed weights into LUTs, and executing on physical hardware with MNIST spike traces. No equation or claim defines the reported metrics in terms of the same fitted quantities, nor does any self-citation chain substitute for an independent derivation. The derivation chain is therefore self-contained against external benchmarks.

Axiom & Free-Parameter Ledger

2 free parameters · 0 axioms · 0 invented entities

The central claim rests on standard digital design practices plus two ad-hoc engineering choices: piecewise linear replacements for tanh/exp and global scaling to integer arithmetic. No new physical entities or unstated mathematical axioms are introduced.

free parameters (2)
  • piecewise approximation breakpoints and slopes
    Chosen to remove unary operators while keeping the SRC response close enough for the target task.
  • global scaling factor for fixed-point conversion
    Selected to eliminate floating-point units on the FPGA.

pith-pipeline@v0.9.0 · 5610 in / 1204 out tokens · 87036 ms · 2026-05-13T06:50:48.577658+00:00 · methodology

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Reference graph

Works this paper leans on

23 extracted references · 23 canonical work pages · 2 internal anchors

  1. [1]

    Lapicque’s introduction of the integrate-and-fire model neuron (1907).Brain research bulletin, 50(5-6):303–304, 1999

    Larry F Abbott. Lapicque’s introduction of the integrate-and-fire model neuron (1907).Brain research bulletin, 50(5-6):303–304, 1999

    work page 1907

  2. [2]

    Exploring the sparsity-quantization interplay on a novel hybrid snn event-driven architecture

    Ilkin Aliyev, Jesus Lopez, and Tosiron Adegbija. Exploring the sparsity-quantization interplay on a novel hybrid snn event-driven architecture. In2025 Design, Automation & Test in Europe Conference (DATE), pages 1–7. IEEE, 2025

    work page 2025

  3. [3]

    Spiker: an fpga-optimized hardware accelerator for spiking neural networks

    Alessio Carpegna, Alessandro Savino, and Stefano Di Carlo. Spiker: an fpga-optimized hardware accelerator for spiking neural networks. In2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pages 14–19. IEEE, 2022

    work page 2022

  4. [4]

    Spiker+: a framework for the generation of efficient spiking neural networks fpga accelerators for inference at the edge.IEEE Transactions on Emerging Topics in Computing, 2024

    Alessio Carpegna, Alessandro Savino, and Stefano Di Carlo. Spiker+: a framework for the generation of efficient spiking neural networks fpga accelerators for inference at the edge.IEEE Transactions on Emerging Topics in Computing, 2024

    work page 2024

  5. [5]

    Are snns really more energy-efficient than anns? an in-depth hardware-aware study.IEEE Transactions on Emerging Topics in Computational Intelligence, 7(3):731–741, 2022

    Manon Dampfhoffer, Thomas Mesquida, Alexandre Valentian, and Lorena Anghel. Are snns really more energy-efficient than anns? an in-depth hardware-aware study.IEEE Transactions on Emerging Topics in Computational Intelligence, 7(3):731–741, 2022

    work page 2022

  6. [6]

    Spike-based computation using clas- sical recurrent neural networks.Neuromorphic Computing and Engineering, 4(2):024007, 2024

    Florent De Geeter, Damien Ernst, and Guillaume Drion. Spike-based computation using clas- sical recurrent neural networks.Neuromorphic Computing and Engineering, 4(2):024007, 2024

    work page 2024

  7. [7]

    Is the integrate-and-fire model good enough?—a review.Neural networks, 14 (6-7):955–975, 2001

    Jianfeng Feng. Is the integrate-and-fire model good enough?—a review.Neural networks, 14 (6-7):955–975, 2001

    work page 2001

  8. [8]

    Fpga implementation of simplified spiking neural network

    Shikhar Gupta, Arpan Vyas, and Gaurav Trivedi. Fpga implementation of simplified spiking neural network. In2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS), pages 1–4. IEEE, 2020

    work page 2020

  9. [9]

    Hardware implementation of spiking neural networks on fpga.Tsinghua Science and Technology, 25(4):479–486, 2020

    Jianhui Han, Zhaolin Li, Weimin Zheng, and Youhui Zhang. Hardware implementation of spiking neural networks on fpga.Tsinghua Science and Technology, 25(4):479–486, 2020

    work page 2020

  10. [10]

    Zhen He, Cong Shi, Tengxiao Wang, Ying Wang, Min Tian, Xichuan Zhou, Ping Li, Liyuan Liu, Nanjian Wu, and Gang Luo. A low-cost fpga implementation of spiking extreme learning machine with on-chip reward-modulated stdp learning.IEEE Transactions on Circuits and Systems II: Express Briefs, 69(3):1657–1661, 2021

    work page 2021

  11. [11]

    A quantitative description of membrane current and its application to conduction and excitation in nerve.The Journal of physiology, 117(4):500, 1952

    Alan L Hodgkin and Andrew F Huxley. A quantitative description of membrane current and its application to conduction and excitation in nerve.The Journal of physiology, 117(4):500, 1952

    work page 1952

  12. [12]

    Neuromorphic is dead

    Giacomo Indiveri. Neuromorphic is dead. long live neuromorphic.Neuron, 113(20):3311–3314, 2025

    work page 2025

  13. [13]

    Jindong Li, Guobin Shen, Dongcheng Zhao, Qian Zhang, and Yi Zeng. Firefly: A high- throughput hardware accelerator for spiking neural networks with efficient dsp and memory optimization.IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 31(8):1178– 1191, 2023

    work page 2023

  14. [14]

    Sixu Li, Zhaomin Zhang, Ruixin Mao, Jianbiao Xiao, Liang Chang, and Jun Zhou. A fast and energy-efficient snn processor with adaptive clock/event-driven computation scheme and online learning.IEEE Transactions on Circuits and Systems I: Regular Papers, 68(4):1543–1552, 2021. 18

    work page 2021

  15. [15]

    A Neuromodulable Current-Mode Silicon Neuron for Robust and Adaptive Neuromorphic Systems

    Loris Mendolia, Chenxi Wen, Elisabetta Chicca, Giacomo Indiveri, Rodolphe Sepulchre, Jean- Michel Redout´ e, and Alessio Franci. A neuromodulable current-mode silicon neuron for robust and adaptive neuromorphic systems.arXiv preprint arXiv:2512.01133, 2025

    work page internal anchor Pith review Pith/arXiv arXiv 2025

  16. [16]

    Openspike: an openram snn accelerator

    Farhad Modaresi, Matthew Guthaus, and Jason K Eshraghian. Openspike: an openram snn accelerator. In2023 IEEE International Symposium on Circuits and Systems (ISCAS), pages 1–5. IEEE, 2023

    work page 2023

  17. [17]

    Syncnn: Evaluating and accelerating spiking neural networks on fpgas.ACM Transactions on Reconfigurable Technology and Systems, 15(4):1–27, 2022

    Sathish Panchapakesan, Zhenman Fang, and Jian Li. Syncnn: Evaluating and accelerating spiking neural networks on fpgas.ACM Transactions on Reconfigurable Technology and Systems, 15(4):1–27, 2022

    work page 2022

  18. [18]

    A programmable event-driven architecture for evaluating spiking neural networks

    Arnab Roy, Swagath Venkataramani, Neel Gala, Sanchari Sen, Kamakoti Veezhinathan, and Anand Raghunathan. A programmable event-driven architecture for evaluating spiking neural networks. In2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), pages 1–6. IEEE, 2017

    work page 2017

  19. [19]

    Conductance-based models.Scholarpedia, 1(11):1408, 2006

    Frances K Skinner. Conductance-based models.Scholarpedia, 1(11):1408, 2006

    work page 2006

  20. [20]

    Energy and policy considerations for deep learning in nlp

    Emma Strubell, Ananya Ganesh, and Andrew McCallum. Energy and policy considerations for deep learning in nlp. InProceedings of the 57th annual meeting of the association for computational linguistics, pages 3645–3650, 2019

    work page 2019

  21. [21]

    Energy efficient parallel neuromorphic architectures with approximate arithmetic on fpga.Neurocomputing, 221:146– 158, 2017

    Qian Wang, Youjie Li, Botang Shao, Siddhartha Dey, and Peng Li. Energy efficient parallel neuromorphic architectures with approximate arithmetic on fpga.Neurocomputing, 221:146– 158, 2017

    work page 2017

  22. [22]

    Efficient spiking convolutional neural networks accelerator with multi-structure compatibility

    Jiadong Wu, Lun Lu, Yinan Wang, Zhiwei Li, Changlin Chen, Qingjiang Li, and Kairang Chen. Efficient spiking convolutional neural networks accelerator with multi-structure compatibility. Frontiers in Neuroscience, 19:1662886, 2025

    work page 2025

  23. [23]

    Reconsidering the energy efficiency of spiking neural networks

    Zhanglu Yan, Zhenyu Bai, and Weng-Fai Wong. Reconsidering the energy efficiency of spiking neural networks.arXiv preprint arXiv:2409.08290, 2024. 19

    work page internal anchor Pith review Pith/arXiv arXiv 2024