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arxiv: 2605.11243 · v1 · submitted 2026-05-11 · 💻 cs.NE · eess.SP

Recognition: 2 theorem links

· Lean Theorem

Leveraging Non-Equilibrium ECRAM Dynamics for Short-Term Plasticity in Neuromorphic Circuits

Alex Currie , Sean Borkholder , Nithil Harris Manimaran , Huayuan Han , Cory Merkel , Ke Xu , Tejasvi Das
Authors on Pith no claims yet

Pith reviewed 2026-05-13 00:58 UTC · model grok-4.3

classification 💻 cs.NE eess.SP
keywords ECRAMshort-term plasticityneuromorphic computingleaky integrate-and-fire neuronsynaptic facilitationspiking neural networkstemporal computationmemristive devices
0
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The pith

Non-equilibrium ECRAM dynamics can serve as a native hardware substrate for short-term plasticity in neuromorphic circuits.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper shows that transient conductance changes in ECRAM devices, often treated as unwanted variability, can instead be used directly to produce short-term plasticity behaviors in hardware. A delay-feedback LIF neuron is co-designed with ECRAM synapses so that activity-dependent ionic dynamics modulate both synaptic efficacy and neuron excitability with almost no added circuitry. Simulations drawn from experimental device measurements demonstrate synaptic facilitation, excitability tuning, and frequency-selective spike filtering across neuron types, all at 2 pJ per spike. A reader would care because this approach embeds temporal computation in the physics of the memory device rather than requiring separate dedicated circuits.

Core claim

The central claim is that non-equilibrium ECRAM ionic dynamics generate transient conductance modulation (1.5 kΩ per spike) that, when paired with a tunable delay-feedback LIF architecture, directly produces synaptic facilitation and intrinsic excitability modulation; the same mechanisms extend to multiple neuron topologies and allow individual synapses to function as tunable temporal filters in spiking networks while consuming 2 pJ per spike.

What carries the argument

The delay-feedback leaky integrate-and-fire neuron architecture co-designed with ECRAM synapses, which routes activity-dependent conductance modulation into the spike-generation path to alter excitability and synaptic strength.

If this is right

  • Synaptic facilitation arises directly from the device's transient conductance changes without auxiliary circuits.
  • Neuron excitability can be modulated by recent spiking history through the same ECRAM dynamics.
  • Individual synapses can operate as tunable temporal filters for frequency-selective spike processing in networks.
  • The same device-circuit co-design works across multiple neuron topologies with low overhead.
  • Overall energy remains at 2 pJ per spike in the simulated configurations.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • This device-level approach could reduce the area and power cost of adding explicit short-term memory elements in neuromorphic chips.
  • Variability in real ECRAM endurance might limit the reliability of the temporal filtering over long operation.
  • The same co-design principle could be tested on other volatile memristive technologies to broaden the set of native plasticity mechanisms.
  • Large-scale networks built this way might show emergent filtering behaviors not captured in the small-scale simulations.

Load-bearing premise

The compact behavioral model extracted from experimental ECRAM data accurately represents all relevant non-equilibrium dynamics under the voltage and timing conditions of the proposed circuit, with negligible variability or endurance loss.

What would settle it

A fabricated delay-feedback LIF circuit using the characterized ECRAM devices that fails to exhibit synaptic facilitation or excitability modulation, or that consumes substantially more than 2 pJ per spike, would disprove the central claim.

Figures

Figures reproduced from arXiv: 2605.11243 by Alex Currie, Cory Merkel, Huayuan Han, Ke Xu, Nithil Harris Manimaran, Sean Borkholder, Tejasvi Das.

Figure 1
Figure 1. Figure 1: Proposed cross-layer framework linking volatile ECRAM device dynamics to neuromorphic computation: Volatile conductance dynamics in fabricated ECRAM devices are modeled and interpreted as a computational primitive corresponding to STP. These dynamics are exploited in neuron circuits to implement activity-dependent modulation within delay-feedback LIF architectures, enabling frequency-selective spike proces… view at source ↗
Figure 2
Figure 2. Figure 2: (a) Schematic of a side-gated ECRAM device. (b) Optical image of the fabricated device (scale bar = 8 µm). (c) Atomic Force Microscopy (AFM) scan of the M oS2 channel before fabrication. (d) Ionically gated transfer characteristics of the fabricated device. VDS is held constant at 100 mV. Cadence circuit simulation tools used for this work. The accuracy of the model is demonstrated in Section 7 through dir… view at source ↗
Figure 3
Figure 3. Figure 3: (a) Proposed 1T1E synapse structure. A HVT NMOS transistor acts as the primary synaptic input, only allowing current to flow when a voltage pulse is applied to its gate. An ECRAM device acts as a synaptic weight, restricting current flow based on its nonvolatile conductance state. Current can be subsequently integrated by a connected LIF circuit structure. (b) By applying a voltage pulse to the ECRAM gate … view at source ↗
Figure 4
Figure 4. Figure 4: Proposed delay-feedback LIF neuron architecture co-designed for operation with volatile ECRAM synapses. Input current mirroring (a) integrates synaptic currents onto the membrane capacitor Cmem, while a positive-feedback firing stage (b) generates robust output spikes and suppresses near-threshold shoot-through currents. A delay-feedback path formed by current-starved inverters and capacitive loading (c) c… view at source ↗
Figure 5
Figure 5. Figure 5: Inverter variant schematics and symbols used in our LIF designs: (a) standard CMOS inverter, (b) CMOS Schmitt trigger inverter, (c) positive feedback inverter and (d) current-starved inverter. The proposed neuron architecture establishes a hardware framework for leveraging volatile ECRAM dynamics. When integrated within larger spiking networks, the activity-dependent modulation produced by these circuits n… view at source ↗
Figure 6
Figure 6. Figure 6: LIF neuron circuit based on the topology introduced in [20]. Our modifications include: (a) a high current mirroring ratio at the synaptic input stage (b) replacement of a traditional CMOS inverter in the output stage with a CMOS schmitt trigger and (c) a high-resistance transistor placed in the membrane voltage reset path. Similarly to the current-starving topology, STP can be implemented by either connec… view at source ↗
Figure 7
Figure 7. Figure 7: Measured volatile current dynamics of fabricated ECRAM devices in response to a 2.5s gate voltage pulse 2.5 applied at varying amplitudes. The model behavior (solid lines) closely matches (R2 = 0.97 − 0.99) the experimental data (markers) for all input pulses, demonstrating an accurate recreation of ECRAM volatile dynamics in a simulated environment. functionality without requiring additional circuitry 7 D… view at source ↗
Figure 8
Figure 8. Figure 8: Number of input spikes required for the capacitive refractory topology (a) and delay-feedback topology at slow (b) and fast (c) timescales to generate an output spike at each nonvolatile ECRAM conductance state. As nonvolatile conductance of the ECRAM device decreases, the synaptic current generated by each input spike is reduced, resulting in a smaller change in membrane voltage. As such a greater number … view at source ↗
Figure 9
Figure 9. Figure 9: Increased activity of the delay-feedback LIF neuron circuit with a synapse in state 60. After 1.2 seconds of repeated input APs, every firing event takes one fewer input to trigger than the initial state, showcasing neuronal facilitation. Highlighted in blue is the output triggering after 6 input stimuli, and highlighted in red is the output triggering after 5 input stimuli. 1.4 1.5 1.6 Synapse Resistance … view at source ↗
Figure 10
Figure 10. Figure 10: Increased activity of the current-starving LIF circuit with a synapse in state 60. After 170 milliseconds of repeated input APs, every firing event takes one fewer input to trigger than the initial state, showcasing synaptic facilitation. Highlighted in blue is the output triggering after 6 input stimuli, and highlighted in red is the output triggering after 5 input stimuli. 14 [PITH_FULL_IMAGE:figures/f… view at source ↗
Figure 11
Figure 11. Figure 11: Histograms demonstrating variability metrics of the delay-feedback LIF topology at selected ECRAM states. (a) The drop in membrane voltage incurred by a single input spike, in mV. (b) The energy consumed by the circuit over the course of a single firing event. (c) The absolute time required to generate an output spike given a 100 kHz, 10% duty cycle input. ability to scale down the circuit to the microsec… view at source ↗
Figure 12
Figure 12. Figure 12: Synaptic facilitation of the capacitive refractory topology with a synapse in conductance state 112. During the first 100 ms, no facilitation occurs and each output spike requires 4 input spikes. Between 100 and 240 ms, a firing pattern of 3-4-3-4 emerges as the synaptic resistance passes through a near-threshold state. Finally, after 240 ms of repeated input activity, the resistance decreases sufficientl… view at source ↗
Figure 13
Figure 13. Figure 13: Activation of a low-conductance synapse in ECRAM conductance state 1 after repeated facilitation from input APs. Initially, membrane leakage dominates synaptic current such that Vmem is unable to reach the firing threshold. As repeated input spikes induce synaptic facilitation, the synaptic conductance gradually increases, allowing the current to eventually overcome leakage and begin generating output APs… view at source ↗
Figure 14
Figure 14. Figure 14: Frequency response of an LIF neuron (Phase space analysis) with ECRAM-based facilitating/depressing synapse. Each panel shows the frequency response νout/nuin vs. τd (vertical axis) and νin (horizontal axis) illustrating how STP dynamics enable frequency-selective temporal filtering of spike trains. Rows and columns in (a) correspond to different values of τf and ∆f /∆d, respectively, with w = 0.6, τs = 0… view at source ↗
Figure 15
Figure 15. Figure 15: Comparison of analytical and simulated frequency responses for a 1-d slice through parameter space of the ECRAM-based synapse with facilitation and depression capabilities. In this parameter regime, the combined effects of synaptic dynamics and membrane leakage produce a band-pass–like frequency response, where spiking occurs only within a limited range of input frequencies per spike. Because volatile and… view at source ↗
read the original abstract

Short-term plasticity (STP) is fundamental to temporal information processing in biological neural systems but remains difficult to realize efficiently in neuromorphic hardware. Memristive electrochemical random-access memory (ECRAM) devices naturally exhibit non-equilibrium ionic dynamics that produce transient conductance modulation; however, these behaviors are typically treated as undesirable variability or tolerated as side effects in memory-centric computing paradigms. In this work, we instead transform these volatile dynamics from a tolerated device artifact into a computational resource through a cross-layer device-circuit-system co-design framework. We introduce a delay-feedback leaky integrate-and-fire (LIF) neuron architecture co-designed with ECRAM synapses that exploits activity-dependent conductance modulation with negligible additional circuit overhead. The architecture integrates ECRAM-based synapses with a tunable delay-feedback spike-generation path, enabling transient device dynamics to directly modulate neuron excitability and synaptic efficacy. We used experimentally characterized ECRAM devices exhibiting transient conductance modulation (1.5 KOhms per spike) to develop a compact behavioral model suitable for circuit-level simulation. Circuit simulations demonstrate two key STP behaviors -- synaptic facilitation and intrinsic excitability modulation -- while consuming 2 pJ per spike, and the same device-driven mechanisms extend across multiple neuron topologies. Network-level analysis further demonstrates frequency-selective spike processing, allowing individual synapses to act as tunable temporal filters within spiking neural networks. This work demonstrates that non-equilibrium ECRAM dynamics can serve as a native hardware substrate for STP and temporal computation in neuromorphic circuits.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 1 minor

Summary. The paper claims that non-equilibrium ionic dynamics in ECRAM devices, which produce transient conductance modulation (experimentally measured at 1.5 kΩ per spike), can be repurposed as a native hardware substrate for short-term plasticity (STP) and temporal computation in neuromorphic circuits. Through a device-circuit co-design, the authors introduce a delay-feedback leaky integrate-and-fire (LIF) neuron architecture that couples ECRAM synapses to a tunable spike-generation path; a compact behavioral model fitted to experimental transients is then used in circuit simulations to demonstrate synaptic facilitation, intrinsic excitability modulation, 2 pJ/spike energy consumption, and frequency-selective spike processing that extends across multiple neuron topologies and enables individual synapses to act as tunable temporal filters in spiking networks.

Significance. If the behavioral model accurately reproduces the relevant non-equilibrium dynamics under the voltage, timing, and feedback conditions of the proposed circuits, the work would demonstrate a low-overhead route to native STP in hardware without auxiliary circuits, turning a common device non-ideality into a computational primitive. This could meaningfully advance energy-efficient temporal processing in neuromorphic systems, with the reported 2 pJ/spike figure and cross-topology generality providing concrete, falsifiable simulation benchmarks.

major comments (2)
  1. [Behavioral Model and Circuit Simulations] The central claim that non-equilibrium ECRAM dynamics serve as a native STP substrate rests entirely on circuit simulations driven by the compact behavioral model derived from experimental transients. No additional device measurements or hardware-in-the-loop validation are reported under the specific pulse amplitudes, intervals, and delay-feedback conditions of the LIF architecture, leaving open whether variability, endurance degradation, or regime-specific deviations would preserve the observed facilitation, excitability modulation, and 2 pJ/spike figures (see abstract description of model development and simulation results).
  2. [Network-level Analysis] The network-level frequency-selective filtering result depends on the model faithfully capturing activity-dependent conductance modulation when coupled to the tunable delay-feedback path. Without independent verification of the model under those exact operating conditions, the extension to tunable temporal filters in SNNs remains simulation-dependent and could be sensitive to unmodeled non-idealities.
minor comments (1)
  1. [Abstract] The abstract states the transient modulation as '1.5 KOhms per spike' while the full text uses '1.5 kΩ'; consistent notation would improve readability.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the detailed and constructive review. The comments correctly identify that our claims rest on a behavioral model fitted to prior device measurements and on circuit simulations rather than new hardware validation under the exact delay-feedback conditions. We have revised the manuscript to strengthen the discussion of model applicability, add sensitivity analyses, and explicitly state the assumptions and limitations. Below we respond point by point.

read point-by-point responses

  1. Referee: [Behavioral Model and Circuit Simulations] The central claim that non-equilibrium ECRAM dynamics serve as a native STP substrate rests entirely on circuit simulations driven by the compact behavioral model derived from experimental transients. No additional device measurements or hardware-in-the-loop validation are reported under the specific pulse amplitudes, intervals, and delay-feedback conditions of the LIF architecture, leaving open whether variability, endurance degradation, or regime-specific deviations would preserve the observed facilitation, excitability modulation, and 2 pJ/spike figures (see abstract description of model development and simulation results).

    Authors: We agree that direct hardware-in-the-loop measurements under the precise delay-feedback LIF operating points would provide stronger confirmation. The compact model was obtained by fitting to experimental transient data collected under pulsed voltages and timings that overlap with the amplitudes and intervals used in the circuit simulations; the 1.5 kΩ per spike modulation and the functional form of the non-equilibrium decay were directly taken from those measurements. In the revised manuscript we have (i) expanded the model-development section with the exact experimental parameter ranges and fitting residuals, (ii) added a dedicated subsection on model limitations that discusses variability, endurance, and possible deviations outside the characterized regime, and (iii) included new Monte-Carlo simulations that propagate measured device-to-device variation through the LIF circuit to quantify impact on facilitation and energy figures. We note, however, that performing new device experiments with the full feedback circuitry is a substantial follow-on effort that lies beyond the scope of the present co-design study. revision: partial

  2. Referee: [Network-level Analysis] The network-level frequency-selective filtering result depends on the model faithfully capturing activity-dependent conductance modulation when coupled to the tunable delay-feedback path. Without independent verification of the model under those exact operating conditions, the extension to tunable temporal filters in SNNs remains simulation-dependent and could be sensitive to unmodeled non-idealities.

    Authors: We acknowledge the simulation dependence. The frequency-selective behavior emerges directly from the same activity-dependent conductance transients that were experimentally observed and captured by the model. In the revision we have added (i) an explicit robustness analysis that sweeps model parameters within the experimentally observed spread and shows that the frequency selectivity persists, and (ii) a new paragraph in the discussion section that enumerates the main unmodeled non-idealities (e.g., history-dependent drift, temperature sensitivity) and their expected influence on the temporal-filtering function. These additions make the assumptions and the simulation-only nature of the network results transparent while preserving the core demonstration that the device dynamics can be co-designed into tunable filters. revision: partial

Circularity Check

0 steps flagged

No circularity: experimental data grounds behavioral model used in forward circuit simulations

full rationale

The paper's chain proceeds from direct experimental characterization of ECRAM transient conductance (1.5 kΩ per spike) to a compact behavioral model fitted to those measurements, followed by circuit simulations of a co-designed delay-feedback LIF architecture that exhibits STP behaviors. This is a standard, non-circular modeling workflow: the model parameters are externally anchored in measured device data rather than defined in terms of the target STP outcomes or circuit results. No self-citation load-bearing steps, uniqueness theorems, or ansatz smuggling appear in the provided text; the frequency-selective filtering and 2 pJ/spike claims are simulation outputs that depend on the architecture-device interaction, not tautological restatements of the input transients. The derivation remains self-contained against the external experimental benchmarks.

Axiom & Free-Parameter Ledger

2 free parameters · 2 axioms · 0 invented entities

The central claim rests on a compact behavioral model fitted to measured transients and on standard assumptions of the LIF neuron model. No new physical entities are postulated.

free parameters (2)
  • transient conductance modulation amplitude
    1.5 kΩ per spike value taken directly from experimental characterization and used to scale all subsequent circuit behavior.
  • delay-feedback time constant
    Tunable parameter in the neuron circuit that must be matched to the ECRAM relaxation dynamics.
axioms (2)
  • domain assumption LIF neuron dynamics with additive delayed feedback accurately represent biological short-term plasticity when driven by ECRAM conductance transients.
    Invoked when the architecture is introduced as enabling transient device dynamics to modulate neuron excitability.
  • domain assumption The compact behavioral model extracted from device measurements remains valid under the voltage and timing regimes of the proposed circuit.
    Required for all circuit-level simulation claims.

pith-pipeline@v0.9.0 · 5580 in / 1573 out tokens · 36792 ms · 2026-05-13T00:58:19.829595+00:00 · methodology

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    Relation between the paper passage and the cited Recognition theorem.

    We used experimentally characterized ECRAM devices exhibiting transient conductance modulation (1.5 kΩ per spike) to develop a compact behavioral model suitable for circuit-level simulation.

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Reference graph

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