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arxiv: 2605.12385 · v1 · submitted 2026-05-12 · 🪐 quant-ph

Recognition: no theorem link

Lower overhead fault-tolerant building blocks for noisy quantum computers

Prithviraj Prabhu
Authors on Pith no claims yet

Pith reviewed 2026-05-13 04:31 UTC · model grok-4.3

classification 🪐 quant-ph
keywords quantum error correctionfault toleranceflag qubitsstabilizer measurementsurface codelogical qubit encodingoverhead reductionplanar codes
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The pith

A distance-four code encoding six logical qubits matches the error protection of the distance-five surface code using one-tenth as many physical qubits.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper shows how to redesign the core circuits for measuring stabilizers and preparing logical states so that fault-tolerant quantum error correction requires far fewer physical qubits and less time. A combinatorial argument proves that flag-based fault tolerance can cut the ancilla qubits needed for any stabilizer measurement exponentially while still catching one fault. The same techniques yield perfect-success state preparation for the Steane and Golay codes and allow a compact planar code to protect six logical qubits at the same reliability level previously achieved only by much larger surface-code patches. If these reductions hold, the total hardware cost of running error-corrected algorithms drops sharply, moving practical fault-tolerant computation closer.

Core claim

We develop a combinatorial proof with flag fault tolerance that exponentially reduces the extra qubits needed to measure a stabilizer of any size, while tolerating one fault. We leverage these proofs to design state preparation circuits for the Steane and Golay codes with 100% yield. A distance-four code encoding six logical qubits protects information as well as the distance-five surface code, using one-tenth as many physical qubits. Finally, protecting measurement results with a classical code cuts the time overhead of logical gates by a factor of two to six.

What carries the argument

Flag fault tolerance combined with combinatorial counting arguments that bound the number of ancilla qubits required for single-fault-tolerant stabilizer measurement of arbitrary weight.

If this is right

  • Stabilizer measurements of any size need only exponentially fewer ancilla qubits while remaining single-fault tolerant.
  • State preparation for the Steane and Golay codes can achieve 100 percent success rate with no post-selection overhead.
  • Equivalent distance protection on a planar layout becomes possible with roughly one-tenth the physical qubits previously required by the surface code.
  • Logical gate execution time in surface-code architectures drops by a factor between two and six when measurement outcomes are protected classically.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The same flag-plus-combinatorial technique could be applied to reduce overhead in other stabilizer codes beyond the Steane and Golay examples given.
  • If the six-logical-qubit block scales without introducing new correlated errors, it could be tiled to build larger logical processors with lower total qubit count than surface-code patches of equivalent distance.
  • The classical-code protection of measurement results might combine with other time-optimization methods such as lattice surgery to produce still larger speedups.

Load-bearing premise

The combinatorial counting argument with flag qubits actually produces circuits that measure any stabilizer while tolerating exactly one fault and without leaving any undetected errors that would require extra qubits or assumptions.

What would settle it

An explicit circuit diagram or fault-simulation result for a weight-8 stabilizer showing the claimed ancilla count and confirming that every single-fault pattern is detected, or a direct comparison of logical error rates between the proposed six-qubit distance-four code and a distance-five surface-code patch under the same noise model.

Figures

Figures reproduced from arXiv: 2605.12385 by Prithviraj Prabhu.

Figure 1
Figure 1. Figure 1 [PITH_FULL_IMAGE:figures/full_fig_p005_1.png] view at source ↗
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Figure 3. Figure 3 [PITH_FULL_IMAGE:figures/full_fig_p005_3.png] view at source ↗
Figure 5
Figure 5. Figure 5 [PITH_FULL_IMAGE:figures/full_fig_p005_5.png] view at source ↗
Figure 3
Figure 3. Figure 3 [PITH_FULL_IMAGE:figures/full_fig_p010_3.png] view at source ↗
Figure 4
Figure 4. Figure 4 [PITH_FULL_IMAGE:figures/full_fig_p011_4.png] view at source ↗
Figure 5
Figure 5. Figure 5 [PITH_FULL_IMAGE:figures/full_fig_p012_5.png] view at source ↗
Figure 5
Figure 5. Figure 5 [PITH_FULL_IMAGE:figures/full_fig_p013_5.png] view at source ↗
Figure 1
Figure 1. Figure 1 [PITH_FULL_IMAGE:figures/full_fig_p019_1.png] view at source ↗
Figure 1.1
Figure 1.1. Figure 1.1: Qubit and gate counts (T) needed for academic and commercial quantum use [SWM+24]. Quantum algorithms decomposed into a sequence of Clifford and T gates assume only the latter is computationally expensive. To ensure reliable results for large and long computations, qubits are protected by error-correcting codes. When using the surface code, we show the minimum code distance needed to achieve an algorithm… view at source ↗
Figure 1
Figure 1. Figure 1 [PITH_FULL_IMAGE:figures/full_fig_p022_1.png] view at source ↗
Figure 1.2
Figure 1.2. Figure 1.2: Progress of experimental demonstrations of quantum error correction on superconducting, [PITH_FULL_IMAGE:figures/full_fig_p023_1_2.png] view at source ↗
Figure 1
Figure 1. Figure 1 [PITH_FULL_IMAGE:figures/full_fig_p025_1.png] view at source ↗
Figure 1.3
Figure 1.3. Figure 1.3: Layered architecture of a fault-tolerant quantum computer [ [PITH_FULL_IMAGE:figures/full_fig_p026_1_3.png] view at source ↗
Figure 1.4
Figure 1.4. Figure 1.4: Three different models of fault tolerance against faults that corrupt measurement results. [PITH_FULL_IMAGE:figures/full_fig_p027_1_4.png] view at source ↗
Figure 1
Figure 1. Figure 1 [PITH_FULL_IMAGE:figures/full_fig_p027_1.png] view at source ↗
Figure 1.5
Figure 1.5. Figure 1.5: Overview of the thesis. New results are indicated by a [PITH_FULL_IMAGE:figures/full_fig_p029_1_5.png] view at source ↗
Figure 1
Figure 1. Figure 1 [PITH_FULL_IMAGE:figures/full_fig_p034_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: a [PITH_FULL_IMAGE:figures/full_fig_p037_2.png] view at source ↗
Figure 2.1
Figure 2.1. Figure 2.1: (a) Function of a flag scheme. Errors in a non-fault-tolerant circuit can be made to [PITH_FULL_IMAGE:figures/full_fig_p038_2_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: b [PITH_FULL_IMAGE:figures/full_fig_p038_2.png] view at source ↗
Figure 2.2
Figure 2.2. Figure 2.2: Historical progression of stabilizer measurement circuits, illustrated by a weight- [PITH_FULL_IMAGE:figures/full_fig_p039_2_2.png] view at source ↗
Figure 2
Figure 2. Figure 2: b [PITH_FULL_IMAGE:figures/full_fig_p041_2.png] view at source ↗
Figure 2.3
Figure 2.3. Figure 2.3: Flag sequences for distance-three fault-tolerant syndrome measurement, using [PITH_FULL_IMAGE:figures/full_fig_p042_2_3.png] view at source ↗
Figure 2
Figure 2. Figure 2: a [PITH_FULL_IMAGE:figures/full_fig_p043_2.png] view at source ↗
Figure 2.4
Figure 2.4. Figure 2.4: (a) Circuit to measure an X⊗6 stabilizer, CSS fault-tolerant to distance three. (b) Circuit to prepare a six-qubit cat state, fault-tolerant to distance three. ±Z ±Z ±Z ±Z ±Z |+i |0i |0i |0i |0i |0i ··· ±X [PITH_FULL_IMAGE:figures/full_fig_p044_2_4.png] view at source ↗
Figure 2.5
Figure 2.5. Figure 2.5: Distance-three fault-tolerant syndrome bit measurement only needs three flag qubits. [PITH_FULL_IMAGE:figures/full_fig_p044_2_5.png] view at source ↗
Figure 2.6
Figure 2.6. Figure 2.6: Distance-three error correction is not possible with one flag qubit. Either (top) the [PITH_FULL_IMAGE:figures/full_fig_p044_2_6.png] view at source ↗
Figure 2
Figure 2. Figure 2: b [PITH_FULL_IMAGE:figures/full_fig_p045_2.png] view at source ↗
Figure 2
Figure 2. Figure 2 [PITH_FULL_IMAGE:figures/full_fig_p046_2.png] view at source ↗
Figure 2.7
Figure 2.7. Figure 2.7: Simulation of the noisy measurement of an [PITH_FULL_IMAGE:figures/full_fig_p047_2_7.png] view at source ↗
Figure 2
Figure 2. Figure 2: c [PITH_FULL_IMAGE:figures/full_fig_p048_2.png] view at source ↗
Figure 2
Figure 2. Figure 2 [PITH_FULL_IMAGE:figures/full_fig_p049_2.png] view at source ↗
Figure 2.8
Figure 2.8. Figure 2.8: Distance-five CSS stabilizer measurement with slow qubit reset for [PITH_FULL_IMAGE:figures/full_fig_p050_2_8.png] view at source ↗
Figure 2.9
Figure 2.9. Figure 2.9: Distance-five syndrome measurement with slow qubit reset for a weight- [PITH_FULL_IMAGE:figures/full_fig_p050_2_9.png] view at source ↗
Figure 2.10
Figure 2.10. Figure 2.10: Distance-seven syndrome measurement with slow qubit reset for a weight- [PITH_FULL_IMAGE:figures/full_fig_p051_2_10.png] view at source ↗
Figure 2
Figure 2. Figure 2 [PITH_FULL_IMAGE:figures/full_fig_p054_2.png] view at source ↗
Figure 3.1
Figure 3.1. Figure 3.1: Distance-three fault-tolerant cat state preparation circuits. Note that, with fast reset, [PITH_FULL_IMAGE:figures/full_fig_p055_3_1.png] view at source ↗
Figure 3
Figure 3. Figure 3: a [PITH_FULL_IMAGE:figures/full_fig_p056_3.png] view at source ↗
Figure 2
Figure 2. Figure 2: b [PITH_FULL_IMAGE:figures/full_fig_p056_2.png] view at source ↗
Figure 3.2
Figure 3.2. Figure 3.2: Circuit to prepare a 15-qubit cat state by adaptive error correction, fault-tolerant to distance three. Labels on the thick black wire indicate which data qubit in the block is being addressed as the control or target of the CNOT. If a fault occurs while preparing the cat state on the |+⟩ qubit, it is partially localized by the red flag ancilla. The measurement result of this flag then determines a set o… view at source ↗
Figure 3
Figure 3. Figure 3 [PITH_FULL_IMAGE:figures/full_fig_p057_3.png] view at source ↗
Figure 3.3
Figure 3.3. Figure 3.3: If the red ancilla flag in [PITH_FULL_IMAGE:figures/full_fig_p058_3_3.png] view at source ↗
Figure 3
Figure 3. Figure 3 [PITH_FULL_IMAGE:figures/full_fig_p059_3.png] view at source ↗
Figure 3
Figure 3. Figure 3 [PITH_FULL_IMAGE:figures/full_fig_p060_3.png] view at source ↗
Figure 3.4
Figure 3.4. Figure 3.4: Reduced number of ZZ parity measurements required to prepare a cat state fault￾tolerantly. We first consider non-local connectivity, proving that n + ⌈log2(n/3)⌉ measurements are sufficient to tolerate one fault. By random search, we found sequences of parity checks that can tolerate two or three faults too. In the second graph, qubits are laid on a 1-D chain, and CNOT gates are local. The number of pari… view at source ↗
Figure 3
Figure 3. Figure 3 [PITH_FULL_IMAGE:figures/full_fig_p065_3.png] view at source ↗
Figure 3.5
Figure 3.5. Figure 3.5: Rates of residual errors of weight w ∈ {1, 2, 3, 4} after size-eight cat state preparation, for physical error rates p ∈ [5 × 10−3 , 2.5 × 10−2 ].The methods used consist of sequences from [PITH_FULL_IMAGE:figures/full_fig_p066_3_5.png] view at source ↗
Figure 2
Figure 2. Figure 2: b [PITH_FULL_IMAGE:figures/full_fig_p070_2.png] view at source ↗
Figure 4.1
Figure 4.1. Figure 4.1: Fault-tolerant circuit for encoding the operator [PITH_FULL_IMAGE:figures/full_fig_p071_4_1.png] view at source ↗
Figure 4.2
Figure 4.2. Figure 4.2: Fault-tolerant preparation of a [[7, 1, 3]] |0⟩L state. (a) Circuit to ideally prepare the |0L⟩ state of the Steane code, needing nine CNOT gates over three rounds. (b) Condensed circuit to fault-tolerantly and deterministically prepare the |0L⟩ state of the Steane code. This circuit uses the same number of CNOTs as in (c), but has circuit depth seven, as opposed to 21 in (c). (c) Circuit to fault-tolera… view at source ↗
Figure 4
Figure 4. Figure 4 [PITH_FULL_IMAGE:figures/full_fig_p073_4.png] view at source ↗
Figure 4.3
Figure 4.3. Figure 4.3: Rates of residual weight-1 and logical errors after preparing [PITH_FULL_IMAGE:figures/full_fig_p075_4_3.png] view at source ↗
Figure 4.4
Figure 4.4. Figure 4.4: Rates of residual weight-1 and logical errors after preparing [PITH_FULL_IMAGE:figures/full_fig_p076_4_4.png] view at source ↗
Figure 4.5
Figure 4.5. Figure 4.5: Flag-based circuits to encode high-weight [PITH_FULL_IMAGE:figures/full_fig_p077_4_5.png] view at source ↗
Figure 4.6
Figure 4.6. Figure 4.6: Comparison of the rates of residual errors between the [PITH_FULL_IMAGE:figures/full_fig_p079_4_6.png] view at source ↗
Figure 5
Figure 5. Figure 5 [PITH_FULL_IMAGE:figures/full_fig_p081_5.png] view at source ↗
Figure 5.1
Figure 5.1. Figure 5.1: Codes considered in this paper, with associated distance-four fault-tolerant [PITH_FULL_IMAGE:figures/full_fig_p082_5_1.png] view at source ↗
Figure 5.2
Figure 5.2. Figure 5.2: Planar layout of 16 data and 9 ancilla qubits, in black and red respectively. CNOT gates are allowed along the edges. Grey edges are required for the surface code, and green edges between ancillas are required for the new codes in this paper. 64 [PITH_FULL_IMAGE:figures/full_fig_p082_5_2.png] view at source ↗
Figure 5
Figure 5. Figure 5 [PITH_FULL_IMAGE:figures/full_fig_p083_5.png] view at source ↗
Figure 5.3
Figure 5.3. Figure 5.3: Summary of results. For short computations, the probability of a logical error in the [PITH_FULL_IMAGE:figures/full_fig_p084_5_3.png] view at source ↗
Figure 5
Figure 5. Figure 5 [PITH_FULL_IMAGE:figures/full_fig_p084_5.png] view at source ↗
Figure 5
Figure 5. Figure 5 [PITH_FULL_IMAGE:figures/full_fig_p085_5.png] view at source ↗
Figure 5
Figure 5. Figure 5 [PITH_FULL_IMAGE:figures/full_fig_p086_5.png] view at source ↗
Figure 5.4
Figure 5.4. Figure 5.4: (a) A distance-4 stabilizer measurement circuit contains ancilla preparation, CNOTs, measurement and a recovery. (b) Rules for fault tolerance. One fault should be corrected to an error of X/Z weight at most one—this is sufficient for distance 3. Two faults should either be rejected (denoted by the red R) or result in an error of weight two. 5 6 7 1 2 3 4 |0i |+i |0i ±Z ±X ±Z (a) 5 6 7 1 2 3 4 5 6 7 1 2 … view at source ↗
Figure 5.5
Figure 5.5. Figure 5.5: (a) Circuit to measure a weight-four X stabilizer fault-tolerantly to distance-four, satisfying the locality constraints in (b). The ±Z measurements are used to flag mid-circuit faults. Gates bunched together can be performed in parallel. (b) Two layouts for measuring stabilizers in the sequences of [PITH_FULL_IMAGE:figures/full_fig_p087_5_5.png] view at source ↗
Figure 5.6
Figure 5.6. Figure 5.6: (a) Circuit to measure a weight-eight X stabilizer fault-tolerantly to distance-four, satisfying the locality constraints in (b). One fault is corrected to at most a weight-one error, but two or more faults may either be corrected, or detected resulting in rejection. The resulting flag outcomes for corrections and rejection are tabulated in Appendix .3. (b) Two layouts for measuring stabilizers in the se… view at source ↗
Figure 5
Figure 5. Figure 5: a [PITH_FULL_IMAGE:figures/full_fig_p089_5.png] view at source ↗
Figure 5.7
Figure 5.7. Figure 5.7: Fault-tolerant error correction with the three bit repetition code [PITH_FULL_IMAGE:figures/full_fig_p090_5_7.png] view at source ↗
Figure 5
Figure 5. Figure 5: a [PITH_FULL_IMAGE:figures/full_fig_p090_5.png] view at source ↗
Figure 5.8
Figure 5.8. Figure 5.8: (a) A stabilizer measurement sequence (SMS) consists of multiple time steps of parallel [PITH_FULL_IMAGE:figures/full_fig_p091_5_8.png] view at source ↗
Figure 5
Figure 5. Figure 5 [PITH_FULL_IMAGE:figures/full_fig_p093_5.png] view at source ↗
Figure 5.9
Figure 5.9. Figure 5.9: O(p 3 ) scaling of X logical error rate and O(p 2 ) scaling of rejection rate, with error bars, for the distance-four codes. The distance-three and distance-five surface codes are shown for comparison. The new codes have logical error rate per time step as low as 1/10th the distance-five surface code. The distance-four surface code is as low as 1/100. 76 [PITH_FULL_IMAGE:figures/full_fig_p094_5_9.png] view at source ↗
Figure 5
Figure 5. Figure 5 [PITH_FULL_IMAGE:figures/full_fig_p096_5.png] view at source ↗
Figure 5.10
Figure 5.10. Figure 5.10: Probability of X logical error (solid) and acceptance (dotted) for t time steps of error correction on six codes, as a function of physical error rate (row) and desired logical qubits (column). The three colored curves correspond to the k = 2, k = 4 and k = 6 codes and the three gray curves are the surface codes. The graphs for few time steps look like step functions because the code patches are checked… view at source ↗
Figure 5.11
Figure 5.11. Figure 5.11: CNOT depth at which each code has accumulated [PITH_FULL_IMAGE:figures/full_fig_p100_5_11.png] view at source ↗
Figure 5
Figure 5. Figure 5 [PITH_FULL_IMAGE:figures/full_fig_p100_5.png] view at source ↗
Figure 5
Figure 5. Figure 5: a [PITH_FULL_IMAGE:figures/full_fig_p101_5.png] view at source ↗
Figure 5.12
Figure 5.12. Figure 5.12: A degree-four layout for flag-fault-tolerant error correction of the [PITH_FULL_IMAGE:figures/full_fig_p102_5_12.png] view at source ↗
Figure 5
Figure 5. Figure 5 [PITH_FULL_IMAGE:figures/full_fig_p102_5.png] view at source ↗
Figure 5
Figure 5. Figure 5: a [PITH_FULL_IMAGE:figures/full_fig_p103_5.png] view at source ↗
Figure 5.13
Figure 5.13. Figure 5.13: Syndrome graphs passed to the union-find decoder. All the vertices labeled [PITH_FULL_IMAGE:figures/full_fig_p104_5_13.png] view at source ↗
Figure 5
Figure 5. Figure 5 [PITH_FULL_IMAGE:figures/full_fig_p105_5.png] view at source ↗
Figure 5.14
Figure 5.14. Figure 5.14: (a) Stabilizers of the [[16, 6, 4]] code. The [[16, 4, 2, 4]] code is derived by assigning two of the logical qubits as gauge qubits. (b) The two logical qubits chosen as gauges are the horizontal and vertical weight-four operators. By stabilizer equivalence, every column (row) of four qubits is a representation of the vertical (horizontal) gauge. These groups of data qubits are denoted by the letters a… view at source ↗
Figure 5.15
Figure 5.15. Figure 5.15: Implementation of quantum error correction with a [PITH_FULL_IMAGE:figures/full_fig_p107_5_15.png] view at source ↗
Figure 5
Figure 5. Figure 5 [PITH_FULL_IMAGE:figures/full_fig_p107_5.png] view at source ↗
Figure 5.16
Figure 5.16. Figure 5.16: Rejection rates (top two) and logical error rates (bottom three) per time step, when [PITH_FULL_IMAGE:figures/full_fig_p108_5_16.png] view at source ↗
Figure 5.17
Figure 5.17. Figure 5.17: Fault-tolerant versions of physical CZ and SWAP gates. (a) Performing a SWAP [PITH_FULL_IMAGE:figures/full_fig_p109_5_17.png] view at source ↗
Figure 5
Figure 5. Figure 5: a [PITH_FULL_IMAGE:figures/full_fig_p109_5.png] view at source ↗
Figure 5
Figure 5. Figure 5 [PITH_FULL_IMAGE:figures/full_fig_p110_5.png] view at source ↗
Figure 6.1
Figure 6.1. Figure 6.1: General model of Pauli-based computation. A quantum algorithm can be written [PITH_FULL_IMAGE:figures/full_fig_p113_6_1.png] view at source ↗
Figure 6.2
Figure 6.2. Figure 6.2: (a) Old protocol for temporally encoded lattice surgery of a PP set of size-2, where [PITH_FULL_IMAGE:figures/full_fig_p113_6_2.png] view at source ↗
Figure 6.3
Figure 6.3. Figure 6.3: Lattice surgery implementation of an X ⊗ X measurement between two logical qubits encoded in dx = 3, dz = 5 surface code patches. Note that X (Z) stabilizers are represented by red (blue) plaquettes. Prior to measuring X ⊗ X, yellow data qubits in the routing region are prepared in the |0⟩ state. The X ⊗ X measurement outcome is then obtained by measuring the X-stabilizers (shown with white ancillas) in … view at source ↗
Figure 6.4
Figure 6.4. Figure 6.4: The best average runtime per Pauli (in units of syndrome measurement rounds) for all [PITH_FULL_IMAGE:figures/full_fig_p128_6_4.png] view at source ↗
Figure 7.1
Figure 7.1. Figure 7.1: Circuit used in a 15-to-1 magic state distillation protocol expressed as a sequence of multi-qubit non-Clifford gates. The circuit above is the Hadamard-transformed version of [PITH_FULL_IMAGE:figures/full_fig_p131_7_1.png] view at source ↗
Figure 7.2
Figure 7.2. Figure 7.2: (a) Circuit for performing a π/8 multi-qubit Pauli measurement. The circuit requires a |TX⟩ = H|T⟩ resource state, and a Clifford correction may be required depending on the P ⊗ X measurement outcome. (b) Circuit for performing a Clifford gate using an ancilla prepared in |0⟩. Both circuits are adapted from Ref. [Lit19a]. given that Xπ/4ZX† π/4 = −Y , Xπ/2ZX† π/2 = −Z , X3π/4ZX† 3π/4 = Y . (7.3) For prot… view at source ↗
Figure 7.3
Figure 7.3. Figure 7.3: Circuit gadget for an auto-corrected non-Clifford gate. The circuit does not require [PITH_FULL_IMAGE:figures/full_fig_p138_7_3.png] view at source ↗
Figure 7.4
Figure 7.4. Figure 7.4: Layouts of logical qubits for TELS-assisted [PITH_FULL_IMAGE:figures/full_fig_p142_7_4.png] view at source ↗
Figure 7.5
Figure 7.5. Figure 7.5: Layouts of logical qubits for parallelized TELS-based [PITH_FULL_IMAGE:figures/full_fig_p143_7_5.png] view at source ↗
Figure 7.6
Figure 7.6. Figure 7.6: (a) On the layout of Fig [PITH_FULL_IMAGE:figures/full_fig_p144_7_6.png] view at source ↗
Figure 7.7
Figure 7.7. Figure 7.7: Time dynamics of a TELS-assisted distillation factory. Here we consider a 15-to-1 [PITH_FULL_IMAGE:figures/full_fig_p147_7_7.png] view at source ↗
Figure 7.8
Figure 7.8. Figure 7.8: Round robin scheduling of deterministic-time distillation tiles in a factory. This [PITH_FULL_IMAGE:figures/full_fig_p150_7_8.png] view at source ↗
Figure 2
Figure 2. Figure 2: a [PITH_FULL_IMAGE:figures/full_fig_p165_2.png] view at source ↗
Figure 9
Figure 9. Figure 9: Two-error-detecting fault-tolerant circuit for the preparation of a weight- [PITH_FULL_IMAGE:figures/full_fig_p166_9.png] view at source ↗
Figure 10
Figure 10. Figure 10: (a) Logarithmic-depth preparation of an eight-qubit cat state shows there are six possible [PITH_FULL_IMAGE:figures/full_fig_p166_10.png] view at source ↗
Figure 11
Figure 11. Figure 11: (a) Distance-4 fault-tolerant circuit for measuring a weight-8 stabilizer on a square lattice [PITH_FULL_IMAGE:figures/full_fig_p168_11.png] view at source ↗
Figure 5
Figure 5. Figure 5: a [PITH_FULL_IMAGE:figures/full_fig_p168_5.png] view at source ↗
Figure 5
Figure 5. Figure 5 [PITH_FULL_IMAGE:figures/full_fig_p169_5.png] view at source ↗
Figure 12
Figure 12. Figure 12: We show the classical codes achieving the lowest average runtime per Pauli for [PITH_FULL_IMAGE:figures/full_fig_p178_12.png] view at source ↗
Figure 13
Figure 13. Figure 13: We show the classical codes achieving the lowest average runtime per Pauli for [PITH_FULL_IMAGE:figures/full_fig_p179_13.png] view at source ↗
Figure 14
Figure 14. Figure 14: Layouts of logical qubits for lattice-surgery-based [PITH_FULL_IMAGE:figures/full_fig_p193_14.png] view at source ↗
Figure 15
Figure 15. Figure 15: Layouts of logical qubits for lattice-surgery-based [PITH_FULL_IMAGE:figures/full_fig_p195_15.png] view at source ↗
Figure 16
Figure 16. Figure 16: Layouts of logical qubits for lattice-surgery-based [PITH_FULL_IMAGE:figures/full_fig_p197_16.png] view at source ↗
read the original abstract

Quantum computation holds the promise of solving certain complex problems exponentially faster than classical computers. However, the high prevalent noise in current quantum devices impedes the accurate execution of even basic algorithms. This can be remedied by protecting quantum information with a quantum error-correcting code, where the logical information of an algorithmic qubit is spread across multiple physical qubits. Individual quantum errors are then located and corrected by the fault-tolerant measurement of multi-qubit stabilizer operators (parity checks). Unfortunately, error correction and fault tolerance both impose large demands on the qubit overhead: hundreds to thousands of physical qubits per logical qubit. We reduce the spacetime cost of fault tolerance by redesigning key building blocks of an error-corrected quantum computer. First, we develop a combinatorial proof with flag fault tolerance that exponentially reduces the extra qubits needed to measure a stabilizer of any size, while tolerating one fault. We leverage these proofs to then design state preparation circuits for the Steane and Golay codes with 100% yield. Next, we improve error correction on a planar layout by showing that a distance-four code encoding six logical qubits protects information as well as the distance-five surface code, using one-tenth as many physical qubits. Finally, we optimize the time overhead of logical gates in surface code quantum computers by protecting measurement results with a classical code, cutting computation time by a factor of two to six. Our hardware-agnostic optimizations of fault tolerance overheads thus suggest new routes to advance the timeline of error-free quantum computing.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 2 minor

Summary. The manuscript claims four main overhead reductions for fault-tolerant quantum computing: a combinatorial construction with flag qubits that exponentially cuts ancilla overhead for measuring arbitrary-weight stabilizers while tolerating one fault; 100% yield state-preparation circuits for the Steane and Golay codes; a distance-4 code encoding six logical qubits that matches the protection of the distance-5 surface code at one-tenth the physical-qubit cost; and a classical-code protection of measurement outcomes that reduces surface-code logical-gate time by a factor of 2–6.

Significance. If the central constructions hold, the work would materially lower both qubit and spacetime overheads for error correction on near-term hardware, offering concrete routes to earlier fault-tolerant operation. The flag-based combinatorial method and the six-logical-qubit planar code are the most load-bearing claims; reproducible verification of either would constitute a notable advance.

major comments (2)
  1. [Abstract / main construction] The headline exponential ancilla reduction rests on the combinatorial proof with flag fault tolerance asserted in the abstract. No derivation, circuit diagram, or explicit error-propagation analysis is supplied, so it is impossible to confirm that the construction remains fault-tolerant for arbitrary stabilizer weight, introduces no undetected error channels that reach the data, or scales without additional size-dependent verification qubits.
  2. [Distance-4 code section] The distance-4 six-logical-qubit code is claimed to protect information equivalently to the distance-5 surface code while using one-tenth the physical qubits. No distance calculation, logical-error-rate comparison, or layout diagram is provided, leaving the quantitative claim unsupported.
minor comments (2)
  1. [Abstract] The abstract states 'combinatorial proofs' and 'precise performance numbers' yet contains neither equations nor tables; the manuscript should include at least one explicit small-weight example with circuit and fault table.
  2. [State-preparation section] The 100% yield claim for Steane and Golay state preparation is stated without the corresponding circuit diagrams or yield calculation.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for their careful reading of our manuscript and for highlighting areas where additional details would improve clarity. We respond to the major comments point-by-point below. We will revise the manuscript to incorporate more explicit derivations, diagrams, and analyses as requested.

read point-by-point responses

  1. Referee: [Abstract / main construction] The headline exponential ancilla reduction rests on the combinatorial proof with flag fault tolerance asserted in the abstract. No derivation, circuit diagram, or explicit error-propagation analysis is supplied, so it is impossible to confirm that the construction remains fault-tolerant for arbitrary stabilizer weight, introduces no undetected error channels that reach the data, or scales without additional size-dependent verification qubits.

    Authors: We agree that the presentation of the combinatorial proof can be strengthened with more explicit details. The construction is described in the main body of the paper, but we will add a full step-by-step derivation of the flag qubit selection for arbitrary stabilizer weights, include example circuit diagrams, and provide an error-propagation analysis. This analysis will demonstrate that the method tolerates one fault without undetected errors propagating to the data qubits, and that the number of flag qubits does not grow with stabilizer size due to the combinatorial covering. We believe this will address the concerns regarding verification qubits and scalability. revision: yes

  2. Referee: [Distance-4 code section] The distance-4 six-logical-qubit code is claimed to protect information equivalently to the distance-five surface code while using one-tenth the physical qubits. No distance calculation, logical-error-rate comparison, or layout diagram is provided, leaving the quantitative claim unsupported.

    Authors: The distance-4 code and its comparison to the surface code are discussed in the relevant section, but we acknowledge the need for supporting calculations and visuals. In the revised manuscript, we will include an explicit proof or calculation of the code distance, numerical simulations or bounds on logical error rates under standard noise models, and a clear layout diagram illustrating the physical qubit arrangement and the factor of ten reduction in overhead compared to a distance-5 surface code patch. This will substantiate the equivalence in protection. revision: yes

Circularity Check

0 steps flagged

No circularity: novel combinatorial constructions and code designs stand independently

full rationale

The paper advances new designs for fault-tolerant quantum error correction, including a combinatorial proof using flag qubits for stabilizer measurement with exponential ancilla reduction, 100% yield state-preparation circuits for Steane/Golay codes, a distance-4 code encoding six logical qubits, and classical-code protection for measurement results. No equations, fitted parameters, or self-referential definitions appear in the provided text. Claims do not reduce by construction to inputs (e.g., no 'prediction' that is a renamed fit, no ansatz smuggled via self-citation, no uniqueness theorem imported from prior author work). The derivation chain consists of original constructions presented as independent contributions, making the paper self-contained against external benchmarks with no load-bearing circular steps.

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 0 invented entities

Only the abstract is available; no explicit free parameters, ad-hoc axioms, or new physical entities are identifiable from the given text.

axioms (1)
  • domain assumption Standard assumptions of quantum mechanics, stabilizer formalism, and fault-tolerant quantum computation
    The work presupposes the established framework of quantum error correction without introducing new foundational axioms.

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