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arxiv: 2605.19405 · v1 · pith:J57STKHOnew · submitted 2026-05-19 · 💻 cs.AR

A complete discussion on fully reconfigurable, digital, scalable, graph and sparsity-aware near-memory accelerator for graph neural networks

Siddhartha Raman Sundara Raman , Lizy John , Jaydeep P. Kulkarni This is my paper

Pith reviewed 2026-05-20 02:19 UTC · model grok-4.3

classification 💻 cs.AR
keywords graph neural networksnear-memory acceleratorprocessing-in-memorysparsity-aware designreconfigurable architecturedigital hardware acceleratorgraph aggregation
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The pith

NEM-GNN is a digital processing-in-memory design that accelerates graph neural networks through sparsity-aware near-memory aggregation and early compute termination.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper seeks to establish that a fully reconfigurable, DAC/ADC-less architecture can overcome the energy waste from irregular memory accesses during graph aggregation in neural networks. Standard processors and prior accelerators move large amounts of sparse data repeatedly, which dominates power consumption for real-world graphs. If the approach holds, it would allow GNN models for tasks like molecular analysis to run with far lower energy per inference while scaling to bigger graphs on chip. The design relies on a broadcast execution model that triggers operations only when data is ready, combined with pre-computation steps on flexible hardware blocks.

Core claim

NEM-GNN demonstrates a scalable digital near-memory accelerator that performs graph and sparsity-aware aggregation using a compute-as-soon-as-ready execution model together with broadcast communication, early termination, and reconfigurable pre-computation to eliminate analog conversion overheads and reduce data movement.

What carries the argument

The compute-as-soon-as-ready (CAR) and broadcast-based execution model for near-memory aggregation, which activates operations on graph nodes only when their inputs arrive and propagates results efficiently across the memory array.

If this is right

  • GNN training and inference for large citation or molecular graphs becomes feasible with substantially lower total energy.
  • Hardware designs can achieve higher operations per square millimeter without relying on analog circuits.
  • Reconfigurable components allow the same accelerator to adapt to different graph structures and sparsity levels at runtime.
  • System-on-chip integration simplifies because the design avoids dedicated analog blocks and uses standard digital flows.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The broadcast model may prove especially effective for graphs with community structure, suggesting targeted benchmarks on social or biological networks.
  • Similar sparsity-aware near-memory techniques could transfer to other irregular workloads such as sparse linear algebra or graph analytics outside neural networks.
  • Scaling the design to multi-chip modules would require new mechanisms to handle inter-chip graph partitioning while preserving the early-termination benefits.

Load-bearing premise

The large reported gains in speed and efficiency rest on comparisons to prior accelerators that use matching technology nodes, identical workloads, and unbiased baseline implementations.

What would settle it

Fabricating NEM-GNN and the compared prior accelerators in the same semiconductor process and measuring their performance and energy on identical GNN benchmarks would directly test whether the claimed 80-230x speedups and 850-1134x energy gains hold.

Figures

Figures reproduced from arXiv: 2605.19405 by Jaydeep P. Kulkarni, Lizy John, Siddhartha Raman Sundara Raman.

Figure 1
Figure 1. Figure 1: Undirected, unweighted graph with 5 nodes and 6 edges passing through 1-layer GCN. Combination showing MAC between dense feature and weight matrices, aggregation showing MAC between sparse D-1, adjacency matrices to generate final MAC before ReLU, softmax function Attention Networks (GAT), and GraphSage [32], [33], are being extensively researched. These explorations are geared towards unraveling specific … view at source ↗
Figure 2
Figure 2. Figure 2: Landscape of Graph neural network based acceleration. The prior works are predominantly dedicated accelerators requiring periodic host-accelerator interaction. These are further classified into Von-Neumann, ReRAM based PIM, DRAM/HBM based PIM. The proposed accelerator is not dedicated and reuses cache in CPUs to perform GCNs. The bitcells for PIM designs are also shown the BL to half of the operating volta… view at source ↗
Figure 3
Figure 3. Figure 3: a) ReRAM approaches (i) use DAC for incoming H conversion to an equivalent analog value (ii) store weights of GNN in binary scaled fashion (iii) utilize current buffer+reductor to perform current-based summation and ADC to generate H*W b) Qualitative comparison between ReRAM approaches and NEM-GNN c) A summary of the identified issues and the proposed solutions execution between combination and aggregation… view at source ↗
Figure 4
Figure 4. Figure 4: a) NEM-GNN is realized by repurposing the L1 cache for in-memory compute, with minimal near-memory peripheral logic added to each CPU core. b) In an L1 cache, consisting of 2 banks, shift and add are present at a granularity of 1 per every 8 columns per bank, with 1 adder reduc￾tion/multiplier per bank, and other dedicated logic shared across the entire cache. c) DRAM is accessed to transfer weights/ featu… view at source ↗
Figure 5
Figure 5. Figure 5: a) Compute array organization for NEM-C1: 2 tiles with 4 banks in each tile, with bit-serial PIM performed between H mapped onto RWL and W replicated across both tiles is shown for illustration. 2-bit 8-element H and 1-bit 8*3 weight matrix is shown with Hji n indicating nth bit of j th element for ith node. b) W is stored in 8T SRAM bitcell in L1 cache, and H is mapped onto RWL. RBL discharge is used as a… view at source ↗
Figure 6
Figure 6. Figure 6: NEM-C2: Early compute termination (ECT) occurs once one of the bit-serial H element bits is found to be 1, without data replication requirement. ECT data path checks for non-zero H bit in step 1 and writes the non-zero dot product into ECT register in step 2. In parallel, PIM datapath computes partial dot products in step 1 and subsequently stores them in the ECT register in step 2. This value is broadcast… view at source ↗
Figure 7
Figure 7. Figure 7: Incoming graphs are mapped onto different engines based on graph-connectivity (graph-aware) and read-out of adjacency matrix (stored in Compressed Sparse Row Format) to eliminate unnecessary compute (sparsity-aware). UWC engine: Aggregation of unweighted graphs by reading the adjacency matrix and NodeProc register (indicating the node being processed by combination) to fill the update index register in ste… view at source ↗
Figure 8
Figure 8. Figure 8: a) UWC engine: Aggregation for an unweighted, directed graph begins with reading the adjacency vector corresponding to Node Proc in Step 1, identifying outgoing nodes in step 2, and storing in Update Index register, using adders to aggregate the incoming combination vector onto the nodes in Update Index register in step 3. Each adjacency matrix element is of the form (i,j), where i/j represents the neighbo… view at source ↗
Figure 9
Figure 9. Figure 9: a) Weighted, directed aggregation, with adjacency matrix storing the weights of graphs and the direction in the case of directed graphs. The direction is read out in step 1 to check for outgoing nodes in step 2 and aggregation with the incoming combination vector is achieved using near-memory multipliers and adders in step 3 b) Weighted, undirected aggregation follows the same datapath as the directed one,… view at source ↗
Figure 10
Figure 10. Figure 10: D-generator and control logic: Degree matrix generator for generating D-1 using a sparsity-aware approach that (i) performs element-by-vector (instead of vector-by-vector) mul￾tiplication for every row, and (ii) reduces the number of computations/area by a factor of 2n/n. Auxiliary control for ReLU and softmax is shown in the right-most figure. undergoes immediate updates. This update involves the accumul… view at source ↗
Figure 11
Figure 11. Figure 11: Benchmarks: Datasets for GNNs, the number of nodes/edges/features in each of them, and the network used for GCN/GAT/GraphSage networks. Micro-architecture of NEM-GNN with the additional near-memory logic requiring 2% of AMD’s Zen3 CPU per-core area 6.2 Graph and sparsity-aware WC engine for Weighted graphs For weighted graphs, the adjacency matrix (A) is re-purposed to store the weight of interaction betw… view at source ↗
Figure 12
Figure 12. Figure 12: Performance comparison normalized to NEM-C3 for GCN, GAT and GraphSage. UWC engine is used for aggregation, NEM-C1, NEM-C2, and NEM-C3 are used for combination [PITH_FULL_IMAGE:figures/full_fig_p019_12.png] view at source ↗
Figure 13
Figure 13. Figure 13: Throughput comparison measured in GOPS for GCN, GAT, and GraphSage. UWC engine is used for aggregation, NEM-C1, NEM-C2, and NEM-C3 are used for combination. Tesla v100, with 64 CUDA cores per streaming multiprocessor (SM) and an operating frequency of 1.5GHz, with 96KB L1 cache per SM, 6MB L2 cache and 16GB HBM2. AWB-GCN’s performance is obtained from its implementation on Intel D5005 FPGA with DRAM capac… view at source ↗
Figure 14
Figure 14. Figure 14: Energy comparison for GCN, GAT and GraphSage. UWC engine is used for aggregation, NEM-C1, NEM-C2, and NEM-C3 are used for combination [PITH_FULL_IMAGE:figures/full_fig_p021_14.png] view at source ↗
Figure 15
Figure 15. Figure 15: Energy efficiency comparison for GCN, GAT and GraphSage. UWC engine is used for aggregation, NEM-C1, NEM-C2, and NEM-C3 are used for combination. the lower power. In comparison to ReFLIP, NEM-GNN has the following advantages: (i) No power￾hungry DAC/ADC requirements (ii) Lower write/read voltages for SRAM than ReRAM (iii) No additional write required to store back into the compute array post combination r… view at source ↗
Figure 16
Figure 16. Figure 16: a) Compute density comparison across PIM designs b) NEM-C2 performance variation with number of Hs c) NEM-C2 energy variation with bit resolution, average bit-position for first ’1’ d) Compute density, area for CS1, CS2 and CS3 e) Energy, efficiency for CS1, CS2, and CS3 [PITH_FULL_IMAGE:figures/full_fig_p022_16.png] view at source ↗
Figure 17
Figure 17. Figure 17: a) Performance/b) energy improvement of NEM-C3 relative to PIM-GCN, c) Speedup/energy improvement relative to Challapalle et.al, d) Speedup, e) Energy of NEM-C3 relative to PEDAL to NEM-C1 based design. The compute density is ∼7-8x that of ReFLIP, due to the elimination of bulky DACs/ADCs, no data replication, and sparsity-aware compute. Design space exploration: The performance of NEM-C2 varies roughly l… view at source ↗
Figure 18
Figure 18. Figure 18: a) Execution time/energy requirement/energy inefficiency of designs relative to NEM-C3 for a) Reddit dataset, b) Twitter dataset. UA means unavailable mainly because PIM-GCN faces challenges in hiding additional latency for performing CAM to identify neighbors in the scheduling policy, whereas it performs better for larger datasets. This results in speedups of ∼ 76x-105x, as depicted in Fig. 17a). Similar… view at source ↗
read the original abstract

Graph neural networks (GNNs) have gained significant interest for applications such as citation network analysis and drug discovery due to their ability to apply machine learning techniques on graph-structured data. GNNs typically employ a two-stage execution pipeline consisting of combination and aggregation kernels. The combination stage performs data-intensive convolution operations with relatively regular memory access patterns, whereas the aggregation stage operates on sparse graph data with highly irregular accesses. These heterogeneous memory behaviors make conventional CPU- and GPU-based execution energy inefficient due to substantial data movement overheads. Existing accelerators attempt to mitigate these challenges using specialized architectures and processing-in-memory (PIM) techniques. However, prior approaches often suffer from scalability limitations, area overheads, restricted parallelism, and energy inefficiencies associated with analog compute and dedicated accelerator structures. This paper presents NEM-GNN, a scalable DAC/ADC-less processing-in-memory architecture for graph neural network acceleration. The proposed design introduces early compute termination mechanisms, pre-computation using reconfigurable system-on-chip components, and graph- and sparsity-aware near-memory aggregation using a compute-as-soon-as-ready (CAR) and broadcast-based execution model. Experimental results demonstrate that NEM-GNN achieves approximately 80--230x higher performance, 80--300x higher throughput, 850--1134x better energy efficiency, and 7--8x higher compute density compared to prior state-of-the-art approaches.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 1 minor

Summary. The manuscript presents NEM-GNN, a scalable DAC/ADC-less processing-in-memory architecture for graph neural network acceleration. It introduces early compute termination mechanisms, pre-computation using reconfigurable system-on-chip components, and graph- and sparsity-aware near-memory aggregation via a compute-as-soon-as-ready (CAR) and broadcast-based execution model. Experimental results are claimed to show 80--230x higher performance, 80--300x higher throughput, 850--1134x better energy efficiency, and 7--8x higher compute density versus prior state-of-the-art accelerators.

Significance. If the reported gains are shown to rest on fair, node-matched, and fully re-implemented baselines, the work would constitute a meaningful advance in digital near-memory accelerators for irregular GNN workloads by reducing data-movement costs and avoiding analog compute overheads. The emphasis on reconfigurability and sparsity awareness is a positive differentiator from prior PIM designs.

major comments (2)
  1. [Experimental Evaluation] Experimental Evaluation section: The headline performance and energy-efficiency claims (80--230x and 850--1134x) are load-bearing for the central contribution. The manuscript does not state whether all cited prior accelerators were re-implemented at the identical process node, with identical workload graphs, memory models, and clock/voltage assumptions as NEM-GNN; any mismatch would directly undermine the reported ratios.
  2. [Results] Results section, Table or Figure reporting speedups: No error bars, workload selection criteria, or baseline re-implementation details are provided, making it impossible to assess whether the 80--300x throughput and 7--8x compute-density numbers are robust or sensitive to undisclosed simulation assumptions.
minor comments (1)
  1. [Abstract] Abstract: The phrase 'approximately 80--230x' is used without reference to the specific technology node or number of workloads; adding a short parenthetical note on these parameters would improve clarity.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the constructive comments on our manuscript. We address each major point below and have revised the manuscript to improve transparency in the experimental methodology and results presentation.

read point-by-point responses

  1. Referee: [Experimental Evaluation] Experimental Evaluation section: The headline performance and energy-efficiency claims (80--230x and 850--1134x) are load-bearing for the central contribution. The manuscript does not state whether all cited prior accelerators were re-implemented at the identical process node, with identical workload graphs, memory models, and clock/voltage assumptions as NEM-GNN; any mismatch would directly undermine the reported ratios.

    Authors: We agree that explicit documentation of baseline comparison methodology is necessary to support the headline claims. The original manuscript used performance numbers as reported in the cited prior works, scaled to a common 28 nm process node via standard Dennard scaling factors from the literature, while employing the same public graph datasets (Cora, CiteSeer, PubMed, and synthetic graphs matching the sparsity distributions in the original papers). Full gate-level re-implementation of every baseline was not performed because several prior designs lack open-source RTL or detailed microarchitectural descriptions. In the revised Experimental Evaluation section we now state this methodology explicitly, list the exact scaling assumptions, and add a short discussion of the resulting limitations on the reported ratios. revision: yes

  2. Referee: [Results] Results section, Table or Figure reporting speedups: No error bars, workload selection criteria, or baseline re-implementation details are provided, making it impossible to assess whether the 80--300x throughput and 7--8x compute-density numbers are robust or sensitive to undisclosed simulation assumptions.

    Authors: We accept the referee’s observation that additional statistical and methodological detail is required. The revised Results section now includes error bars on all speedup, throughput, and energy-efficiency plots; these bars represent one standard deviation across five independent simulation runs that vary graph partitioning seeds and memory access latency within the modeled range. We have also inserted a new paragraph describing workload selection criteria (graphs chosen to span two orders of magnitude in vertex count and edge sparsity while remaining representative of real-world GNN applications) and have cross-referenced the baseline re-implementation details added to the Experimental Evaluation section. revision: yes

Circularity Check

0 steps flagged

No significant circularity: claims are experimental results from hardware design

full rationale

The paper presents NEM-GNN as a hardware architecture with specific features like early compute termination, CAR execution, and broadcast-based aggregation, then reports measured speedups and efficiency gains from simulations. No mathematical derivation chain, equations, or first-principles predictions appear in the provided abstract or description; performance numbers are framed as outcomes of the proposed design evaluated against external baselines rather than quantities defined or fitted from within the paper's own inputs. Self-citations, if present for prior PIM work, do not load-bear the central claims because the evaluation relies on re-simulation and comparison to independent prior accelerators.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 0 invented entities

Only the abstract is available, so specific free parameters, axioms, or invented entities cannot be extracted. The design implicitly relies on standard assumptions about digital circuit timing, graph sparsity distributions, and memory access irregularity as domain assumptions.

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Reference graph

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