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arxiv: 2605.30455 · v1 · pith:ZZUREG4N · submitted 2026-05-28 · quant-ph

A Denser Planar Surface Code

Guang Hao Low , William J. Huggins , Dominic W. Berry , Tanuj Khattar , Alec F. White , Nicholas C. Rubin , Ryan Babbush This is my paper

Reviewed by Pith T0 review T1 audit T2 compute T3 formal T4 kernel 2026-06-29 06:28 UTCgrok-4.3pith:ZZUREG4Nrecord.jsonopen to challenge →

classification quant-ph
keywords surface codetwist defectslattice surgeryquantum error correctionfault-tolerant quantum computationquantum chemistry simulationhexagonal latticeencoding rate
0
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The pith

A hex-grid surface code packs twist defects to reach 4.5 times the logical-qubit density of rotated surface codes under 10^{-3} circuit noise.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper introduces a planar quantum error-correcting code built on a regular hexagonal lattice by densely packing surface-code twist defects. New measurement cycles use only four layers of nearest-neighbor two-qubit gates, produce almost no hook errors that shorten distance, and admit efficient decoding. Under a uniform depolarizing noise model with 10^{-3} error rates, the resulting encoding rate is up to 4.5 times higher than that of standard rotated surface-code patches. The denser layout supports padding-free lattice surgery inside a 2d squared bounding box and yields concrete resource reductions for fault-tolerant algorithms.

Core claim

We present a quantum code implementable on a regular 2D hex grid with an estimated encoding rate up to 4.5× of that of a rotated surface code patch using circuit-level noise in a one- and two-qubit 10^{-3} error uniform depolarizing model. Our approach is based on yoking a dense packing of surface code twist defects, enabled by new stabilizer measurement cycles with an optimal four layers of nearest-neighbor two-qubit gates, almost no distance-reducing hook errors, and efficient decoding. We demonstrate a space-efficient architecture for computing on densely packed logical qubits, including new padding-free lattice surgery protocols in an optimal bounding box of 2d² data and measurement qubi

What carries the argument

Dense yoking of surface-code twist defects on a hex grid, realized through four-layer nearest-neighbor stabilizer cycles that avoid hook errors.

If this is right

  • Chemically accurate ground-state phase estimation of the 108-spin-orbital FeMoco molecule becomes feasible in under a month using 89k noisy superconducting qubits.
  • Space overhead drops by a factor of 36 and spacetime overhead by a factor of 6.6 relative to prior minimum-Toffoli estimates.
  • A Pareto frontier of space-time trade-offs exists with a minimum physical quantum volume of 1.3 mega-qubit-hours.
  • Padding-free lattice surgery fits inside a 2d² bounding box for each logical patch.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The same twist-defect packing technique may reduce overhead for non-chemistry algorithms whose bottleneck is the number of logical qubits rather than gate depth.
  • If the four-layer cycles remain efficient when the code is concatenated or used inside larger fault-tolerant protocols, the approach could compound with other overhead-reduction methods.
  • Hardware that already supports hexagonal connectivity may see an immediate density gain without requiring new fabrication steps.

Load-bearing premise

The new four-layer stabilizer cycles can be executed on hardware without introducing error rates or correlations beyond those captured by the uniform 10^{-3} depolarizing model.

What would settle it

A circuit-level simulation or device experiment that measures the logical error rate per cycle for the new code and finds it no better than the rate achieved by a rotated surface-code patch of equal distance at the same physical error rate.

Figures

Figures reproduced from arXiv: 2605.30455 by Alec F. White, Dominic W. Berry, Guang Hao Low, Nicholas C. Rubin, Ryan Babbush, Tanuj Khattar, William J. Huggins.

Figure 1
Figure 1. Figure 1: FIG. 1. Pareto frontier of physical resources for chemically-accurate ground state phase estimation of ‘utility-scale’ benchmark [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: FIG. 2. Summary of our key contributions. Section [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: FIG. 3. (Left) Rotated surface code patch with weight-4 Pauli- [PITH_FULL_IMAGE:figures/full_fig_p005_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: FIG. 4. The [PITH_FULL_IMAGE:figures/full_fig_p006_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: FIG. 5. Surface code patch encoding one logical qubit using [PITH_FULL_IMAGE:figures/full_fig_p007_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: FIG. 6. (Left) Memory benchmark of alternating gate sequence Fig. [PITH_FULL_IMAGE:figures/full_fig_p009_6.png] view at source ↗
Figure 7
Figure 7. Figure 7: FIG. 7. (Left) The [PITH_FULL_IMAGE:figures/full_fig_p010_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: FIG. 8. (Top) Lattice surgery merge operation. Step [PITH_FULL_IMAGE:figures/full_fig_p011_8.png] view at source ↗
Figure 9
Figure 9. Figure 9: FIG. 9. The logical error rate per round per patch of H-bridge lattice surgery between distance [PITH_FULL_IMAGE:figures/full_fig_p012_9.png] view at source ↗
Figure 10
Figure 10. Figure 10: FIG. 10. (Left) Rectangular surface code patch with two weight-5 twist defects featuring a Pauli- [PITH_FULL_IMAGE:figures/full_fig_p013_10.png] view at source ↗
Figure 11
Figure 11. Figure 11: FIG. 11. We present various dense packings of twist defects that enable up to a 4 [PITH_FULL_IMAGE:figures/full_fig_p014_11.png] view at source ↗
Figure 12
Figure 12. Figure 12: FIG. 12 [PITH_FULL_IMAGE:figures/full_fig_p016_12.png] view at source ↗
Figure 13
Figure 13. Figure 13: FIG. 13. (Left) The dimensions of the three-qubit patch. [PITH_FULL_IMAGE:figures/full_fig_p017_13.png] view at source ↗
Figure 14
Figure 14. Figure 14: FIG. 14. Defect diagrams for (top) a standard patch rotation like in prior art, (middle) a spatial Hadamard, and (bottom) an [PITH_FULL_IMAGE:figures/full_fig_p018_14.png] view at source ↗
Figure 15
Figure 15. Figure 15: FIG. 15. (Top) All distance [PITH_FULL_IMAGE:figures/full_fig_p018_15.png] view at source ↗
Figure 16
Figure 16. Figure 16: FIG. 16. (Top) [PITH_FULL_IMAGE:figures/full_fig_p019_16.png] view at source ↗
Figure 17
Figure 17. Figure 17: FIG. 17. Non-exhaustive sequence of high-level operations for loading and unloading of 1-qubit patches into a (top) 2-qubit [PITH_FULL_IMAGE:figures/full_fig_p020_17.png] view at source ↗
Figure 18
Figure 18. Figure 18: FIG. 18. Lattice surgery operations that measure the logical [PITH_FULL_IMAGE:figures/full_fig_p021_18.png] view at source ↗
Figure 19
Figure 19. Figure 19: FIG. 19. Sequence of operations, with some drawn from Figs. [PITH_FULL_IMAGE:figures/full_fig_p022_19.png] view at source ↗
Figure 20
Figure 20. Figure 20: FIG. 20. (Left) We group dense twist storage logical qubits into columns with an even number of qubits (gray boxes) and [PITH_FULL_IMAGE:figures/full_fig_p023_20.png] view at source ↗
Figure 21
Figure 21. Figure 21: FIG. 21. Assuming that no distance 2 [PITH_FULL_IMAGE:figures/full_fig_p024_21.png] view at source ↗
Figure 22
Figure 22. Figure 22: FIG. 22. (Top) Logical error rate of 1D yoked twist dense memory assuming an ideal outer decoder. By correlating information [PITH_FULL_IMAGE:figures/full_fig_p024_22.png] view at source ↗
Figure 23
Figure 23. Figure 23: FIG. 23. We organize lattice surgery of an algorithm into specialized regions: compute, cold storage, and hot storage, drawn [PITH_FULL_IMAGE:figures/full_fig_p025_23.png] view at source ↗
Figure 24
Figure 24. Figure 24: FIG. 24. Hot storage syndrome extraction optimized for medium latency. In the first 6 [PITH_FULL_IMAGE:figures/full_fig_p028_24.png] view at source ↗
Figure 25
Figure 25. Figure 25: FIG. 25. Density of logical qubit hot storage based on the layouts in Fig. [PITH_FULL_IMAGE:figures/full_fig_p029_25.png] view at source ↗
Figure 26
Figure 26. Figure 26: FIG. 26. Probability of failure for each logical operator in a qubit hotel, where [PITH_FULL_IMAGE:figures/full_fig_p030_26.png] view at source ↗
Figure 27
Figure 27. Figure 27: FIG. 27. Example layouts drawn to scale with [PITH_FULL_IMAGE:figures/full_fig_p031_27.png] view at source ↗
Figure 28
Figure 28. Figure 28: FIG. 28. Map between quantum circuit, [PITH_FULL_IMAGE:figures/full_fig_p034_28.png] view at source ↗
Figure 29
Figure 29. Figure 29: FIG. 29. Pipe diagram showing how lookup table output bits are written to hot storage. The example shown is 6 columns of [PITH_FULL_IMAGE:figures/full_fig_p036_29.png] view at source ↗
Figure 30
Figure 30. Figure 30: FIG. 30. Reproduced verbatim from Figure. 10 of [ [PITH_FULL_IMAGE:figures/full_fig_p037_30.png] view at source ↗
Figure 31
Figure 31. Figure 31: FIG. 31. Implementation of the [PITH_FULL_IMAGE:figures/full_fig_p041_31.png] view at source ↗
Figure 32
Figure 32. Figure 32: FIG. 32. Implementation of the [PITH_FULL_IMAGE:figures/full_fig_p041_32.png] view at source ↗
Figure 33
Figure 33. Figure 33: FIG. 33. Implementation of the controlled Hadamard gate using Clifford gates, along with one [PITH_FULL_IMAGE:figures/full_fig_p041_33.png] view at source ↗
Figure 34
Figure 34. Figure 34: FIG. 34. Implementation of the controlled phase gate using Clifford gates, along with two [PITH_FULL_IMAGE:figures/full_fig_p042_34.png] view at source ↗
Figure 35
Figure 35. Figure 35: FIG. 35. A lattice surgery pipe diagram that shows the Clifford component of our optimized catalyzed CCZ to 2T circuit. The [PITH_FULL_IMAGE:figures/full_fig_p042_35.png] view at source ↗
Figure 36
Figure 36. Figure 36: FIG. 36. A plot showing the error achievable as a function of the number of T gates for diagonal rotation synthesis. We [PITH_FULL_IMAGE:figures/full_fig_p043_36.png] view at source ↗
Figure 37
Figure 37. Figure 37: FIG. 37. A circuit diagram for the fallback protocol, reproduced from [ [PITH_FULL_IMAGE:figures/full_fig_p044_37.png] view at source ↗
Figure 38
Figure 38. Figure 38: FIG. 38. A plot showing the error achievable as a function of the number of T gates for fallback rotation synthesis. This plot [PITH_FULL_IMAGE:figures/full_fig_p045_38.png] view at source ↗
Figure 39
Figure 39. Figure 39: FIG. 39. Implementation of a Givens rotation using a controlled [PITH_FULL_IMAGE:figures/full_fig_p045_39.png] view at source ↗
Figure 40
Figure 40. Figure 40: FIG. 40. Implementation of a controlled [PITH_FULL_IMAGE:figures/full_fig_p046_40.png] view at source ↗
Figure 41
Figure 41. Figure 41: FIG. 41. Implementation of the [PITH_FULL_IMAGE:figures/full_fig_p046_41.png] view at source ↗
Figure 42
Figure 42. Figure 42: FIG. 42. Diagrams of the logical circuits for the three main components we use to compile the controlled adder. [PITH_FULL_IMAGE:figures/full_fig_p047_42.png] view at source ↗
Figure 43
Figure 43. Figure 43: FIG. 43. Our controlled adder is implemented by combining the AND, MAJ, and UMA components in a 5 [PITH_FULL_IMAGE:figures/full_fig_p048_43.png] view at source ↗
Figure 44
Figure 44. Figure 44: FIG. 44. Our best physical-qubit-runtime tradeoff in Fig. [PITH_FULL_IMAGE:figures/full_fig_p051_44.png] view at source ↗
Figure 45
Figure 45. Figure 45: FIG. 45. Quantum circuit for block-encoding the DFTHC square-root Hamiltonian after all logical qubit count optimizations. [PITH_FULL_IMAGE:figures/full_fig_p052_45.png] view at source ↗
Figure 46
Figure 46. Figure 46: FIG. 46. (Left) We block-encode the DFTHC Hamiltonian Section [PITH_FULL_IMAGE:figures/full_fig_p052_46.png] view at source ↗
Figure 47
Figure 47. Figure 47: FIG. 47. After implementing the quantum lookup table, rows of output bits are packed towards the top in order to instantiate [PITH_FULL_IMAGE:figures/full_fig_p055_47.png] view at source ↗
Figure 48
Figure 48. Figure 48: FIG. 48. Gate sequences implementing walking of a surface code patch for the cases of (top) an [PITH_FULL_IMAGE:figures/full_fig_p062_48.png] view at source ↗
Figure 49
Figure 49. Figure 49: FIG. 49. The logical error rate per round per patch of H-bridge lattice surgery between distance [PITH_FULL_IMAGE:figures/full_fig_p063_49.png] view at source ↗
Figure 50
Figure 50. Figure 50: FIG. 50. Lattice surgery merge operation for all possible patch orientations. [PITH_FULL_IMAGE:figures/full_fig_p064_50.png] view at source ↗
Figure 50
Figure 50. Figure 50: FIG. 50. (Continued) Lattice surgery merge operation for all possible patch orientations. [PITH_FULL_IMAGE:figures/full_fig_p065_50.png] view at source ↗
Figure 51
Figure 51. Figure 51: FIG. 51. Lattice surgery split operation for all possible patch orientations. [PITH_FULL_IMAGE:figures/full_fig_p066_51.png] view at source ↗
Figure 51
Figure 51. Figure 51: FIG. 51. (Continued) Lattice surgery split operation for all possible patch orientations. [PITH_FULL_IMAGE:figures/full_fig_p067_51.png] view at source ↗
Figure 52
Figure 52. Figure 52: FIG. 52. (Top) Gate sequence implementing a rectangular patch encoding two logical qubits. Note the point [PITH_FULL_IMAGE:figures/full_fig_p068_52.png] view at source ↗
Figure 53
Figure 53. Figure 53: FIG. 53. Lattice surgery implementing a logical [PITH_FULL_IMAGE:figures/full_fig_p069_53.png] view at source ↗
Figure 54
Figure 54. Figure 54: FIG. 54. Benchmark of alternating gate sequence using one additional column and row [ [PITH_FULL_IMAGE:figures/full_fig_p070_54.png] view at source ↗
Figure 55
Figure 55. Figure 55: FIG. 55. An 8-cycle implementation of a twist defect with no hook errors. Note that all resets may be moved to execute in the [PITH_FULL_IMAGE:figures/full_fig_p070_55.png] view at source ↗
Figure 56
Figure 56. Figure 56: FIG. 56. Example of elementary steps that realize some of the high-level operations in Fig. [PITH_FULL_IMAGE:figures/full_fig_p070_56.png] view at source ↗
Figure 57
Figure 57. Figure 57: FIG. 57. (Top left) Example minimum-spacetime layout of skew-tree lookup with clean ancilla Fig. [PITH_FULL_IMAGE:figures/full_fig_p073_57.png] view at source ↗
Figure 58
Figure 58. Figure 58: FIG. 58. Skew Tree QROM circuit (a) without errors and (b) with classical absorption of CCZ injection errors at node 12. [PITH_FULL_IMAGE:figures/full_fig_p077_58.png] view at source ↗
Figure 59
Figure 59. Figure 59: FIG. 59. The core 3 [PITH_FULL_IMAGE:figures/full_fig_p079_59.png] view at source ↗
Figure 60
Figure 60. Figure 60: FIG. 60 [PITH_FULL_IMAGE:figures/full_fig_p080_60.png] view at source ↗
Figure 61
Figure 61. Figure 61: FIG. 61 [PITH_FULL_IMAGE:figures/full_fig_p081_61.png] view at source ↗
Figure 62
Figure 62. Figure 62: FIG. 62 [PITH_FULL_IMAGE:figures/full_fig_p081_62.png] view at source ↗
Figure 63
Figure 63. Figure 63: FIG. 63 [PITH_FULL_IMAGE:figures/full_fig_p082_63.png] view at source ↗
Figure 64
Figure 64. Figure 64: FIG. 64 [PITH_FULL_IMAGE:figures/full_fig_p083_64.png] view at source ↗
Figure 65
Figure 65. Figure 65: FIG. 65 [PITH_FULL_IMAGE:figures/full_fig_p084_65.png] view at source ↗
Figure 66
Figure 66. Figure 66: FIG. 66. Alternative bottom-view camera angle of the compiled spacetime geometries in Figure [PITH_FULL_IMAGE:figures/full_fig_p084_66.png] view at source ↗
Figure 67
Figure 67. Figure 67: FIG. 67. Alternative back-view camera angle of the compiled spacetime geometries in Figure [PITH_FULL_IMAGE:figures/full_fig_p085_67.png] view at source ↗
Figure 68
Figure 68. Figure 68: FIG. 68. Sequence of moves showing how columns of single-access hallways may be moved to open up new space for another [PITH_FULL_IMAGE:figures/full_fig_p085_68.png] view at source ↗
Figure 69
Figure 69. Figure 69: FIG. 69. (Left) The circuit for the sum of squares from Ref. [ [PITH_FULL_IMAGE:figures/full_fig_p086_69.png] view at source ↗
Figure 70
Figure 70. Figure 70: FIG. 70. The circuit diagram for the procedure shown in step 2 of Table [PITH_FULL_IMAGE:figures/full_fig_p091_70.png] view at source ↗
read the original abstract

We present a quantum code implementable on a regular $2$D hex grid with an estimated encoding rate up to $4.5\times$ of that of a rotated surface code patch using circuit-level noise in a one- and two-qubit $10^{-3}$ error uniform depolarizing model. Our approach is based on yoking a dense packing of surface code twist defects, enabled by new stabilizer measurement cycles with an optimal four layers of nearest-neighbor two-qubit gates, almost no distance-reducing hook errors, and efficient decoding. We demonstrate a space-efficient architecture for computing on densely packed logical qubits, including new padding-free lattice surgery protocols in an optimal bounding box of $2d^2$ data and measurement qubits per patch. Assuming a $1\mu$s surface code cycle time and a $10\mu$s reaction time, these developments enable chemically accurate ground state phase estimation of a broad class of `utility-scale' electronic structure simulation problems such as the $108$ spin-orbital FeMoco-based nitrogen fixation catalyst in under a month with $89$k noisy superconducting qubits. We elucidate a Pareto frontier of space-time trade-offs and find a minimum physical quantum volume of $1.3$ mega-qubit-hours. These correspond to a $36\times$ space and $6.6\times$ spacetime improvement, respectively, over our previous state-of-the-art minimum-Toffoli resource estimates (Phys. Rev. X 15, 041016).

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

1 major / 1 minor

Summary. The manuscript proposes a denser planar surface code on a regular 2D hexagonal grid achieved via dense packing of surface-code twist defects. It introduces new stabilizer measurement cycles using an optimal four layers of nearest-neighbor two-qubit gates that are asserted to incur almost no distance-reducing hook errors while supporting efficient decoding. Under a circuit-level uniform depolarizing noise model with 10^{-3} one- and two-qubit error rates, the construction is claimed to deliver up to 4.5× higher encoding rate than rotated surface-code patches, together with padding-free lattice surgery in a 2d² bounding box. These improvements are used to derive resource estimates for chemically accurate ground-state phase estimation of the 108-orbital FeMoco system (89k physical qubits, under one month) and a minimum physical quantum volume of 1.3 mega-qubit-hours, corresponding to 36× space and 6.6× spacetime gains over prior estimates.

Significance. If the hook-error suppression and distance preservation claims are substantiated, the work would provide a concrete reduction in physical-qubit overhead for planar surface-code architectures, directly impacting the feasibility of utility-scale quantum simulations on near-term superconducting hardware. The explicit Pareto frontier of space-time trade-offs and the end-to-end FeMoco resource calculation supply falsifiable benchmarks that strengthen the paper’s utility for the broader quantum resource estimation literature.

major comments (1)
  1. [Abstract] Abstract: the central claim that the four-layer stabilizer cycles incur 'almost no distance-reducing hook errors' and support 'efficient decoding' for the dense twist-defect packing is load-bearing for the reported 4.5× encoding rate, 36× space improvement, and 89k-qubit FeMoco estimate, yet the abstract supplies no explicit distance calculations, per-configuration hook-error analysis, or threshold simulations under the stated 10^{-3} depolarizing model to confirm that effective distance is preserved across all relevant defect arrangements.
minor comments (1)
  1. [Abstract] Abstract: the precise definition of the 'one- and two-qubit 10^{-3} error uniform depolarizing model' (including whether measurement errors are included and how the circuit-level noise is applied to the four-layer schedule) should be stated explicitly or referenced to a methods section for reproducibility.

Simulated Author's Rebuttal

1 responses · 0 unresolved

We thank the referee for their thoughtful review and positive assessment of the work's significance. We address the single major comment below, providing clarification on where the supporting analyses appear in the manuscript while agreeing that the abstract itself is concise by design.

read point-by-point responses

  1. Referee: [Abstract] Abstract: the central claim that the four-layer stabilizer cycles incur 'almost no distance-reducing hook errors' and support 'efficient decoding' for the dense twist-defect packing is load-bearing for the reported 4.5× encoding rate, 36× space improvement, and 89k-qubit FeMoco estimate, yet the abstract supplies no explicit distance calculations, per-configuration hook-error analysis, or threshold simulations under the stated 10^{-3} depolarizing model to confirm that effective distance is preserved across all relevant defect arrangements.

    Authors: The abstract is a high-level summary and does not include detailed calculations, which is standard. The explicit distance calculations, per-configuration hook-error analysis demonstrating preservation of distance for all relevant twist-defect arrangements, and threshold simulations under the uniform depolarizing circuit-level noise model at 10^{-3} are provided in the main text (Sections III–V). These confirm that the four-layer cycles incur almost no distance-reducing hook errors and support efficient decoding. We will revise the abstract to add a short clause referencing these results for improved clarity. revision: partial

Circularity Check

1 steps flagged

Minor self-citation for baseline comparison; central code construction and rate estimates remain independent.

specific steps
  1. self citation load bearing [Abstract (final sentence)]
    "These correspond to a 36× space and 6.6× spacetime improvement, respectively, over our previous state-of-the-art minimum-Toffoli resource estimates (Phys. Rev. X 15, 041016)."

    The quoted improvement factors are computed relative to the authors' own earlier resource estimates. While this is only a comparative baseline and does not define or justify the new stabilizer cycles or encoding rate, it constitutes the single minor self-citation present.

full rationale

The paper introduces new stabilizer measurement cycles (four nearest-neighbor layers) and padding-free lattice surgery on a hex grid, then estimates encoding rate (4.5×) and resource counts under an explicit circuit-level depolarizing noise model. These constructions are presented directly rather than defined in terms of the output metrics. The 36×/6.6× improvements and FeMoco numbers are comparisons to a prior self-cited work (Phys. Rev. X 15, 041016); this citation supplies only the baseline and is not invoked to justify uniqueness or forbid alternatives for the new code. No fitted parameters are renamed as predictions, no self-definitional loops appear in the abstract or cited claims, and the derivation does not reduce to its inputs by construction. This is the normal minor self-citation case (score 2).

Axiom & Free-Parameter Ledger

3 free parameters · 2 axioms · 0 invented entities

Performance estimates rest on an assumed uniform depolarizing noise model, fixed cycle and reaction times, and the unverified feasibility of the new measurement cycles and decoding.

free parameters (3)
  • depolarizing error probability = 10^{-3}
    Uniform one- and two-qubit 10^{-3} error rate used for all circuit-level simulations and resource estimates.
  • surface-code cycle time = 1 μs
    1 μs assumed to convert gate counts into wall-clock time for the FeMoco estimate.
  • reaction time = 10 μs
    10 μs assumed for classical feedback latency in spacetime volume calculations.
axioms (2)
  • domain assumption New stabilizer measurement cycles on the hex grid incur almost no distance-reducing hook errors and admit efficient decoding.
    This premise is required for the 4.5× encoding-rate claim but receives no derivation in the abstract.
  • domain assumption The 1 μs cycle time and 10 μs reaction time are representative of future hardware.
    These timing assumptions convert abstract gate counts into the reported month-scale runtime.

pith-pipeline@v0.9.1-grok · 5811 in / 1746 out tokens · 33446 ms · 2026-06-29T06:28:43.936569+00:00 · methodology

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Forward citations

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Reference graph

Works this paper leans on

15 extracted references · cited by 5 Pith papers

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    From|x o⟩, compute in a single ancillary qubit the comparison|x o <2 nR C⟩

  2. [2]

    These correspond to theG SF components

    Controlled on|x o <2 nR C⟩=|1⟩, perform unary iteration over the firstRaddresses of then R qubits. These correspond to theG SF components

  3. [3]

    The high bit can be used as a control to perform unary iteration over the firstNaddresses of then R +n C qubits

    Subtract 2 nR Cfrom|x o⟩to obtain|x o −2 nR C⟩. The high bit can be used as a control to perform unary iteration over the firstNaddresses of then R +n C qubits. These correspond to theG D1 andG Q1 compo- nents. •Removing the single-qubit|b=B⟩registerQROAM inRPrepoutputs a single qubit state flagging the condition|b=B⟩. This is then used to controlMaj: If|...

  4. [4]

    This large overhead was chosen to minimize the Toffoli cost ofRPrep

    Reducing RPrep bits and using dirty qubits The qubit overhead is dominated by the (N−1)b rot qubits output by theQROMinRPrep. This large overhead was chosen to minimize the Toffoli cost ofRPrep. In this section, we show that for any integerλ∈[1,(N−1)], we can reduce this qubit overhead to justλb rot. We also use QROAM with either clean or dirty qubits for...

  5. [5]

    In contrast, alias sampling of the same state tob coeff bits of precision uses a large number of 2(n X +b coeff) persistent bits

    Pure state preparation instead of alias sampling Storing a pure state PX−1 j=0 cj |j⟩requires onlyn X qubits. In contrast, alias sampling of the same state tob coeff bits of precision uses a large number of 2(n X +b coeff) persistent bits. In the limit of very few ancillae, it is beneficial to replace alias sampling in both Inner and OuterPrepwith alterna...

  6. [6]

    However, there exist alternate implementations that cost a constant factor more in Toffoli gates but only use dirty qubits

    Clean-ancilla-free arithmetic The arithmetic operations (multiple-controlledX, quantum-classical comparators, adders, unary iteration) used in our block-encoding previously required temporary clean ancilla qubits. However, there exist alternate implementations that cost a constant factor more in Toffoli gates but only use dirty qubits. By using only dirty...

  7. [7]

    This method always uses at least 2b rot qubits: Half for storing ab rot-qubit Fourier resource state, and half for theb rot-qubit bit-string specifying the rotation angle

    Rotation synthesis with fewer qubits Up to this point, we have been synthesizingb-bitZrotations using the phase gradient technique. This method always uses at least 2b rot qubits: Half for storing ab rot-qubit Fourier resource state, and half for theb rot-qubit bit-string specifying the rotation angle. However, there are other methods of rotation synthesi...

  8. [8]

    Qubits after

    Uncompute QROAM. For any integerγ∈[1, b rot], one may instead define a loop overl= 0,1, l max −1, wherel max =⌈b rot/γ⌉. Then at iterationl: 1) Perform QROAM on some number ofdaddresses to outputγ rotation bits| ⃗θl⟩where ⃗θl .= (θ0+lγ, θ1+lγ,· · ·, θ γ−1+lγ ). Similar to the programmable gate array, the (l+ 1) th iteration can XOR in ⃗θl ⊕ ⃗θl+1 to reali...

  9. [9]

    This uses as most one dirty ancilla for the comparison by Lemma 9, which also dominates the Toffoli count

    Compute the flags|f SF⟩=|x o < RC⟩and|f B′⟩=|b ′ =B⟩. This uses as most one dirty ancilla for the comparison by Lemma 9, which also dominates the Toffoli count

  10. [10]

    This guarantees that|b⟩stores an integer< B

    Controlled by|f B′⟩=|1⟩, perform a quantum-classical subtraction|b⟩ → |b−B⟩using one dirty ancilla. This guarantees that|b⟩stores an integer< B

  11. [11]

    The multiply-add uses one clean qubit and one dirty qubit

    Controlled by|f SF⟩, apply a multiply-add to compute|x o⟩ |b⟩ → |x oB+b⟩, wherex oB+b=cRB+rB+b. The multiply-add uses one clean qubit and one dirty qubit

  12. [12]

    Controlled by|f SF⟩, apply a multiply-add in reverse to compute|x oB+b⟩ → |rB+b⟩ |c⟩

  13. [13]

    Controlled by|f SF⟩=|1⟩, add the constantNwith a quantum-classical adder to obtain|rB+b⟩ → |rB+b+N⟩, and controlled by|f SF⟩=|0⟩, subtract the constantRCfrom|x o⟩to index theG D1 , GQ1 terms

  14. [14]

    Uncompute the flag|f SF⟩using a comparison

  15. [15]

    At this point, the lowestn N+RB qubits hold the contiguous address, and the remaining addresses may be used as dirty qubits for QROAM. One may also flatten theRBCaddresses forInner, but this does not appear worth doing as it only frees one or two qubits sinceRBC≫N+RB, andInneris a much smaller lookup thanRPrepanyway. Address flattening also changes some o...

    2002