Typed states for the displayed outbound observations.
Source: paper_references, paper_reference_links, observed 2026-06-28T12:08:37.102375Z
Paper Citation Record · LEDGER
As of 15 August 2026, this Paper Citation Record lists 14 of 14 outbound references and 0 inbound Pith citation observations for arXiv:2606.02358.
A citation records a reference. It does not transfer a finding from one paper to another.
Typed states for the displayed outbound observations.
Source: paper_references, paper_reference_links, observed 2026-06-28T12:08:37.102375Z
One-hop event checks from named stored sources.
Source: scholarly_work_events, retraction_status_cache, observed 2026-08-15T06:32:42.880941+00:00
Pith citing papers itemized under the disclosed page cap.
Source: paper_references, paper_reference_links
A source-named dated measurement, never combined with another source.
Source: cited_works
14 of 14 outbound references displayed
External citation measurements
No source-named external measurement is stored.
Observation dc036e41-02cc-453e-a359-48d04be1c8e6 · outbound
CHIMERA: A Flexible and Scalable 3.1 TOPS/W AI-MCU with Transformer Accelerator and 563 Gb/s Shared-L2 Memory Subsystem with QoS Guarantees A Survey on Deep Learning Hardware Accelerators for Heterogeneous HPC Platforms,
Reference 1
Source-reported events for the cited work
Unavailable: canonical work link unavailable.
Observation 1dfcbbb8-c3e4-4b86-96ee-4b0a8a4e77cd · outbound
CHIMERA: A Flexible and Scalable 3.1 TOPS/W AI-MCU with Transformer Accelerator and 563 Gb/s Shared-L2 Memory Subsystem with QoS Guarantees How to Keep Pushing ML Accelerator Performance? Know Your Rooflines!
Reference 2
Source-reported events for the cited work
Unavailable: canonical work link unavailable.
Observation d2ad0e9b-5baa-4575-bda6-964eb515f8eb · outbound
CHIMERA: A Flexible and Scalable 3.1 TOPS/W AI-MCU with Transformer Accelerator and 563 Gb/s Shared-L2 Memory Subsystem with QoS Guarantees DeepSpeed- Inference: Enabling Efficient In- ference of Transformer Models at Unprecedented Scale,
Reference 3
Source-reported events for the cited work
Unavailable: canonical work link unavailable.
Observation a6e7b030-cc29-4f1c-b61d-06b1ec69f51f · outbound
CHIMERA: A Flexible and Scalable 3.1 TOPS/W AI-MCU with Transformer Accelerator and 563 Gb/s Shared-L2 Memory Subsystem with QoS Guarantees AI and Memory Wall,
Reference 4
Source-reported events for the cited work
Unavailable: canonical work link unavailable.
Observation d75f9539-9321-49d6-86f0-01938d564ffb · outbound
CHIMERA: A Flexible and Scalable 3.1 TOPS/W AI-MCU with Transformer Accelerator and 563 Gb/s Shared-L2 Memory Subsystem with QoS Guarantees Shared Memory-contention-aware Con- current DNN Execution for Diversely Heterogeneous System-on-Chips,
Reference 5
Source-reported events for the cited work
Unavailable: canonical work link unavailable.
Observation 0a9384fe-d136-4731-9c4b-3de38a4a4d55 · outbound
CHIMERA: A Flexible and Scalable 3.1 TOPS/W AI-MCU with Transformer Accelerator and 563 Gb/s Shared-L2 Memory Subsystem with QoS Guarantees Analysis and Mitigation of Shared Resource Contention on Heterogeneous Multicore: An Industrial Case Study,
Reference 6
Source-reported events for the cited work
Unavailable: canonical work link unavailable.
Observation 2a178887-d583-4fed-8cb3-650bca89d905 · outbound
CHIMERA: A Flexible and Scalable 3.1 TOPS/W AI-MCU with Transformer Accelerator and 563 Gb/s Shared-L2 Memory Subsystem with QoS Guarantees Artificial intelligence index report 2025,
Reference 7
Source-reported events for the cited work
Unavailable: canonical work link unavailable.
Observation 2631e486-14ee-4dae-a3c6-5a0f3ee19821 · outbound
CHIMERA: A Flexible and Scalable 3.1 TOPS/W AI-MCU with Transformer Accelerator and 563 Gb/s Shared-L2 Memory Subsystem with QoS Guarantees Flex-SFU: Activation Function Acceleration With Nonuniform Piecewise Approximation,
Reference 8
Source-reported events for the cited work
Unavailable: canonical work link unavailable.
Observation e54a4271-0e0a-4da4-b29c-22c4dda42958 · outbound
CHIMERA: A Flexible and Scalable 3.1 TOPS/W AI-MCU with Transformer Accelerator and 563 Gb/s Shared-L2 Memory Subsystem with QoS Guarantees ITA: An Energy-Efficient Attention and Softmax Accelerator for Quantized Transformers,
Reference 9
Source-reported events for the cited work
Unavailable: canonical work link unavailable.
Observation 517aee99-fa0e-44e3-93a6-fa694aad4d1a · outbound
CHIMERA: A Flexible and Scalable 3.1 TOPS/W AI-MCU with Transformer Accelerator and 563 Gb/s Shared-L2 Memory Subsystem with QoS Guarantees Ayaka: A Versatile Transformer Accelerator With Low- Rank Estimation and Heterogeneous Dataflow,
Reference 10
Source-reported events for the cited work
Unavailable: canonical work link unavailable.
Observation a816eae9-e254-4217-a0ca-2b6593d49f02 · outbound
CHIMERA: A Flexible and Scalable 3.1 TOPS/W AI-MCU with Transformer Accelerator and 563 Gb/s Shared-L2 Memory Subsystem with QoS Guarantees EV A: A 16mm2 1.54TFLOPS Tiled-Based Accelerator for Evolvable Edge Computing,
Reference 11
Source-reported events for the cited work
Unavailable: canonical work link unavailable.
Observation 3864d56f-22a3-44a7-af6e-caf52b65bb19 · outbound
CHIMERA: A Flexible and Scalable 3.1 TOPS/W AI-MCU with Transformer Accelerator and 563 Gb/s Shared-L2 Memory Subsystem with QoS Guarantees A 22nm 25.08TOPS/W Multi-Task Transformer Accel- erator with Mixed Precision Structured Sparsity and Two-Stage Task- Adaptive Power Management,
Reference 12
Source-reported events for the cited work
Unavailable: canonical work link unavailable.
Observation 6695648b-e62a-4a5b-b37e-b61ea90a8e7e · outbound
CHIMERA: A Flexible and Scalable 3.1 TOPS/W AI-MCU with Transformer Accelerator and 563 Gb/s Shared-L2 Memory Subsystem with QoS Guarantees TinyVers: A 0.8-17 TOPS/W, 1.7 µW-20 mW, Tiny Versatile System-on-chip with State-Retentive eMRAM for Machine Learning Inference at the Extreme Edge,
Reference 13
Source-reported events for the cited work
Unavailable: canonical work link unavailable.
Observation 64c00b3f-2e27-4d1b-bd03-083cd1bfdc3c · outbound
CHIMERA: A Flexible and Scalable 3.1 TOPS/W AI-MCU with Transformer Accelerator and 563 Gb/s Shared-L2 Memory Subsystem with QoS Guarantees A 18 nm FD-SOI CMOS 6.38 mW 15 fps 8 -bit features 14.8 µJ/inference QVGA road-traffic monitoring Edge AI SoC demonstrator,
Reference 14
Source-reported events for the cited work
Unavailable: canonical work link unavailable.
No inbound Pith citation observations are available.