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arxiv: 2606.08378 · v1 · pith:63VT24GPnew · submitted 2026-06-07 · ❄️ cond-mat.mtrl-sci

Thermal Processing Limits in Oxide-Channel Ferroelectric Field Effect Transistors

Lance Fernandes , Yu-Hsin Kuo , Chengyang Zhang , Priyankka Ravikumar , Ranie Jeyakumar , Dyutimoy Chakraborty , Jiayi Chen , Taeyoung Song
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Kai Ni Woohyun Hwang Kwangyou Seo Suhwan Lim Wanki Kim Daewon Ha Julia Medvedeva Suman Datta Shimeng Yu Asif Khan
This is my paper

Pith reviewed 2026-06-27 18:32 UTC · model grok-4.3

classification ❄️ cond-mat.mtrl-sci
keywords ferroelectric field-effect transistorsoxide semiconductor channelsthermal annealingindium oxidememory windowstructural evolutionGa dopingW doping
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The pith

10 percent Ga-doped and 4 percent W-doped InO channels in FeFETs function after 650 C annealing for limited times.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper investigates the thermal stability of oxide-semiconductor channel ferroelectric field-effect transistors under high-temperature post-capping annealing. It demonstrates that 10% Ga-doped InO and 4% W-doped InO channels maintain functionality up to 650°C for 30 and 10 minutes respectively when paired with a specific hybrid capping layer and ferroelectric stack. Beyond these limits, devices experience irreversible loss of conduction. Electrical analysis links memory window changes to threshold voltage shifts, and X-ray diffraction confirms structural evolution in the channels as the cause of failure.

Core claim

Using an identical ferroelectric gate stack of 8nm HZO / 3nm Al2O3 / 8nm HZO and a hybrid capping layer, the 10 percent Ga doped InO channel and 4 percent W doped InO channel FeFETs remain functional after annealing at temperatures up to 650 C for durations of up to 30 min and 10 min, respectively; further annealing results in irreversible loss of conduction and device failure. The MW enhancement originates from a preferential positive shift in the erased-state threshold voltage, while the programmed-state threshold voltage remains comparatively stable, with grazing-incidence X-ray diffraction measurements indicating structural evolution in the oxide channels.

What carries the argument

The doped indium oxide channels (10% Ga-doped InO and 4% W-doped InO) whose structural evolution under annealing sets the thermal processing limits, isolated by the hybrid capping layer and ferroelectric gate stack.

If this is right

  • Memory window enhancement via erased-state threshold voltage shift remains achievable within the stated annealing budgets.
  • The channels support post-capping thermal steps up to 650 C without immediate loss of conduction.
  • Further temperature or time increases trigger irreversible channel degradation visible in both electrical and diffraction data.
  • Structural changes in the oxide channels are the dominant factor setting the upper thermal bound for these FeFETs.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • Different doping percentages in similar indium oxide channels could shift the observed temperature and time limits under the same stack conditions.
  • The results point toward channel composition as a lever for matching FeFETs to fabrication flows with higher thermal budgets.
  • Comparable capping strategies applied to other oxide channels would likely reveal material-specific thermal ceilings.

Load-bearing premise

The hybrid capping layer and identical ferroelectric gate stack isolate thermal effects to the oxide channels, such that observed threshold voltage shifts and device failure are attributable to channel structural evolution rather than capping or stack degradation.

What would settle it

Annealing devices that lack the hybrid capping layer or use a different gate stack and checking whether failure occurs at the same temperatures and times would test whether the channel alone drives the limits.

Figures

Figures reproduced from arXiv: 2606.08378 by Asif Khan, Chengyang Zhang, Daewon Ha, Dyutimoy Chakraborty, Jiayi Chen, Julia Medvedeva, Kai Ni, Kwangyou Seo, Lance Fernandes, Priyankka Ravikumar, Ranie Jeyakumar, Shimeng Yu, Suhwan Lim, Suman Datta, Taeyoung Song, Wanki Kim, Woohyun Hwang, Yu-Hsin Kuo.

Figure 1
Figure 1. Figure 1: (a) Fabrication process flow for back-gated OS-FeFET with laminated stack and [PITH_FULL_IMAGE:figures/full_fig_p003_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: (a) DC Id-Vg and Ig-Vg characteristics of the device without PCA. (b-c) DC Id￾Vg and Ig-Vg characteristics following moderate-temperature annealing (400–550 ◦C) (d-f) DC Id-Vg and Ig-Vg characteristics after high-temperature annealing (650 ◦C). Blue arrows indicate the direction of I-V sweep. 4 [PITH_FULL_IMAGE:figures/full_fig_p004_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: (a) Pulsed I-V measurement scheme used to extract MW. (b-c) Memory window [PITH_FULL_IMAGE:figures/full_fig_p005_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: Overdrive current at Vg=Vth+3V (=Iov) as a function of Vth for PGM and ERS states (Vt,P GM and Vt,ERS) for all annealing conditions. budget, lowers the Oxygen vacancies in channel, which leads to higher channel and contact resistance in the oxide-semiconductor channel. In FeFETs, this effect primarily impacts the high-Vth erased state, where the depleted channel places the device in an injection-limited re… view at source ↗
Figure 5
Figure 5. Figure 5: Polarization vs. Voltage characteristics on MFM capacitor for before and after [PITH_FULL_IMAGE:figures/full_fig_p007_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: Zoomed-in GI-XRD post-capping for unannealed and 650 [PITH_FULL_IMAGE:figures/full_fig_p008_6.png] view at source ↗
Figure 7
Figure 7. Figure 7: Retention at room temperature under respective maximum thermal budget con [PITH_FULL_IMAGE:figures/full_fig_p009_7.png] view at source ↗
read the original abstract

In this work, we report a systematic study of the impact of high-temperature post-capping thermal annealing on the memory characteristics of Oxide-semiconductor channel ferroelectric field-effect transistors (OS-FeFETs). Using an identical engineered ferroelectric gate stack 8nm Hf0.5Zr0.5O2 (HZO) / 3 nm Al2O3 / 8 nm HZO (8/3/8) and a hybrid capping layer (3 nm HfO2 + 3 nm Al2O3), 10 percent Ga doped InO (IGO) channel and 4 percent W doped InO (IWO) channel FeFETs remain functional after annealing at temperatures up to 650 C for durations of up to 30 min and 10 min, respectively; further annealing results in irreversible loss of conduction and device failure. Detailed electrical analysis reveals that the MW enhancement originates from a preferential positive shift in the erased-state threshold voltage, while the programmed-state threshold voltage remains comparatively stable. Grazing-incidence X-ray diffraction measurements further indicate structural evolution in the IWO and IGO oxide channels with increasing annealing temperature, supporting the observed electrical trends.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 0 minor

Summary. The manuscript reports a study of post-capping thermal annealing effects on oxide-semiconductor channel FeFETs using an identical 8/3/8 HZO/Al2O3/HZO ferroelectric gate stack and hybrid HfO2/Al2O3 capping layer. It claims that 10% Ga-doped InO (IGO) and 4% W-doped InO (IWO) channel devices remain functional after annealing up to 650°C (30 min for IGO, 10 min for IWO), with memory window enhancement arising from preferential positive shifts in erased-state threshold voltage; further annealing causes irreversible loss of conduction attributed to channel structural evolution, supported by grazing-incidence XRD trends.

Significance. If the attribution of electrical degradation solely to channel evolution is confirmed, the work establishes practical thermal processing limits for OS-FeFET integration, which is relevant for back-end-of-line compatibility in ferroelectric memory. The correlation between GIXRD structural changes and VT/MW trends provides a useful experimental link, though the absence of full datasets limits the strength of the conclusions.

major comments (2)
  1. [Abstract] Abstract and electrical analysis sections: The central attribution of device failure after 650°C annealing to IGO/IWO channel structural evolution (supported by GIXRD) assumes the fixed 8/3/8 HZO/Al2O3/HZO ferroelectric stack and hybrid capping layer remain electrically intact. No post-anneal P-E hysteresis, C-V, or leakage data on the gate stack itself are described to isolate channel effects from possible stack degradation.
  2. [Abstract] Abstract: The reported electrical trends (MW enhancement from erased-state VT shift, irreversible conduction loss) are described as arising from detailed analysis, but the manuscript lacks full datasets, error bars, statistical details, or exclusion criteria, leaving the robustness of the cross-temperature claims moderately supported at best.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the careful review and valuable comments on our manuscript. We address each major comment below.

read point-by-point responses

  1. Referee: [Abstract] Abstract and electrical analysis sections: The central attribution of device failure after 650°C annealing to IGO/IWO channel structural evolution (supported by GIXRD) assumes the fixed 8/3/8 HZO/Al2O3/HZO ferroelectric stack and hybrid capping layer remain electrically intact. No post-anneal P-E hysteresis, C-V, or leakage data on the gate stack itself are described to isolate channel effects from possible stack degradation.

    Authors: This is an important point. However, since the gate stack is identical for both IGO and IWO channel devices, and the maximum annealing temperature and time before failure differ between the two channel materials (650°C for 30 min in IGO vs. 10 min in IWO), the degradation cannot be attributed to the gate stack, which would affect both similarly. The correlation with channel-specific GIXRD changes further supports our interpretation. We will add this clarification to the revised manuscript to strengthen the argument. revision: partial

  2. Referee: [Abstract] Abstract: The reported electrical trends (MW enhancement from erased-state VT shift, irreversible conduction loss) are described as arising from detailed analysis, but the manuscript lacks full datasets, error bars, statistical details, or exclusion criteria, leaving the robustness of the cross-temperature claims moderately supported at best.

    Authors: We agree that including more comprehensive data presentation will improve the manuscript. In the revision, we will add error bars to the relevant plots, specify the number of devices measured at each temperature, and include details on the analysis methods and any data exclusion criteria used. revision: yes

Circularity Check

0 steps flagged

No circularity: purely experimental report with no derivations or models

full rationale

The manuscript is an experimental study reporting measured electrical characteristics (threshold voltage shifts, memory window) and GIXRD data on annealed OS-FeFET devices. No equations, fitted parameters, predictions, or theoretical derivations appear in the provided text or abstract. Claims rest on direct observation of device behavior before/after annealing and structural measurements; the attribution of trends to channel evolution is an interpretive conclusion from data, not a self-referential reduction. No self-citations, ansatzes, or uniqueness theorems are invoked in any load-bearing step. The derivation chain is empty by construction, satisfying the default expectation of no circularity for experimental reports.

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 0 invented entities

Experimental materials paper with no mathematical derivations, free parameters, or postulated entities; relies on standard domain assumptions about measurement validity.

axioms (1)
  • domain assumption Electrical characterization and grazing-incidence X-ray diffraction accurately capture threshold voltage shifts and structural evolution without significant artifacts.
    The paper's conclusions rest on these techniques linking annealing temperature to device behavior.

pith-pipeline@v0.9.1-grok · 5812 in / 1381 out tokens · 27641 ms · 2026-06-27T18:32:36.968440+00:00 · methodology

discussion (0)

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