pith. sign in

arxiv: 2606.13089 · v1 · pith:ZR47IK3Ynew · submitted 2026-06-11 · 💻 cs.NE

Multi-Objective Coevolution of Prompts and Templates for Circuit Approximation

Martin Tomasovic , Lukas Sekanina This is my paper

Pith reviewed 2026-06-27 05:18 UTC · model grok-4.3

classification 💻 cs.NE
keywords approximate multipliersevolutionary algorithmslarge language modelscircuit designco-evolutionprompt templatesapproximate computing
0
0 comments X

The pith

Co-evolving prompt templates with circuits lets an LLM discover superior 8-bit approximate multipliers.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

This paper introduces a co-evolutionary approach that evolves both a population of approximate circuit designs and a population of prompt templates. These templates guide an off-the-shelf large language model to propose modifications to the circuits. The goal is to optimize 8-bit multipliers for multiple objectives such as minimizing error while reducing area. Experiments show that the method finds designs with better error-area trade-offs than the highly optimized circuits in the EvoApproxLib library. The technique requires no domain-specific training of the language model.

Core claim

The paper claims that a co-evolutionary algorithm simultaneously evolving candidate circuits and prompt templates can steer an unmodified LLM to generate modifications that yield 8-bit approximate multipliers with improved error-area trade-offs over those in EvoApproxLib.

What carries the argument

The co-evolutionary algorithm maintaining separate populations for circuits and for prompt templates that direct LLM-based circuit edits.

If this is right

  • Approximate circuit design can be automated for error-resilient applications without expert intervention.
  • Multi-objective optimization becomes feasible for other circuit components using similar LLM guidance.
  • The method scales to different target objectives like power or latency in addition to error and area.
  • Library-based approximate designs can be surpassed by dynamically evolved prompts and circuits.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • LLMs might serve as general-purpose design assistants in hardware when paired with evolutionary steering.
  • Similar co-evolution could apply to prompt engineering in other technical domains beyond circuits.
  • Testing on larger multipliers or different arithmetic units would reveal the method's broader applicability.

Load-bearing premise

The off-the-shelf LLM can produce useful circuit changes when directed by the evolved prompt templates.

What would settle it

A run of the algorithm that fails to produce any 8-bit multiplier improving the error-area Pareto front of EvoApproxLib across the tested objectives.

Figures

Figures reproduced from arXiv: 2606.13089 by Lukas Sekanina, Martin Tomasovic.

Figure 1
Figure 1. Figure 1: The proposed circuit approximation method that utilizes a co-evolutionary algorithm evolving a population of circuits (left-hand side) and a population of circuit￾producing templates (right-hand side) [PITH_FULL_IMAGE:figures/full_fig_p006_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: Final Pareto fronts obtained from 10 runs of HC, CoEA-3-5, and CoEA-1-15. The same initial population of circuits was used in the i-th run of CoEA algorithms. The target specification is depicted with a red cross [PITH_FULL_IMAGE:figures/full_fig_p011_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: The hypervolume indicator computed from the final Pareto front constructed from 10 independent runs of HC, 6CoEA-3-5, and CoEA-1-15 [PITH_FULL_IMAGE:figures/full_fig_p011_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: The progress of evolution of CoEA-3-5 and CoEA-1-15, where the hypervolume indicator is represented as a box plot of the best solutions (in 10 runs) reached in a given generation. 5.2 Long runs Based on the results reported in the previous section, we used CoEA with pa￾rameters specified in Section 4, k = 3 and g = 27 to design approximate 8-bit multipliers for 32 target error-area pairs (see red crosses i… view at source ↗
Figure 5
Figure 5. Figure 5: The WCE-Area trade-offs for 8-bit approximate multipliers generated by the proposed CoEA or taken from EvoApproxLib. The united global Pareto front contains non-dominated solutions generated by CoEA (green square) and taken from EvoAp￾proxLib (blue dots). The remaining points are dominated. The target specifications provided to CoEA are depicted with red crosses. 5.3 Time requirements A single call to the … view at source ↗
Figure 6
Figure 6. Figure 6: The MSE-Area trade-offs for 8-bit approximate multipliers generated by the proposed CoEA or taken from EvoApproxLib. The united global Pareto front contains non-dominated solutions generated by CoEA (green square) and taken from EvoAp￾proxLib (blue dots). The remaining points are dominated. The target specifications provided to CoEA are depicted with red crosses. 6 Conclusions We introduced a co-evolutiona… view at source ↗
read the original abstract

Approximate multipliers deliberately relax computational accuracy to achieve gains in power efficiency, latency, and silicon area, which makes them well-suited for error-resilient applications such as neural networks. In this work, we introduce a co-evolutionary algorithm that leverages an off-the-shelf large language model (LLM) without requiring domain-specific training to automate the design of optimized 8-bit approximate multipliers. The approach simultaneously evolves a population of candidate circuits and a population of prompt templates that steer LLM-driven modifications. Experimental results for several target design objectives demonstrate that the proposed method discovers approximate multipliers with improved error-area trade-offs compared to highly optimized circuits from the EvoApproxLib library.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 2 minor

Summary. The manuscript introduces a co-evolutionary algorithm that simultaneously evolves populations of 8-bit approximate multiplier circuits and prompt templates to steer modifications generated by an off-the-shelf LLM. The central experimental claim is that the resulting circuits achieve improved error-area trade-offs relative to entries from the EvoApproxLib library across multiple design objectives.

Significance. If the experimental claims are substantiated with reproducible protocols, the work would demonstrate a practical method for using prompt evolution to adapt general-purpose LLMs to circuit approximation tasks without domain-specific fine-tuning. This could extend evolutionary design techniques into LLM-augmented hardware optimization and provide a template for coevolving steering mechanisms in other engineering domains.

major comments (2)
  1. [Section 4] Section 4 (Experimental Evaluation): the manuscript reports superior error-area trade-offs but does not specify the number of independent evolutionary runs, the statistical tests applied to the Pareto fronts, or the precise definitions and measurement procedures for the error and area metrics used in the comparison with EvoApproxLib. These omissions prevent verification of the central claim.
  2. [Section 3.2] Section 3.2 (LLM Integration): the mechanism by which evolved prompt templates are applied to generate circuit modifications, including the exact format of LLM outputs, the parsing of those outputs into netlist changes, and any rejection or repair steps, is described at a level that does not permit independent reproduction of the reported circuits.
minor comments (2)
  1. [Figure 3] Figure 3: axis labels and legend entries use inconsistent abbreviations for error metrics; standardize notation with the definitions given in Section 2.
  2. [Introduction] The reference list omits the original EvoApproxLib publication; add the citation when first mentioning the library in the introduction.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the constructive comments, which identify key gaps in reproducibility. We will revise the manuscript to address both points and provide the requested details.

read point-by-point responses

  1. Referee: [Section 4] Section 4 (Experimental Evaluation): the manuscript reports superior error-area trade-offs but does not specify the number of independent evolutionary runs, the statistical tests applied to the Pareto fronts, or the precise definitions and measurement procedures for the error and area metrics used in the comparison with EvoApproxLib. These omissions prevent verification of the central claim.

    Authors: We agree these details are necessary. The revised Section 4 will report that 30 independent runs were executed per objective, that the Mann-Whitney U test was used to assess statistical significance of Pareto-front differences, and that error is defined as mean absolute relative error obtained by exhaustive enumeration over all 65536 input combinations while area is the gate count reported by the ABC synthesis tool under the identical script used for EvoApproxLib. revision: yes

  2. Referee: [Section 3.2] Section 3.2 (LLM Integration): the mechanism by which evolved prompt templates are applied to generate circuit modifications, including the exact format of LLM outputs, the parsing of those outputs into netlist changes, and any rejection or repair steps, is described at a level that does not permit independent reproduction of the reported circuits.

    Authors: We concur that the current description is insufficient for reproduction. The revised Section 3.2 will include the precise prompt-template syntax, the expected LLM output format (Verilog module fragments), the deterministic parser that converts outputs into netlist edits, and the validation/repair procedure that discards syntactically invalid edits and retries the LLM call up to three times before falling back to the parent circuit. revision: yes

Circularity Check

0 steps flagged

No significant circularity

full rationale

The paper introduces a co-evolutionary algorithm that jointly evolves circuits and LLM prompt templates for 8-bit approximate multiplier design, then reports empirical error-area trade-offs against the external EvoApproxLib library. No derivation step reduces by construction to fitted inputs, self-definitions, or load-bearing self-citations; the central claim is an experimental comparison that remains independently verifiable. This matches the reader's assessment of minimal circularity risk.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 0 invented entities

Abstract-only review yields no explicit free parameters, axioms, or invented entities; the central claim rests on the unelaborated premise that LLM steering via evolved prompts works without domain training.

pith-pipeline@v0.9.1-grok · 5631 in / 1058 out tokens · 20501 ms · 2026-06-27T05:18:17.671230+00:00 · methodology

discussion (0)

Sign in with ORCID, Apple, or X to comment. Anyone can read and Pith papers without signing in.

Reference graph

Works this paper leans on

26 extracted references · 19 canonical work pages · 1 internal anchor

  1. [1]

    ACM Comput

    Armeniakos, G., Zervakis, G., Soudris, D., Henkel, J.: Hardware approximate tech- niques for deep neural network accelerators: A survey. ACM Comput. Surv.55(4), 83:1–83:36 (2023). https://doi.org/10.1145/3527156

    work page doi:10.1145/3527156 2023

  2. [2]

    In: Proc

    Caetano, V., Teixeira, M.C., Pappa, G.L.: Symbolic regression trees as embedded representations. In: Proc. of the Genetic and Evolutionary Computation Confer- ence. pp. 411–419. ACM (2023). https://doi.org/10.1145/3583131.3590423

    work page doi:10.1145/3583131.3590423 2023

  3. [3]

    In: Proc

    Ceska, M., Matyas, J., Mrazek, V., Sekanina, L., Vasicek, Z., Vojnar, T.: Approxi- mating complex arithmetic circuits with formal error guarantees: 32-bit multipliers accomplished. In: Proc. of 36th IEEE/ACM Int. Conf. On Computer Aided Design. pp. 416–423. IEEE (2017)

    2017

  4. [4]

    A fast and elitist multiobjective genetic algorithm: NSGA-II

    Deb, K., et al.: A fast and elitist multiobjective genetic algorithm: NSGA- II. IEEE Transactions on Evolutionary Computation6(2), 182–197 (2002). https://doi.org/10.1109/4235.996017

    work page doi:10.1109/4235.996017 2002

  5. [5]

    Hemberg, E., Jorgensen, S., O’Reilly, U.M.: Survey of Genetic Programming and Large Language Models, pp. 67–86. Springer Nature Singapore (2025). https://doi.org/10.1007/978-981-96-0077-9˙4

    work page doi:10.1007/978-981-96-0077-9 2025

  6. [6]

    In: 7th ACM/IEEE Symposium on Machine Learning for CAD

    Hong, C., Roberts, B., An, H., Um, A., Ratan, A., Shao, Y.S.: hdl2v: A code translation dataset for enhanced LLM verilog generation. In: 7th ACM/IEEE Symposium on Machine Learning for CAD. pp. 1–8. IEEE (2025). https://doi.org/10.1109/MLCAD65511.2025.11189055

    work page doi:10.1109/mlcad65511.2025.11189055 2025

  7. [7]

    In: Advances in Artificial Life, ECAL 2013, Proceedings of the Twelfth Eu- ropean Conference on the Synthesis and Simulation of Living Systems

    Hrbacek, R., Drahosova, M.: Coevolutionary cartesian genetic programming in FPGA. In: Advances in Artificial Life, ECAL 2013, Proceedings of the Twelfth Eu- ropean Conference on the Synthesis and Simulation of Living Systems. pp. 431–438. MIT Press, Cambridge (2013). https://doi.org/10.7551/978-0-262-31709-2-ch062

    work page doi:10.7551/978-0-262-31709-2-ch062 2013

  8. [8]

    In: Reda, S., Shafique, M

    Jiang, H., Liu, L., Lombardi, F., Han, J.: Approximate arithmetic circuits: Design and evaluation. In: Reda, S., Shafique, M. (eds.) Approximate Circuits, Method- ologies and CAD, pp. 67–98. Springer (2019)

    2019

  9. [9]

    Jiang, H., Santiago, F.J.H., Mo, H., Liu, L., Han, J.: Approximate arithmetic circuits: A survey, characterization, and recent applications. Proc. IEEE108(12), 2108–2135 (2020)

    2020

  10. [10]

    In: Proc

    Liu, W., Xu, J., Wang, D., Lombardi, F.: Design of approximate logarithmic mul- tipliers. In: Proc. of the Great Lakes Symposium on VLSI. p. 47–52. ACM (2017). https://doi.org/10.1145/3060403.3060409

    work page doi:10.1145/3060403.3060409 2017

  11. [11]

    In: Proc of the Genetic and Evolutionary Computation Conference

    Liventsev, V., Grishina, A., H¨ arm¨ a, A., Moonen, L.: Fully autonomous programming with large language models. In: Proc of the Genetic and Evolutionary Computation Conference. pp. 1146–1155. ACM (2023). https://doi.org/10.1145/3583131.3590481

    work page doi:10.1145/3583131.3590481 2023

  12. [12]

    In: Design, Automation & Test in Europe Conference & Exhibi- tion

    Mrazek, V., Hrbacek, R., Vasicek, Z., Sekanina, L.: Evoapprox8b: Library of ap- proximate adders and multipliers for circuit design and benchmarking of approxi- mation methods. In: Design, Automation & Test in Europe Conference & Exhibi- tion. pp. 258–261 (2017). https://doi.org/10.23919/DATE.2017.7926993 To appear at Parallel Problem Solving From Nature ...

    work page doi:10.23919/date.2017.7926993 2017

  13. [13]

    IEEE Journal on Emerg- ing and Selected Topics in Circuits and Systems10(4), 406–418 (2020)

    Mrazek, V., Sekanina, L., Vasicek, Z.: Libraries of approximate circuits: Auto- mated design and application in CNN accelerators. IEEE Journal on Emerg- ing and Selected Topics in Circuits and Systems10(4), 406–418 (2020). https://doi.org/10.1109/JETCAS.2020.3032495

    work page doi:10.1109/jetcas.2020.3032495 2020

  14. [14]

    Coevolutionary Principles, pp

    Popovici, E., Bucci, A., Wiegand, R.P., De Jong, E.D.: Handbook of Natural Com- puting, chap. Coevolutionary Principles, pp. 987–1033. Springer (2012)

    2012

  15. [15]

    Evolutionary computation8(1), 1–29 (2000)

    Potter, M.A., De Jong, K.A.: Cooperative coevolution: An architecture for evolving coadapted subcomponents. Evolutionary computation8(1), 1–29 (2000)

    2000

  16. [16]

    Mathematics13(5) (2025)

    Shem-Tov, E., Sipper, M., Elyasaf, A.: Bert mutation: Deep transformer model for masked uniform mutation in genetic programming. Mathematics13(5) (2025). https://doi.org/10.3390/math13050779

    work page doi:10.3390/math13050779 2025

  17. [17]

    IEEE Trans

    Sobania, D., Petke, J., Briesch, M., Rothlauf, F.: A comparison of large language models and genetic programming for program synthesis. IEEE Trans. Evol. Com- put.29(4), 1434–1448 (2025). https://doi.org/10.1109/TEVC.2024.3410873

    work page doi:10.1109/tevc.2024.3410873 2025

  18. [18]

    ACM Comput

    Stanley-Marbell, P., Alaghi, A., Carbin, M., Darulova, E., Dolecek, L., Gerstlauer, A., Gillani, G., Jevdjic, D., Moreau, T., Cacciotti, M., Daglis, A., Jerger, N.E., Falsafi, B., Misailovic, S., Sampson, A., Zufferey, D.: Exploiting errors for efficiency: A survey from circuits to applications. ACM Comput. Surv.53(3) (2020)

    2020

  19. [19]

    Team, Q.: Qwen3 technical report (2025), https://arxiv.org/abs/2505.09388

    work page internal anchor Pith review Pith/arXiv arXiv 2025

  20. [20]

    In: Proc

    Teixeira, M.C., Pappa, G.L.: Transformers as surrogate models for genetic pro- gramming in automl tasks. In: Proc. of the Genetic and Evolutionary Computation Conference. p. 472–480. ACM (2025). https://doi.org/10.1145/3712256.3726396

    work page doi:10.1145/3712256.3726396 2025

  21. [21]

    Verigen: A large language model for verilog code generation,

    Thakur, S., Ahmad, B., Pearce, H., Tan, B., Dolan-Gavitt, B., Karri, R., Garg, S.: Verigen: A large language model for verilog code generation. ACM Trans. Design Autom. Electr. Syst.29(3), 46:1–46:31 (2024). https://doi.org/10.1145/3643681

    work page doi:10.1145/3643681 2024

  22. [22]

    IEEE Transactions on Evolutionary Computation29(2), 534–554 (2025)

    Wu, X., Wu, S.H., Wu, J., Feng, L., Tan, K.C.: Evolutionary computation in the era of large language model: Survey and roadmap. IEEE Transactions on Evolutionary Computation29(2), 534–554 (2025). https://doi.org/10.1109/TEVC.2024.3506731

    work page doi:10.1109/tevc.2024.3506731 2025

  23. [23]

    In: Proc

    Xie, L., Zhang, Y., Tang, Z., Chung, E., Li, G., Wang, Z.: Co-evolution of large language models and configuration strategies to enhance surrogate- assisted evolutionary algorithm. In: Proc. of the 31st ACM SIGKDD Conf. on Knowledge Discovery and Data Mining V.2. p. 3321–3332. ACM (2025). https://doi.org/10.1145/3711896.3736882

    work page doi:10.1145/3711896.3736882 2025

  24. [24]

    In: 2025 IEEE 38th International System-on-Chip Conference (SOCC)

    Xu, K., Schwachhofer, D., Blocklove, J., Polian, I., Domanski, P., Pfl¨ uger, D., Garg, S., Karri, R., Sinanoglu, O., Knechtel, J., Zhao, Z., Schlichtmann, U., Li, B.: Large language models (LLMs) for electronic design automation (EDA) : Spe- cial session paper. In: 2025 IEEE 38th International System-on-Chip Conference (SOCC). pp. 1–6 (2025). https://doi...

    work page doi:10.1109/socc66126.2025.11235352 2025

  25. [25]

    IEEE Journal on Emerging and Selected Topics in Circuits and Systems15(2), 349–360 (2025)

    Yi, S., Zuo, W., Wu, H., Dai, R., Qian, W., Chen, J.: GPTAC: Domain-specific gen- erative pre-trained model for approximate circuit design exploration. IEEE Journal on Emerging and Selected Topics in Circuits and Systems15(2), 349–360 (2025)

    2025

  26. [26]

    In: Proc

    Zarb, D.V., Parks, G.T., Kipouros, T.: Program synthesis with LLM- predicted minimal specialized grammars. In: Proc. of the Genetic and Evolutionary Computation Conference. pp. 1072–1080. ACM (2025). https://doi.org/10.1145/3712256.3726430

    work page doi:10.1145/3712256.3726430 2025