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arxiv: 2606.30327 · v1 · pith:35ZT2CKLnew · submitted 2026-06-29 · 🪐 quant-ph

Phase-Altered Interleaved Randomized Benchmarking for Compiled Quantum Gates

Simona K. Grigorova , Nikolay V. Vitanov , Boyan T. Torosov This is my paper

Pith reviewed 2026-06-30 06:33 UTC · model grok-4.3

classification 🪐 quant-ph
keywords phase-altered interleaved randomized benchmarkingvirtual phase gatescompiled Toffoli gateinterleaved randomized benchmarkingquantum error ratessuperconducting processorssoftware-defined phases
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The pith

Virtual phase gates do not measurably change the error estimates obtained from interleaved randomized benchmarking of compiled quantum gates.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper introduces phase-altered interleaved randomized benchmarking to check whether inserting or removing virtual phase operations changes the error rate extracted by standard IRB. It does so by running paired IRB sequences on the same compiled gate, one with phases stripped and one with virtual Z rotations added. Experiments on a compiled Toffoli gate on IBM superconducting processors show the difference in decay parameters is consistent with zero within uncertainty. This result indicates that software-defined phases can be ignored when extracting IRB error rates under the tested compilation and execution conditions. The protocol supplies a lightweight way to validate benchmarking workflows that rely on virtual phase operations.

Core claim

PA-IRB measures the difference Δr = r_d − r_s between the IRB decay rates for phase-dressed and phase-stripped versions of the same compiled gate. In the case study of a Toffoli gate with virtual T and T† gates on IBM processors, this difference is consistent with zero across multiple calibration runs, showing that the virtual phase operations do not alter the extracted error rate beyond statistical fluctuations.

What carries the argument

The phase-altered interleaved randomized benchmarking (PA-IRB) protocol, which executes paired IRB sequences differing only in the inclusion of virtual phase gates and computes their difference in decay parameters with combined uncertainty.

If this is right

  • Virtual phase addition or removal does not measurably alter the IRB-derived error estimate under the employed compilation and execution stack.
  • The same paired comparison can place operational bounds on the contribution of non-Clifford components to the compiled gate error even when those components are physically executed.
  • PA-IRB provides a lightweight, abstraction-aware diagnostic for benchmarking workflows involving software-defined phase operations.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The paired-test approach could be applied to other virtual frame updates beyond phases to check their impact on error extraction.
  • If Δr remains zero across more gate types and processors, compilation choices that use virtual phases would be confirmed as neutral for IRB-based error characterization.
  • The protocol could be extended to isolate the error contribution from non-Clifford gates when they are implemented with physical pulses rather than virtually.

Load-bearing premise

The paired phase-stripped and phase-dressed sequences differ only by the virtual phases, with no other systematic differences from the compilation or control stack affecting the IRB decay parameter.

What would settle it

Repeated PA-IRB runs on the same compiled gate where the measured Δr exceeds the combined uncertainty by several standard deviations would show that virtual phases do affect the extracted error estimate.

Figures

Figures reproduced from arXiv: 2606.30327 by Boyan T. Torosov, Nikolay V. Vitanov, Simona K. Grigorova.

Figure 2
Figure 2. Figure 2: FIG. 2. Interleaved randomized benchmarking circuit. Again [PITH_FULL_IMAGE:figures/full_fig_p002_2.png] view at source ↗
Figure 1
Figure 1. Figure 1: FIG. 1. Randomized benchmarking circuit consisting of ran [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 3
Figure 3. Figure 3: FIG. 3. Schematic compiled operation [PITH_FULL_IMAGE:figures/full_fig_p003_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: FIG. 4. Phase-stripped implementation [PITH_FULL_IMAGE:figures/full_fig_p003_4.png] view at source ↗
Figure 6
Figure 6. Figure 6: FIG. 6. Schematic representation of a generic Toffoli gate [PITH_FULL_IMAGE:figures/full_fig_p004_6.png] view at source ↗
Figure 5
Figure 5. Figure 5: FIG. 5. Phase-dressed construction where non-Clifford phase [PITH_FULL_IMAGE:figures/full_fig_p004_5.png] view at source ↗
Figure 7
Figure 7. Figure 7: FIG. 7. Transpiled Toffoli (CCX) gate circuit as generated by Qiskit’s transpiler for a subset of three adjacent qubits on [PITH_FULL_IMAGE:figures/full_fig_p005_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: FIG. 8. Randomized benchmarking (RB) and interleaved [PITH_FULL_IMAGE:figures/full_fig_p005_8.png] view at source ↗
read the original abstract

Interleaved randomized benchmarking (IRB) provides a scalable estimate of a gate's error rate, but its standard guarantees require the interleaved gate to be Clifford~\cite{Magesan2012Interleaved,magesan2012characterizing}. In superconducting processors, many non-Clifford phase gates in compiled circuits are implemented virtually as software-defined frame updates rather than as additional control pulses~\cite{mckay2017efficient}. This raises the question of whether inserting or removing such virtual phases measurably changes IRB error estimates. We introduce \emph{phase-altered interleaved randomized benchmarking} (PA-IRB), a paired-IRB diagnostic protocol comparing phase-stripped and phase-dressed Clifford interleaving gates derived from the same compiled implementation. PA-IRB reports $\Delta r=r_d-r_s$ with combined uncertainty to test whether virtual phase gates affect the extracted IRB decay beyond statistical error. As a case study, we apply PA-IRB to a compiled Toffoli gate executed on IBM superconducting processors, where the constituent $T/T^\dagger$ gates are implemented as virtual $Z$ rotations. Across tested calibration runs, $\Delta r$ is consistent with zero within uncertainty, indicating that virtual phase addition or removal does not measurably alter the IRB-derived error estimate under the employed compilation and execution stack. More generally, PA-IRB provides a lightweight, abstraction-aware diagnostic for benchmarking workflows involving software-defined phase operations. The same paired comparison can also be used to place operational bounds on the contribution of non-Clifford components to the compiled gate error, even when those components are physically executed rather than implemented virtually.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

1 major / 1 minor

Summary. The paper introduces phase-altered interleaved randomized benchmarking (PA-IRB), a paired-IRB protocol that compares the decay parameter r for phase-stripped (r_s) and phase-dressed (r_d) Clifford interleaving sequences derived from the same compiled implementation. It reports an experimental case study on a compiled Toffoli gate executed on IBM superconducting processors (with T/T† implemented as virtual Z rotations), finding Δr = r_d − r_s consistent with zero within combined uncertainty across calibration runs, and positions PA-IRB as a diagnostic for virtual-phase effects and non-Clifford error bounds.

Significance. If the paired sequences differ only by the virtual phase frames, the result supplies a lightweight, abstraction-aware check that virtual Z operations do not measurably alter IRB-derived error rates under the tested compilation and control stack; the same paired comparison supplies a route to operational bounds on non-Clifford contributions even when those gates are physically executed.

major comments (1)
  1. [Abstract] Abstract: the headline claim that Δr consistent with zero demonstrates that virtual phase addition/removal does not affect the IRB error estimate is load-bearing on the assumption that the phase-stripped and phase-dressed interleaving sequences differ solely by the presence/absence of virtual Z frames. The manuscript supplies no explicit verification (pulse-schedule comparison, timing analysis, or calibration-parameter audit) that compilation, scheduling, or control-stack outputs remain identical when the frame updates are toggled; without such evidence the observed Δr could arise from unintended differences rather than from the virtual phases themselves.
minor comments (1)
  1. [Abstract] The abstract states that Δr is reported 'with combined uncertainty' but does not specify the statistical model, number of calibration runs, or exclusion criteria used to combine the uncertainties.

Simulated Author's Rebuttal

1 responses · 0 unresolved

We thank the referee for their careful reading of the manuscript and for identifying a point that strengthens the interpretation of our results. We address the major comment below.

read point-by-point responses

  1. Referee: [Abstract] Abstract: the headline claim that Δr consistent with zero demonstrates that virtual phase addition/removal does not affect the IRB error estimate is load-bearing on the assumption that the phase-stripped and phase-dressed interleaving sequences differ solely by the presence/absence of virtual Z frames. The manuscript supplies no explicit verification (pulse-schedule comparison, timing analysis, or calibration-parameter audit) that compilation, scheduling, or control-stack outputs remain identical when the frame updates are toggled; without such evidence the observed Δr could arise from unintended differences rather than from the virtual phases themselves.

    Authors: We agree that the manuscript does not contain an explicit verification (e.g., pulse-schedule comparison or timing audit) that the two interleaving sequences differ only by the virtual Z frames. The original text relies on the documented behavior of the IBM compilation stack, in which virtual Z rotations are realized exclusively as software frame updates that leave pulse schedules, timing, and calibration parameters unchanged. To address the referee’s concern directly, we will revise the manuscript by adding a short subsection (or appendix) that (i) states the compilation procedure used to toggle the phase frames, (ii) presents representative pulse-schedule excerpts confirming identical timing and pulse content, and (iii) notes that no calibration parameters are altered. This addition will make the assumption explicit and the interpretation of Δr more robust. revision: yes

Circularity Check

0 steps flagged

No significant circularity; protocol is a direct empirical comparison

full rationale

The paper defines PA-IRB as a paired difference measurement Δr = r_d − r_s on sequences derived from the same compiled gate, using standard IRB decay parameters from Magesan et al. The reported result is an experimental observation that Δr is consistent with zero within uncertainty. No equations, fits, or claims reduce a prediction to its own inputs by construction, nor does any load-bearing step rely on self-citation chains or imported uniqueness theorems. The protocol and conclusion remain self-contained against external IRB benchmarks and the stated compilation assumptions.

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 0 invented entities

The central claim rests on the applicability of standard IRB assumptions to the compiled gate and on the experimental isolation of virtual-phase effects; no free parameters, new entities, or ad-hoc axioms are introduced in the abstract.

axioms (1)
  • domain assumption Interleaved randomized benchmarking decay parameters remain well-defined and comparable when the interleaver is a compiled gate containing virtual phases.
    The protocol invokes IRB guarantees that were originally stated for Clifford gates; the abstract applies them to a non-Clifford compiled Toffoli without additional justification.

pith-pipeline@v0.9.1-grok · 5835 in / 1330 out tokens · 43809 ms · 2026-06-30T06:33:59.436762+00:00 · methodology

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Forward citations

Cited by 1 Pith paper

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score.

  1. Non-Clifford Benchmarking via Ensemble Feature Selection

    quant-ph 2026-07 unverdicted novelty 6.0

    Ensemble Feature Selection trains a ridge-regression linear estimator on an ensemble of noisy channels to estimate process infidelity of non-Clifford gates, validated against IRB on IBM hardware with 0.01 precision ov...

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