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REVIEW 3 major objections 5 minor 24 references

HiFuzz: Hierarchical Reinforcement Learning for Semantic-Aware and Adaptive CPU Fuzzing

T0 review · 3 major / 5 minor · reviewed 2026-07-11 · grok-4.5

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Pith's one-line read A two-level RL generator builds valid RISC-V tests that reach deeper processor states and find more bugs than mutation-based fuzzers.

desk verdict Solid hierarchical constructive RL fuzzer with real multi-DUT gains; the design is the contribution, but the +48.9% headline rests on single-run 24h curves. read the letter →

arxiv 2607.06619 v1 pith:FYJQYRQO submitted 2026-07-07 cs.AR cs.LG

Ya Wang , Hanwei Fan , Zhenguo Liu , Xiaofeng Zhou , Yangdi Lyu , Jiang Xu , Wei Zhang This is my paper · ORCID
classification cs.ARcs.LG
keywords hardwarefuzzingreinforcementlearningRISC-VfunctionalverificationhierarchicalRLcoverage-guidedtestingbasic-blockencoder
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

Processor verification is stuck because random mutation often wrecks instruction semantics, so most tests never exercise deep pipeline or control-register states. HiFuzz replaces mutation with a hierarchical generator: one agent chooses the global program layout (memory, basic-block count, control flow) and a second agent fills each basic block with instruction mixes. Sparse coverage rewards are fixed by two mechanisms—an offline-trained semantic encoder that scores basic-block novelty without waiting for RTL simulation, and a module-level adaptive weighting scheme that keeps easy modules from dominating the reward. On three real RISC-V cores the method produces higher coverage per test and detects more injected bugs than current state-of-the-art fuzzers under the same 24-hour budget.

What carries the argument

Dual-agent hierarchy (Program Agent + Basic Block Agent) closed by a Semantic-Aware Basic Block Encoder that supplies intrinsic novelty rewards and an Adaptive Coverage Reward Mechanism that reweights module-level coverage gains.

What would settle it

Re-run the same 24-hour Rocket/BOOM/CVA6 campaigns with multiple random seeds and report mean control-register coverage and Encarsia detection rates with error bars; if HiFuzz no longer leads Cascade, the central claim fails.

Watch

Extended reading notes

Core claim

HiFuzz shows that constructive CPU fuzzing can be cast as a hierarchical RL problem whose two agents, guided by a DUT-agnostic basic-block novelty encoder and a UCB-style module-coverage reward, generate denser, higher-prevalence RISC-V programs that reach deeper architectural states and find more bugs than mutation-based or purely random constructive baselines.

Load-bearing premise

That one 24-hour run per fuzzer and DUT, plus access to module-level coverage, is enough to claim consistent superiority.

Editorial extensions

If this is right

  • Constructive fuzzers can drop blind mutation once hierarchical RL plus semantic intrinsic rewards keep programs valid and informative.
  • Module-aware adaptive rewards can reduce the masking effect that hides under-covered units behind aggregate coverage scores.
  • A single DUT-agnostic basic-block encoder can transfer across Rocket, BOOM and CVA6 without retraining.
  • Longer dependency chains and higher instruction prevalence become practical targets for RL program generators.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • The same two-level split could be reused for other structured generation tasks (e.g., constrained random testbenches) where global layout and local filling have different timescales.
  • If only global coverage is available, ACRM collapses and the advantage may shrink to the hierarchical generator alone.
  • Extending the Program Agent to multi-hart layouts would be a direct next step for memory-ordering bugs currently out of scope.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 5 minor

Summary. HiFuzz proposes a hierarchical reinforcement-learning framework for constructive RISC-V CPU fuzzing that replaces mutation with a two-level generator: a Rainbow-DQN Program Agent that chooses global program layout (memory footprint, BB count, length/privilege mix) and a PPO Basic Block Agent that outputs category-level instruction distributions and termination modes, with a constrained generator enforcing validity. To address sparse and biased rewards, the system adds (i) a DUT-agnostic Semantic-Aware Basic Block Encoder (structured tokenizer + Bi-LSTM, trained by MLM then BB-Sim contrastive alignment) that supplies intrinsic novelty rewards without RTL simulation, and (ii) an Adaptive Coverage Reward Mechanism that reweights module-level coverage gains via a UCB-style bandit. Evaluations on Rocket, BOOM, and CVA6 under 24-hour wall-clock budgets report large gains over DifuzzRTL, ProcessorFuzz, and Cascade on control-register and related coverage, higher program prevalence and dependency-chain length, and improved Encarsia bug detection (30/60 vs Cascade 26), with ablations attributing substantial gains to the encoder and ACRM.

Significance. If the reported gains hold under stronger statistical controls, this is a meaningful step for hardware fuzzing: it shows that constructive generation can be productively factored into hierarchical RL actions while preserving program validity, and that dense semantic intrinsic feedback plus module-aware extrinsic reweighting can mitigate the sparsity and masking problems that limit both mutation-based and random constructive fuzzers. Strengths include multi-DUT evaluation (including a SystemVerilog core outside the Rocket ecosystem), component ablations isolating the BB Encoder and ACRM, explicit program-quality metrics (prevalence, dependency length, ISA coverage), and an Encarsia bug campaign with per-bug tables. The hierarchical generator and frozen DUT-agnostic encoder are reusable design ideas beyond the specific cores studied.

major comments (3)
  1. The central claim of substantial superiority under identical 24-hour budgets (Table II: Rocket Control Register Coverage 1,102,343 vs Cascade 740,329, +48.9%, 3.3× coverage/test; Fig. 7–11; Encarsia Table IV) rests on single full campaigns per fuzzer/DUT. §VI states that curves are not averaged over random seeds and flags multi-seed mean/std as future work. Rainbow DQN, PPO with dual critics, online cluster centers for R_int (Eq. 1), and UCB module weights (Eqs. 5–7) are all stochastic; Cascade is constructive-random. Without seed replicates or error bars, the magnitude of the headline gap cannot be distinguished from a favorable exploration trajectory. At minimum, report multi-seed means and variance for the primary Rocket control-register metric and the Fig. 11 ablations, or substantially qualify the strength of the “significantly outperforms” claim.
  2. §III-D and Fig. 12 present the BB Encoder as micro-architecture-aware because embeddings track the hand-designed BB-Sim metric (Algorithm 1). Fig. 12 only shows that cosine similarity correlates with BB-Sim (Pearson r=0.876), not that BB-Sim (or embedding novelty) correlates with measured microarchitectural stress (e.g., issue-queue pressure, ROB occupancy, unit utilization). The “hardware stress patterns” claim is therefore stronger than the evidence. Either validate BB-Sim/novelty against DUT-side microarch counters on a held-out set, or reframe the encoder as a structural/ISA-semantic novelty prior whose utility is established empirically by the ablation (+34% in Fig. 11) rather than by microarchitectural grounding.
  3. §V-A and Table I treat Control Register Coverage as the primary efficiency metric on Rocket, while CVA6 uses summed Line+Toggle (Fig. 8) because Control Register instrumentation is unavailable. The paper correctly notes that Line/Toggle can saturate and that MUX/Control Register are closer to verification intent, yet the cross-DUT “generality” claim mixes non-comparable metrics. Please either instrument a common processor-relevant metric on all three DUTs where possible, or more carefully separate “same-metric Rocket/BOOM comparison” from “transfer evidence on CVA6 under a coarser metric,” so the 7.2% CVA6 gain is not read as commensurate with the Rocket control-register result.
minor comments (5)
  1. §V-B5 and related text avoid a direct GenHuzz coverage comparison for good backend/model-release reasons; still, a short table of structural differences (action interface, validity mechanism, reward source) would make the contrast easier to cite without implying a coverage ranking.
  2. Appendix A lists many free parameters (α_int/α_ext, γ, τ, β schedule, BB-Sim scoring constants). A brief sensitivity note—or a statement that defaults were fixed before the final 24-hour campaigns—would help readers assess robustness.
  3. Fig. 9’s dual coverage/weight panels are informative but dense; labeling which modules are “easy” vs “hard” in the caption would help readers connect ACRM weight drops to the masking-effect narrative in §III-E.
  4. Typographical inconsistencies appear in core names (CV A6 / CVA6) and occasional spacing in math (e.g., R int vs R_int). Normalize throughout.
  5. §VI correctly scopes out multi-hart/A-extension concurrency bugs; a one-sentence forward pointer in the introduction would set expectations earlier for readers focused on memory-ordering verification.

Circularity Check

0 steps flagged · score 0.0 of 10

No circularity: empirical RL optimization paper whose coverage/bug claims rest on external DUT simulation, not on self-definitional or fitted-as-prediction reductions.

full rationale

HiFuzz is an engineering/empirical systems paper, not a first-principles derivation. Its load-bearing claims (Table II Control-Register Coverage 1,102,343 vs Cascade 740,329; Encarsia 30/60 bugs; ablations in Fig. 11; CVA6 Total Coverage) are measured by running generated programs on independent RTL simulators (Verilator) and Spike reference models under fixed 24 h wall-clock budgets. The dual-agent hierarchy, Semantic-Aware BB Encoder (two-stage MLM + contrastive alignment to hand-designed BB-Sim), and UCB-based ACRM are design choices that produce denser intrinsic/extrinsic rewards; they do not redefine the evaluation metrics. The encoder is trained offline once on Cascade programs and frozen, so novelty R_int is not fitted to the same coverage numbers later reported as results. No uniqueness theorems, self-citation chains, or ansatz-smuggling appear; citations to Rainbow DQN, PPO, RND, Cascade, etc. are standard external tools. Single-run variance is a statistical-support issue (noted by the authors in §VI), not circularity. The derivation chain therefore does not reduce any claimed result to its own inputs by construction.

Assumptions & free parameters 6 free parameters · 5 assumptions · 3 invented entities

Load-bearing content is mostly engineering choices and domain assumptions of coverage-guided CPU fuzzing, plus many hand-set RL and similarity hyperparameters. No physical entities are postulated; the new machinery is algorithmic. The central empirical claim rests on these design choices plus the assumption that single-run coverage/bug campaigns generalize.

free parameters (6)
  • α_int, α_ext (intrinsic/extrinsic actor weights)
    Set to 1 and 2; directly scale dual-advantage learning and therefore policy behavior.
  • extrinsic baseline diminishing factor γ
    Set to 0.75; controls how coverage improvement is normalized into R_ext.
  • Program/BB agent learning rates
    1e-4 (Rainbow DQN) and 1e-3 (PPO); chosen by authors, not derived.
  • UCB temperature τ and dynamic β schedule
    Control module weight sharpness and exploration shift in ACRM; hand-tuned.
  • BB-Sim match/dependency scoring constants (B_exact, α discount, β_bonus, window W)
    Define the supervised similarity target for the encoder; not learned from hardware ground truth.
  • Encoder embedding/hidden sizes and training corpus size
    Bi-LSTM dim 96, 20k Cascade programs, dual masking rates; architectural free choices affecting novelty rewards.
assumptions (5)
  • domain assumption Control-register, MUX, line, and toggle coverage are useful proxies for verification progress and correlate with bug-finding power.
    Used throughout §V as primary success metrics; paper notes they are complementary but still optimizes and ranks methods by them.
  • ad hoc to paper Program generation can be productively factored into global structural actions and per-BB category distributions without needing instruction-level RL actions.
    Core design of §III-C; validity is delegated to a Cascade-style constrained generator.
  • ad hoc to paper BB-Sim structural similarity reflects microarchitectural stress similarity well enough that embedding novelty is a useful intrinsic reward.
    Stage-2 training objective in §III-D; supported by Pearson r=0.876 to BB-Sim, not by direct hardware labels.
  • domain assumption Module-level coverage instrumentation is available and modules can be treated as independent bandit arms.
    Required by ACRM (§III-E); limitations state ACRM degrades to global reward without it.
  • domain assumption Rainbow DQN and PPO with dual critics are appropriate learners for the discrete macro and continuous micro action spaces.
    Algorithm choices in §III-C and §IV; standard RL practice, not proved optimal here.
invented entities (3)
  • Semantic-Aware Basic Block Encoder (Bi-LSTM + BB-Sim curriculum)
    purpose: Provide dense, simulation-free intrinsic novelty rewards for the Basic Block Agent.
    New component trained offline; independent handle is only correlation with BB-Sim and ablation gains, not external hardware labels.
  • Adaptive Coverage Reward Mechanism (UCB module reweighting)
    purpose: Counter masking of hard modules by easy coverage gains.
    Paper-specific reward shaping; evidence is module-weight plots and ablation, not an external theory result.
  • Dual-agent hierarchical constructive fuzzer (Program Agent + Basic Block Agent)
    purpose: Make constructive program generation a tractable RL control problem while preserving validity.
    Central architecture; evaluated only inside this paper’s campaigns.

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Cite this review

Pith. "Pith review of HiFuzz: Hierarchical Reinforcement Learning for Semantic-Aware and Adaptive CPU Fuzzing." pith.science (2026). https://pith.science/paper/FYJQYRQO

@misc{pith2026260706619,
  author       = {Pith},
  title        = {Pith review of: HiFuzz: Hierarchical Reinforcement Learning for Semantic-Aware and Adaptive CPU Fuzzing},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/FYJQYRQO}},
  note         = {Machine review of arXiv:2607.06619}
}
read the original abstract

Modern processor verification struggles to reach deep architectural states due to the inefficiencies of traditional mutation-based fuzzing. We propose HiFuzz, a novel hierarchical reinforcement learning framework that replaces mutation with a structured, two-layer generation process: a Program Agent for global layout and a Basic Block Agent for precise instruction filling. To overcome reward sparsity, HiFuzz integrates an adaptive coverage reward mechanism and a semantic-aware basic block encoder providing intrinsic feedback. Extensive evaluations on three real-world RISC-V cores demonstrate that HiFuzz significantly outperforms state-of-the-art fuzzers in coverage and bug detection.

Figures

Figures reproduced from arXiv: 2607.06619 by the authors.

Figure 1
Figure 1. The paradigm shift in hardware fuzzing: mutation [PITH_FULL_IMAGE:figures/full_fig_p001_1.png] view at source ↗
Figure 2
Figure 2. HiFuzz framework overview. The dual-agent architecture collaboratively generates test programs: (1) Program Agent [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 3
Figure 3. Hierarchical Configuration mechanism Agent determines the global structure of the test program, while the low-level Basic Block Agent decides the instructions inside each BB. This decomposition is motivated by the fact that program-level decisions (memory layout, BB count, control flow) operate on a fundamentally different timescale and abstraction level from instruction-level decisions (operand selection, dependenc… view at source ↗
Figures from the paper (8 more)
Figure 4
Figure 4. Figure 4: HRL Agent Interaction (Temporal Workflow). The [PITH_FULL_IMAGE:figures/full_fig_p004_4.png]
Figure 6
Figure 6. Figure 6: Two-stage training pipeline for the BB Encoder. [PITH_FULL_IMAGE:figures/full_fig_p005_6.png]
Figure 7
Figure 7. Figure 7: 24-hour Control Register Coverage growth on Rocket [PITH_FULL_IMAGE:figures/full_fig_p007_7.png]
Figure 10
Figure 10. Figure 10: MUX coverage on Rocket and BOOM. HiFuzz’s [PITH_FULL_IMAGE:figures/full_fig_p008_10.png]
Figure 9
Figure 9. Figure 9: Per-module Control-Register Coverage growth (top) [PITH_FULL_IMAGE:figures/full_fig_p008_9.png]
Figure 13
Figure 13. Figure 13: BB Encoder two-stage training loss. Stage 1: [PITH_FULL_IMAGE:figures/full_fig_p009_13.png]
Figure 12
Figure 12. Figure 12: Correlation between embedding cosine similarity and [PITH_FULL_IMAGE:figures/full_fig_p009_12.png]
Figure 14
Figure 14. Figure 14: Generated program quality across fuzzers: (a) preva [PITH_FULL_IMAGE:figures/full_fig_p012_14.png]

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Reference graph

Works this paper leans on

24 extracted references · 24 canonical work pages

  1. [1]

    Meltdown: Reading kernel memory from user space,

    M. Lipp, M. Schwarz, D. Gruss, T. Prescher, W. Haas, A. Fogh, J. Horn, S. Mangard, P. Kocher, D. Genkin, Y . Yarom, and M. Hamburg, “Meltdown: Reading kernel memory from user space,” in27th USENIX Security Symposium (USENIX Security 18), 2018, pp. 973–990

    work page 2018

  2. [2]

    Spectre attacks: Exploiting speculative execution,

    P. Kocher, J. Horn, A. Fogh, D. Genkin, D. Gruss, W. Haas, M. Hamburg, M. Lipp, S. Mangard, T. Prescher, and Y . Yarom, “Spectre attacks: Exploiting speculative execution,” in2019 IEEE Symposium on Security and Privacy (S&P), 2019, pp. 1–19

    work page 2019

  3. [3]

    Bergeron,Writing Testbenches: Functional Verification of HDL Models, 2nd ed

    J. Bergeron,Writing Testbenches: Functional Verification of HDL Models, 2nd ed. Springer, 2003

    work page 2003

  4. [4]

    E. M. Clarke, T. A. Henzinger, H. Veith, and R. Bloem, Eds.,Handbook of Model Checking. Springer, 2018

    work page 2018

  5. [5]

    Rfuzz: Coverage-directed fuzz testing of RTL on FP- GAs,

    K. Laeufer, J. Koenig, D. Kim, J. Bachrach, and K. Sen, “Rfuzz: Coverage-directed fuzz testing of RTL on FP- GAs,” in2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD). IEEE, 2018, pp. 1–8

    work page 2018

  6. [6]

    Difuzzrtl: Differential fuzz testing to find cpu bugs,

    J. Hur, S. Song, D. Kwon, E. Baek, J. Kim, and B. Lee, “Difuzzrtl: Differential fuzz testing to find cpu bugs,” in 2021 IEEE Symposium on Security and Privacy (SP). IEEE, 2021, pp. 1286–1303

    work page 2021

  7. [7]

    Cascade: CPU fuzzing via intricate program generation,

    F. Solt, K. Ceesay-Seitz, and K. Razavi, “Cascade: CPU fuzzing via intricate program generation,” in33rd USENIX Security Symposium (USENIX Security 24), 2024, pp. 5341–5358

    work page 2024

  8. [8]

    Processorfuzz: Processor fuzzing with control and status registers guidance,

    S. Canakci, C. Rajapaksha, L. Delshadtehrani, A. Nataraja, M. B. Taylor, M. Egele, and A. Joshi, “Processorfuzz: Processor fuzzing with control and status registers guidance,” in2023 IEEE International Symposium on Hardware Oriented Security and Trust (HOST). IEEE, 2023, pp. 1–12

    work page 2023

Show all 24 references
  1. [9]

    Beyond random inputs: A novel ml-based hardware fuzzing,

    M. Rostami, M. Chilese, S. Zeitouni, R. Kande, J. Ra- jendran, and A. R. Sadeghi, “Beyond random inputs: A novel ml-based hardware fuzzing,” in2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2024, pp. 1–6

    2024

  2. [10]

    {GenHuzz}: An efficient generative hardware fuzzer,

    L. Wu, M. Rostami, H. Li, J. Rajendran, and A.-R. Sadeghi, “{GenHuzz}: An efficient generative hardware fuzzer,” in34th USENIX Security Symposium (USENIX Security 25), 2025, pp. 1787–1805

    2025

  3. [11]

    Chisel: Constructing hardware in a scala embedded language,

    J. Bachrach, H. V o, B. Richards, Y . Lee, A. Waterman, R. Avizienis, J. Wawrzynek, and K. Asanovi ´c, “Chisel: Constructing hardware in a scala embedded language,” inDAC Design Automation Conference. IEEE, 2012, pp. 1212–1221

    2012

  4. [12]

    The Rocket chip generator,

    K. Asanovi ´cet al., “The Rocket chip generator,”Techni- cal Report UCB/EECS-2016-17, EECS Department, UC Berkeley, 2016

    2016

  5. [13]

    BOOM: An open-source out-of-order risc-v core,

    C. Celio, D. A. Patterson, and K. Asanovi ´c, “BOOM: An open-source out-of-order risc-v core,” inFirst Work- shop on Computer Architecture Research with RISC-V (CARRV), 2017

    2017

  6. [14]

    Simulator independent coverage for RTL hardware languages,

    K. Laeufer, V . Iyer, D. Biancolin, J. Bachrach, B. Nikoli´c, and K. Sen, “Simulator independent coverage for RTL hardware languages,” inProceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 3, 202...

    2023

  7. [15]

    Between MDPs and semi-MDPs: A framework for temporal abstraction in reinforcement learning,

    R. S. Sutton, D. Precup, and S. Singh, “Between MDPs and semi-MDPs: A framework for temporal abstraction in reinforcement learning,”Artificial Intelligence, vol. 112, no. 1–2, pp. 181–211, 1999

    1999

  8. [16]

    Rainbow: Combining improvements in deep reinforcement learning,

    M. Hessel, J. Modayil, H. Van Hasselt, T. Schaul, G. Os- trovski, W. Dabney, D. Horgan, B. Piot, M. Azar, and D. Silver, “Rainbow: Combining improvements in deep reinforcement learning,” inAAAI Conference on Artificial Intelligence, 2018

    2018

  9. [17]

    Proximal policy optimization algorithms,

    J. Schulman, F. Wolski, P. Dhariwal, A. Radford, and O. Klimov, “Proximal policy optimization algorithms,” arXiv preprint arXiv:1707.06347, 2017

    2017 arXiv

  10. [18]

    Ex- ploration by random network distillation,

    Y . Burda, H. Edwards, A. Storkey, and O. Klimov, “Ex- ploration by random network distillation,”International Conference on Learning Representations (ICLR), 2019

    2019

  11. [19]

    High-dimensional continuous control us- ing generalized advantage estimation,

    J. Schulman, P. Moritz, S. Levine, M. Jordan, and P. Abbeel, “High-dimensional continuous control us- ing generalized advantage estimation,”arXiv preprint arXiv:1506.02438, 2015

    2015 arXiv

  12. [20]

    BinSe- quence: Fast, accurate and scalable binary code reuse 10 detection,

    H. Huang, A. M. Youssef, and M. Debbabi, “BinSe- quence: Fast, accurate and scalable binary code reuse 10 detection,” inProceedings of the 2017 ACM on Asia Conference on Computer and Communications Security (ASIA CCS), 2017, pp. 155–166

    2017

  13. [21]

    Finite-time analysis of the multiarmed bandit problem,

    P. Auer, N. Cesa-Bianchi, and P. Fischer, “Finite-time analysis of the multiarmed bandit problem,”Machine Learning, vol. 47, no. 2–3, pp. 235–256, 2002

    2002

  14. [22]

    Verilator: The Fastest Verilog/SystemVerilog Simulator,

    CHIPS Alliance under The Linux Foundation, “Verilator: The Fastest Verilog/SystemVerilog Simulator,” https:// github.com/verilator/verilator, 2024, (2024)

    2024

  15. [23]

    The cost of application-class processing: Energy and performance analysis of a Linux- ready 1.7-GHz 64-bit RISC-V core in 22-nm FDSOI technology,

    F. Zaruba and L. Benini, “The cost of application-class processing: Energy and performance analysis of a Linux- ready 1.7-GHz 64-bit RISC-V core in 22-nm FDSOI technology,” inIEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 27, no. 11. IEEE, 2019, pp. 2629–2640

    2019

  16. [24]

    Encarsia: Evaluating cpu fuzzers via automatic bug injection,

    M. B ¨olcskei, F. Solt, K. Ceesay-Seitz, and K. Razavi, “Encarsia: Evaluating cpu fuzzers via automatic bug injection,” in34th USENIX Security Symposium, 2025. APPENDIXA IMPLEMENTATIONCONFIGURATIONDETAILS This appendix complements Section IV with the full state/action schemas,...

    2025

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