Hardware-aware Graph Neural Networks prunning for embedded event-based vision

Kamil Jeziorek; Piotr Wzorek; Tomasz Kryjak

REVIEW 2 major objections 5 minor 19 references

Hardware-aware Graph Neural Networks prunning for embedded event-based vision

T0 review · 2 major / 5 minor · reviewed 2026-07-10 · grok-4.5

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Pith's one-line read Hardware-aware pruning and quantization of event-based graph convolutional nets cut on-chip BRAM by 26–31% with only small accuracy loss on embedded FPGAs.

desk verdict Solid, usable hardware-aware compression for EFGCN feature memories; first of its kind for event GCNNs, backed by real ZCU104 numbers. read the letter →

arxiv 2607.06739 v1 pith:5BYC6EXO submitted 2026-07-07 cs.CV

Piotr Wzorek , Kamil Jeziorek , Tomasz Kryjak This is my paper · ORCID

classification cs.CV

keywords event-basedvisiongraphconvolutionalnetworkshardware-awarepruningquantizationFPGABRAMembeddedroboticsEFGCN

verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

Event cameras produce sparse, high-speed data that is attractive for mobile robots, yet real-time processing on power-limited platforms is still hard. This paper shows that Graph Convolutional Networks can be deliberately pruned and quantized so that their feature-memory widths line up exactly with the physical sizes of FPGA BlockRAM and UltraRAM blocks. Two search procedures—Fine Grid Search followed by Greedy Layer-wise Iterative Deepening—walk the resulting discrete design space and return configurations that trade a few accuracy points for roughly thirty percent less on-chip memory. The method is demonstrated on three standard neuromorphic classification sets and is backed by a concrete ZCU104 implementation. A sympathetic reader cares because the same memory bottleneck appears whenever larger event-based models must stay on-chip for latency or energy reasons; the paper supplies both the alignment rule and a practical way to search it.

What carries the argument

The pair of closed-form channel families C(BRAM)_m = m·18/gcd(q,18) and C(URAM)_n that guarantee full utilisation of every memory half-block, together with the two-stage FG+GLID search that walks those families while tracking the accuracy–BRAM Pareto front.

What would settle it

An unstructured or activation-aware pruning method that produces a model with lower BRAM count and higher accuracy than the FG+GLID result on the same three datasets and the same ZCU104 fabric would falsify the claim that the hardware-aligned families plus the described search are near-optimal.

Watch

Extended reading notes

Core claim

By forcing the number of channels and the bit-width of each feature map to belong to the discrete families that fully pack BRAM-18 kb halves or URAM-72 kb blocks, and by searching those families with Fine Grid Search plus Greedy Layer-wise Iterative Deepening, the EFGCN architecture can be reduced by 26.5–31.4 % in BRAM while losing only 1.65–5.18 % accuracy on CIFAR10-DVS, MNIST-DVS and N-Caltech101.

Load-bearing premise

The claim rests on the premise that the only configurations worth considering are those that completely fill BRAM or URAM blocks and that a short two-stage heuristic search is enough to find the best accuracy–memory trade-off among them.

Editorial extensions

If this is right

Larger event-based GCNNs can now fit entirely inside on-chip memory of smaller SoC FPGAs, removing the need for external DRAM and its latency and energy cost.
Designers can dial the accuracy–BRAM operating point after the first search stage simply by choosing a different knee on the Pareto front, matching a given platform’s memory budget without retraining from scratch.
The same channel-alignment equations apply to any PointNet-style graph convolution whose feature maps are stored in dual-port FPGA memories, not only to the five-layer EFGCN.
Logic-resource savings accompany the memory reduction because smaller feature vectors shrink the LUT-based multipliers and allow some 6-bit arithmetic.
A working ZCU104 module already demonstrates a 30.6 % overall BRAM cut and a 3.55 % accuracy drop for MNIST-DVS classification.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

The same packing rule could be applied to the asynchronous early layers if their feature memories were also forced onto BRAM/URAM, potentially extending the savings beyond the synchronous part of the pipeline.
Because the search returns an explicit Pareto front, the method can be re-run at design time whenever a new FPGA family changes the BRAM or URAM geometry, giving an automatic portability path.
If edge or temporal importance scores were added to the pruning criterion, the same hardware families might yield still better accuracy for a given BRAM budget, a natural next experiment.

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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Desk Editor's Note

read the letter

This is a practical engineering paper that does what it claims. The new piece is the memory-block-aware channel families (Eqs. 4–5) specialised to EFGCN’s dual-port feature memories, plus the two-stage FG + GLID search that stays inside those families. They get 26–31 % BRAM reduction on three public event datasets with accuracy drops of 1.65–5.18 %, and they close the loop with a synthesised ZCU104 module that actually shows 30.6 % overall BRAM saving. That combination—structured pruning that respects BRAM/URAM widths, applied to PointNetConv temporal-channel memories, with a working FPGA proof—is not in the prior literature they cite.

What they do well is keep the claims empirical and measurable. Tables of channel counts, Pareto plots, fine-tuning results, and the resource table for the full system are all there. The method is deliberately constrained so that every candidate configuration maps cleanly onto on-chip memory; that is the point for mobile robotics that cannot afford external DRAM. The citation pattern is clean: they correctly position themselves against the three existing FPGA event classifiers and against generic structured-pruning work for CNNs.

Soft spots are real but proportionate. The search is a heuristic (k=2 FG steps then GLID stopped at a 5–10 % accuracy delta); they never claim global optimality, only that the method produces the reported operating points. No error bars, no head-to-head against magnitude-based or activation-aware pruners, and no public code. DSP count goes up because some 6-bit multiplies land on DSP slices. None of these reverse the measured BRAM–accuracy numbers or the hardware result. The reliance on their own prior EFGCN architecture is expected and not circular—the pruning measurements stand alone.

This is for people who actually put event GCNNs on SoC FPGAs. If that is your problem, the paper is useful. It deserves a serious referee; the central claim is supported by multi-dataset data and a real synthesis. I would engage with it and would cite the concrete operating points when I next need a memory-aware baseline for event-vision GCNNs.

Referee Report

2 major / 5 minor

Summary. The paper proposes a hardware-aware pruning and quantization strategy for Graph Convolutional Neural Networks (specifically the EFGCN architecture) targeting event-based vision on embedded SoC FPGAs. The method constrains channel counts and bit-widths so that feature memories fully utilize BRAM-18 kb halves or URAM-72 kb blocks (Eqs. 1–5), then explores the resulting discrete design space with Fine Grid Search followed by Greedy Layer-wise Iterative Deepening Search. Evaluated on MNIST-DVS, CIFAR10-DVS and N-Caltech101, the approach reports BRAM reductions of 28.8–31.4 % relative to the floating-point baseline at accuracy drops of 1.65–5.18 % after fine-tuning; a ZCU104 synthesis of the MNIST-DVS model confirms a 30.6 % overall BRAM reduction together with LUT/FF savings.

Significance. If the reported trade-offs hold, the work supplies a practical, platform-aware compression recipe for the still-small literature on FPGA-accelerated event-based GCNNs. Strengths include explicit channel tables, Pareto plots, fine-tuning results, and a synthesised proof-of-concept module that validates the memory numbers on real hardware. The contribution is primarily engineering rather than algorithmic novelty, yet it directly addresses the on-chip memory bottleneck that limits larger models on mobile platforms and therefore has clear utility for the embedded-event-vision community.

major comments (2)

Section IV and Figure 3 report only single-run accuracy and BRAM figures; no error bars, multiple random seeds or statistical tests are provided. Given that the accuracy drops (especially the 5.18 % on N-Caltech101) are modest, the absence of variance estimates makes it difficult to judge whether the observed trade-offs are robust or sensitive to training stochasticity.
Related-work discussion (Section II-B) and the experimental protocol omit any quantitative comparison against magnitude-based unstructured pruning, activation-aware criteria, or other structured pruners that ignore the BRAM/URAM families of Eqs. 4–5. Without such baselines it remains unclear how much of the reported memory–accuracy trade-off is attributable to the hardware-aware constraints versus ordinary channel pruning.

minor comments (5)

Title and several headings contain the typo “prunning”; correct to “pruning” throughout.
Abstract and Section IV inconsistently refer to “CIFAR-10” versus “CIFAR10-DVS”; standardise on the neuromorphic dataset name.
Equation (6) and the surrounding text state that k=2 yields 1024 configurations, yet later claim equivalence to a k=5 FG search; a short clarification of the combinatorial accounting would help.
Table III shows an increase in DSP usage; a one-sentence explanation of the automatic mapping of 6-bit multiplies would improve readability.
Index terms contain “Nerual” and “Prunning”; fix spelling.

Circularity Check

1 steps flagged · score 1.0 of 10

Empirical hardware-aware pruning results measured on held-out data and FPGA synthesis; only mild self-citation of the authors' prior EFGCN architecture as the starting model.

self citation load bearing [Section II-A / III-A / IV-A (baseline model)]
"In this work, we have chosen to utilise the third system — EFGCN. In [7], the authors propose an architecture divided into two parts... For our study, we utilised the large model from [7], which consists of five convolutional layers and two pooling layers."

The unpruned starting architecture, memory layout (temporal channel matrices, feature memories), and initial channel counts are taken directly from the authors' own prior work [7]. This is ordinary self-citation of a baseline system rather than a uniqueness claim or definitional loop; the pruning results themselves remain independent empirical measurements. Mild only.

full rationale

The paper's central claims are measured engineering outcomes: channel counts constrained to the BRAM/URAM full-utilization families (Eqs. 1-5), two-stage FG+GLID search over a discrete design space, fine-tuning, and ZCU104 synthesis produce the reported BRAM reductions (26.5-31.4%) and accuracy drops (1.65-5.18%) relative to floating-point and 8-bit baselines. These numbers are obtained by training, evaluating on standard event datasets, and synthesizing hardware modules; they are not algebraic identities or tautological restatements of the inputs. The sole mild circularity is the use of the authors' own prior EFGCN architecture [7] as the unpruned starting point (Section II-A, III-A, IV-A). That citation supplies the baseline model and memory layout, but the pruning/quantization method, search procedures, accuracy-resource trade-offs, and hardware proof-of-concept are independent measurements performed in the present work. No uniqueness theorem, fitted parameter renamed as prediction, or self-definitional step appears. Score 1 reflects ordinary self-citation of prior architecture without load-bearing circularity in the claimed results.

Assumptions & free parameters 4 free parameters · 3 assumptions · 1 invented entities

The central claim rests on the EFGCN architecture, standard FPGA memory geometry, and a handful of search and training hyper-parameters chosen by the authors; no new physical entities are postulated.

free parameters (4)

FG downward steps k = 2
Set to k=2 for all datasets, controlling the size of the initial discrete search space (Eq. 6).
GLID accuracy-delta stopping criterion = 5%/10%
5% for CIFAR10-DVS/N-Caltech101, 10% for MNIST-DVS; directly determines how far the second-stage search proceeds.
quantisation bit-widths = 6 or 8
Restricted a priori to the two levels {6,8}; all reported configurations use only these values.
fine-tuning learning rate and epochs = 1e-5 / 10 epochs
10 epochs at 1e-5 after compression; chosen to recover accuracy without further architecture search.

assumptions (3)

domain assumption Feature-memory width is the dominant BRAM/URAM consumer and must be an integer multiple of the physical block widths (18 kb halves or 72 kb URAM) for full utilisation.
Stated in Section III-B and used to derive the admissible channel families (Eqs. 4–5).
domain assumption The EFGCN architecture (asynchronous PointNetConv layers + 3-D MaxPool + synchronous part) is a suitable base model for event classification on SoC FPGAs.
Taken from the authors’ prior work [7] and used throughout; all pruning starts from its channel counts.
ad hoc to paper One URAM block is cost-equivalent to two BRAM blocks for the utilisation metric.
Normalisation choice introduced in Section III-C to produce a single scalar cost.

invented entities (1)

Fine Grid Search (FG) + Greedy Layer-wise Iterative Deepening (GLID) procedure
purpose: Tractable two-stage exploration of the combinatorial channel/quantisation space that would otherwise exceed 10^6 configurations.
Defined in Section III-C; no independent theoretical optimality guarantee is claimed or proven.

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Cite this review

Pith. "Pith review of Hardware-aware Graph Neural Networks prunning for embedded event-based vision." pith.science (2026). https://pith.science/paper/5BYC6EXO

@misc{pith2026260706739,
  author       = {Pith},
  title        = {Pith review of: Hardware-aware Graph Neural Networks prunning for embedded event-based vision},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/5BYC6EXO}},
  note         = {Machine review of arXiv:2607.06739}
}

read the original abstract

Event-based cameras are gaining popularity as the sensor of choice for mobile robotics, due to their high performance in dynamic environments. However, these applications require efficient real-time data processing with low latency and power consumption. One strategy to meet these stringent requirements is hardware acceleration of efficient algorithms that preserve the temporal sparsity of event data. In this work, we propose an optimization strategy for Graph Convolutional Neural Networks models aimed at adapting their architecture to the limited resources of embedded heterogeneous FPGA platforms. Our method incorporates hardware-aware pruning and quantization, taking into account the trade-off between on-chip memory savings and inference accuracy. Strategic exploration of the design space with Fine Grid Search and Greedy layer-wise Iterative Deepening Search methods enables flexible adaptation of the model architecture to the target platform. Our approach was evaluated across various network configurations and multiple datasets, resulting in BRAM memory reductions of 28.8% for CIFAR-10 (with a 1.65% decrease in accuracy), 31.4% for MNIST-DVS (accuracy drop of 3.55%), and 26.5% for N-Caltech101 (with a 5.18% accuracy reduction).

Figures

Figures reproduced from arXiv: 2607.06739 by the authors.

**Figure 2.** Comparison of BRAM utilisation and classification performance for the MNIST-DVS, CIFAR10-DVS, and N-Caltech101 [PITH_FULL_IMAGE:figures/full_fig_p005_2.png] view at source ↗

**Figure 3.** Prediction accuracy and BRAM usage for hardware [PITH_FULL_IMAGE:figures/full_fig_p005_3.png] view at source ↗

Discussion (0). Continue with ORCID to comment.

Reference graph

Works this paper leans on

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Pith tools

Reviewed July 10, 2026 · model on record in the stance chip above.

[1] [1]

Event- based vision: A survey,

G. Gallego, T. Delbr ¨uck, G. Orchard, C. Bartolozzi, B. Taba, A. Censi, S. Leutenegger, A. J. Davison, J. Conradt, K. Daniilidiset al., “Event- based vision: A survey,”IEEE transactions on pattern analysis and machine intelligence, vol. 44, no. 1, pp. 154–180, 2020

work page 2020

[2] [2]

Learning to detect objects with a 1 megapixel event camera,

E. Perot, P. De Tournemire, D. Nitti, J. Masci, and A. Sironi, “Learning to detect objects with a 1 megapixel event camera,”Advances in Neural Information Processing Systems, vol. 33, pp. 16 639–16 652, 2020

work page 2020

[3] [3]

Recurrent vision transformers for object detection with event cameras,

M. Gehrig and D. Scaramuzza, “Recurrent vision transformers for object detection with event cameras,” inProceedings of the IEEE/CVF confer- ence on computer vision and pattern recognition, 2023, pp. 13 884– 13 893

work page 2023

[4] [4]

Event- based angular velocity regression with spiking networks,

M. Gehrig, S. B. Shrestha, D. Mouritzen, and D. Scaramuzza, “Event- based angular velocity regression with spiking networks,” in2020 IEEE International Conference on Robotics and Automation (ICRA). IEEE, 2020, pp. 4195–4202

work page 2020

[5] [5]

Aegnn: Asynchronous event-based graph neural networks,

S. Schaefer, D. Gehrig, and D. Scaramuzza, “Aegnn: Asynchronous event-based graph neural networks,” inProceedings of the IEEE/CVF conference on computer vision and pattern recognition, 2022, pp. 12 371–12 381

work page 2022

[6] [6]

Low-latency automotive vision with event cameras,

D. Gehrig and D. Scaramuzza, “Low-latency automotive vision with event cameras,”Nature, vol. 629, no. 8014, pp. 1034–1040, 2024

work page 2024

[7] [7]

Embedded Graph Convolutional Networks for Real-Time Event Data Processing on SoC FPGAs

K. Jeziorek, P. Wzorek, K. Blachut, A. Pinna, and T. Kryjak, “Embedded graph convolutional networks for real-time event data processing on soc fpgas,”arXiv preprint arXiv:2406.07318, 2024

work page Pith review arXiv 2024

[8] [8]

Recent event camera innovations: A survey,

B. Chakravarthi, A. A. Verma, K. Daniilidis, C. Fermuller, and Y . Yang, “Recent event camera innovations: A survey,” inEuropean Conference on Computer Vision. Springer, 2025, pp. 342–376

work page 2025