AtomFlow: An End-to-End FPGA-Based Control Architecture for Neutral Atom Quantum Computers

Jonas Winklmann; Martin Schulz; Vengkeat Chea; Xiaorang Guo

REVIEW 4 major objections 6 minor 40 references

AtomFlow: An End-to-End FPGA-Based Control Architecture for Neutral Atom Quantum Computers

T0 review · 4 major / 6 minor · reviewed 2026-07-14 · grok-4.5

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Pith's one-line read AtomFlow co-locates fluorescence imaging and atom rearrangement on one FPGA and streams moves as they are computed, cutting end-to-end initialization latency to 25.3 ms on a 16×16 array.

desk verdict Solid FPGA systems integration for NAQC init/readout with real silicon latency numbers; streaming hide-behind-execution only holds under the slow AOD model they also plot. read the letter →

arxiv 2607.11490 v1 pith:6BW426BV submitted 2026-07-13 quant-ph cs.AR

Xiaorang Guo , Jonas Winklmann , Vengkeat Chea , Martin Schulz This is my paper

classification quant-phcs.AR

keywords NeutralAtomQuantumComputingFPGADetectionRearrangementControlLatencyStreamingPipeline

verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

Neutral-atom quantum computers lose a large fraction of their cycle time to classical steps: reading noisy fluorescence images to locate atoms, then planning how to rearrange those atoms into a defect-free grid. AtomFlow argues that both stages can live on a single FPGA, with each rearrangement move emitted to the waveform generators the instant it is ready, so the usual host round-trip disappears. On a 16×16 array the full pipeline finishes in 25.3 ms, the first move is available after 4 ms, and subsequent moves average about 1 ms. Resource analysis shows the same board still has headroom for larger arrays. If the claim holds, initialization and mid-circuit readout no longer wait on a software host—an essential requirement once many rounds must finish inside limited coherence time.

What carries the argument

The Atom Rearrangement Engine: an HLS-mapped HiPARS-style by-row lattice sorter that classifies sites, clears a sorting corridor, and streams parallel 2-/3-/4-step moves as soon as each is ready, overlapping generation with physical AOD execution.

What would settle it

Execute the identical 16×16 rearrangement on hardware whose measured transfer and transport times match the paper’s fast model (120 µs transfer, 0.55 µm/µs); if the waveform generator still stalls waiting for moves, the hiding claim fails for that regime.

Watch

Extended reading notes

Core claim

Integrating fluorescence-image analysis with a streaming by-row atom-rearrangement engine on one Zynq UltraScale+ FPGA, and emitting each move over AXI-Stream as soon as it is finalized, yields 25.3 ms end-to-end latency (4 ms first-move, ~1 ms average per move) for a 16×16 array while remaining inside a single-board resource budget for larger grids.

Load-bearing premise

The claim that generation latency can be hidden rests on physical AOD/SLM move times remaining long enough that the FPGA finishes the next move before the previous one finishes executing.

Editorial extensions

If this is right

Host–FPGA round-trips are removed from every defect-free array preparation cycle.
Mid-circuit measurement feedback can stay on the FPGA control plane instead of crossing to a host.
For slower physical-move models, all but the first-move latency is hidden behind AOD execution.
The same board can host both detection and rearrangement for arrays larger than 16×16 without exhausting resources.
Switching between initialization and readout costs only register configuration, not a redesign.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

As AOD transfer times and transport speeds improve, the ~1 ms generation time will become the new bottleneck unless the engine is further accelerated or more tightly coupled to the waveform generator.
The existing streaming interface can be extended to feed an on-FPGA control processor, enabling closed-loop feedback without host involvement.
Resource headroom on the same device suggests co-locating lightweight classical tasks such as simple syndrome decoding is feasible.

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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Desk Editor's Note

read the letter

This paper co-locates their prior FPGA atom-detection IP with a new HLS port of the HiPARS by-row sorter on one Zynq UltraScale+ and streams ParallelMove packets over AXI-Stream as soon as each is ready. On a 16×16 case they measure 25.3 ms end-to-end, 4 ms to first move, ~1.01 ms average generation. That is the actual advance: host round-trips disappear and generation can overlap physical AOD/SLM execution.

What they do well is concrete. Latency breakdowns come from real ZCU216 runs with stds; resources are post-implementation; correctness is checked by replaying the generated moves on ground-truth occupancy and matching the target geometry; BRAM scales roughly linearly while LUT/FF/DSP stay flat out to 256. They ship the code and are explicit that full camera-to-AWG closed loop is still future work (PS still sits in the current path).

The soft spot is exactly the one the stress-test flags, and it is already visible in their own Fig. 8 and Eqs. 1–3. Under the slow literature parameters (800 µs transfer, 0.054 µm/µs) the queue stays full and only first-move latency matters. Under the fast parameters (120 µs, 0.55 µm/µs) generation stalls appear, so the architectural claim that streaming eradicates rearrangement overhead is model-dependent and already broken for the speeds the field is targeting. They do not hide this; they just do not emphasize it. Verification still uses simulated images rather than live camera data, which is minor but real. Free parameters (binarization threshold, AOD channel width) are ordinary for the domain.

This is for people building NAQC control stacks or FPGA quantum backends. The measurements are honest, the architecture is clear, and the citation pattern is normal self-use of prior modules that are re-validated. It deserves a serious referee. If you work on the control path, read it and cite the numbers; otherwise the abstract plus Fig. 8 is enough.

Referee Report

4 major / 6 minor

Summary. AtomFlow presents an FPGA-centric control pipeline for neutral-atom quantum computers that co-locates fluorescence-image analysis and atom rearrangement on a single Zynq UltraScale+ RFSoC, streaming rearrangement moves over AXI-Stream as they are produced. The rearrangement engine is an HLS adaptation of the authors’ HiPARS row-by-row lattice sorter, integrated with a previously published detection IP and a control-interface module that switches between initialization and readout modes. On a 16×16 array requiring 22 moves, the authors report 25.3 ms end-to-end latency, 4 ms first-move latency, and ~1.01 ms average generation per subsequent move, with post-implementation resource usage well below device capacity and HLS-based scaling trends up to 256×256. Functional correctness is checked by applying generated moves to a ground-truth occupancy array and matching a prescribed target geometry. The paper argues that co-location plus streaming removes host-mediated round-trips that otherwise dominate NAQC initialization and mid-circuit feedback paths.

Significance. If the measured latencies and the streaming interface hold under realistic lab integration, this is a useful systems contribution for NAQC control: it closes the detection–rearrangement loop on one board, exposes a low-latency move stream suitable for AOD/AWG backends, and documents resource headroom for larger arrays. Strengths that should be credited include real-silicon timing on a ZCU216 with stage breakdowns and standard deviations, post-place-and-route utilization, open-source release, and an explicit interleaved generation/execution model with literature-based physical timing bounds (Eqs. 1–3, Fig. 8). The algorithmic novelty is limited (FPGA port of HiPARS plus prior detection IP); the value is architectural integration and measured end-to-end behavior. Significance for the control-hardware community is solid but currently tempered by software-in-the-loop evaluation and the lack of a quantitative host baseline.

major comments (4)

Sec. V-B, Eqs. (1)–(3), and Fig. 8: the architectural claim that streaming eradicates rearrangement overhead after the first move is only supported under the slow physical model (t_transfer=800 µs, v=0.054 µm/µs). Under the equally literature-based fast model (120 µs, 0.55 µm/µs), the same 16×16/22-move trace shows execution idle gaps, so generation is not fully hidden. The abstract and conclusion should state the operational regime explicitly and discuss what generation-rate improvements would be required for the fast end of present AOD/SLM hardware, rather than leaving the caveat only in the figure discussion.
Fig. 5 and Sec. IV-A vs. Sec. V-B: the evaluated path is software-in-the-loop through the PS (solid lines); camera→IP, FIFO→AWG, and on-FPGA feedback are dashed “planned” extensions. Table I’s end-to-end and first-move latencies therefore include PS orchestration, AXI-Lite handshakes, and PS-side stream consumption. The manuscript should separate pure FPGA compute time from PS/host path overhead and state which numbers are expected to remain once the dashed path is closed; otherwise the “end-to-end FPGA-based” claim overstates what was measured.
Sec. V (Latency) and the abstract claim of eliminating host-mediated round-trip latency: there is no quantitative baseline for the same 16×16 workload on a conventional host-CPU pipeline, or on a non-streaming FPGA design that buffers the full move list before emission. Absolute times (25.3 ms, 4 ms first move) are useful but do not by themselves establish the magnitude of the co-location/streaming benefit. A controlled comparison—or at least a carefully instrumented host round-trip measurement—is needed to substantiate the central systems claim.
Abstract and Sec. III–IV: the abstract calls the rearrangement algorithm “newly developed,” while the text states it is an FPGA/HLS adaptation of HiPARS row-by-row lattice sorting with a prior detection module. Novelty should be framed as integration, streaming I/O, and hardware mapping, not as a new sorting algorithm. Relatedly, Sec. V-A verifies only on simulated images with perfect move application to ground-truth occupancy; detection errors and atom loss in transit are not exercised. These limitations should be stated clearly so the correctness claim is scoped to algorithmic move generation, not full physical initialization fidelity.

minor comments (6)

Sec. V-C vs. Table II: the text reports 20.8% BRAM utilization and “202 tiles” for rearrangement BRAM, while Table II lists 46 BRAM (36K) total and 4.3% utilization (22 for rearrangement). Reconcile the hierarchical report numbers with the prose.
Fig. 9 caption: resource curves are HLS estimates and are correctly labeled as upper bounds; still, state the post-implementation 16×16 point from Table II on the same plot or in the caption so readers can gauge the HLS-to-P&R gap.
Sec. II-B and Fig. 2: “interleaved approach” is clear, but define whether move packets can be back-pressured by the AWG and how FIFO depth was chosen relative to worst-case burstiness of S1–S3.
Table I: report the number of independent runs (stated as 10 in text) and the array pitch used for Fig. 8 (4 µm) in the table caption for reproducibility.
Minor wording: “rearrangement module for this work’s integration solution” in Sec. III appears to refer to the detection unit; clarify. Also fix occasional grammar (“atom in parallel,” “we can rearrange atom”).
Cite and briefly contrast other recent NA rearrangement/control stacks (beyond the authors’ own HiPARS and detection papers) so the integration contribution is positioned against concurrent FPGA/ASIC control efforts.

Circularity Check

0 steps flagged · score 1.0 of 10

No load-bearing circularity: reported latencies are direct post-implementation measurements; prior self-cited modules are re-validated end-to-end as black boxes.

full rationale

The paper's central quantitative claims (25.3 ms end-to-end, 4 ms first-move, ~1.01 ms/move on a 16 imes16 array) are obtained by instrumenting AP_START/AP_DONE and AXI-Stream packet arrival on a ZCU216 at 100 MHz (Table I, Sec. V-B). These are hardware wall-clock measurements, not algebraic consequences of fitted parameters. The image-analysis IP and HiPARS-derived rearrangement algorithm are imported from the authors' prior works ([20],[37],[12],[21]), yet the integration is treated as a new pipeline whose correctness is re-checked by applying generated moves to ground-truth occupancy and matching the target geometry (Fig. 7, Sec. V-A). Resource numbers are post-place-and-route hierarchical reports (Table II); scalability trends are HLS estimates of buffer growth (Fig. 9). The physical t_exec models (Eqs. 1–3) are taken from external literature values and used only for comparison, not as inputs that force the measured generation times. No equation equates a claimed prediction to a quantity defined by the authors' own fit or definition. Minor self-citation of components is present but not load-bearing for the latency or resource results, yielding a score of 1.

Assumptions & free parameters 2 free parameters · 3 assumptions · 1 invented entities

The paper is an engineering systems design; its claims rest on standard digital-design practice, published physical parameters of AOD/SLM traps, and the correctness of two previously published modules. No new physical constants or free parameters are fitted to produce the latency numbers.

free parameters (2)

binarization threshold for occupancy map
Set by offline calibration on the PS; value is experiment-specific and not reported numerically, but the latency claim does not depend on its exact value.
parallel-move buffer width (AOD channel count)
Fixed by physical AOD hardware limits rather than fitted; kept constant while array size is scaled.

assumptions (3)

domain assumption Physical move time can be modeled as 2·t_transfer + d_move/v with literature ranges t_transfer ∈ [120,800] µs and v ∈ [0.054,0.55] µm/µs
Used in Sec. V-B and Fig. 8 to argue that generation latency can be hidden; taken from cited experimental papers.
domain assumption The previously published FPGA image-analysis module correctly reconstructs occupancy from fluorescence images given a PSF kernel
Invoked as a black-box component (Sec. IV); correctness of the integrated pipeline inherits its fidelity.
standard math HLS PIPELINE II=1 and dual-port BRAM enable in-place compaction at one element per cycle
Standard FPGA scheduling assumption used throughout the rearrangement FSM description.

invented entities (1)

AtomFlow streaming control architecture
purpose: Unify image analysis and rearrangement on one FPGA with AXI-Stream move emission to eliminate host round-trips
The named system is the paper’s contribution; it is an engineering assembly rather than a new physical entity.

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Cite this review

Pith. "Pith review of AtomFlow: An End-to-End FPGA-Based Control Architecture for Neutral Atom Quantum Computers." pith.science (2026). https://pith.science/paper/6BW426BV

@misc{pith2026260711490,
  author       = {Pith},
  title        = {Pith review of: AtomFlow: An End-to-End FPGA-Based Control Architecture for Neutral Atom Quantum Computers},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/6BW426BV}},
  note         = {Machine review of arXiv:2607.11490}
}

read the original abstract

Neutral Atom Quantum Computing (NAQC) is an emerging modality for scalable quantum computation, valued for its long coherence times and the naturally identical atomic qubits. However, one of the main drawbacks is its slow execution rate, dominated by lengthy classical processing tasks, such as fluorescence imaging, cooling, and atom rearrangement. We address this bottleneck with AtomFlow, a field-programmable gate array (FPGA)-based control architecture that consolidates fluorescence-image analysis and a newly developed atom-rearrangement algorithm onto a single Zynq UltraScale+ device. By co-locating the two stages on the same board and emitting rearrangement moves in a streaming fashion as soon as they are computed, AtomFlow eliminates the round-trip latency of conventional host-mediated pipelines. Evaluated on a 16x16 atom array, AtomFlow achieves an end-to-end latency of 25.3 ms with a first-move latency of 4 ms and an average move generation of 1 ms. Furthermore, our scalability analysis demonstrates that the architecture can readily support larger atom arrays within a single-board resource budget.

Figures

Figures reproduced from arXiv: 2607.11490 by the authors.

**Figure 3.** By-row lattice sorting scheme. The sorting channel [PITH_FULL_IMAGE:figures/full_fig_p003_3.png] view at source ↗

**Figure 2.** Sequential (blue) sequence diagram of rearrangement [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗

Figures from the paper (4 more)

**Figure 5.** Figure 5: System architecture of AtomFlow. Solid black lines [PITH_FULL_IMAGE:figures/full_fig_p004_5.png]

**Figure 6.** Figure 6: High-level architecture of the FPGA-based Atom [PITH_FULL_IMAGE:figures/full_fig_p005_6.png]

**Figure 7.** Figure 7: Visualization of 24×24 rearrangement. (a) Initial random atom array. (b) Final array after rearrangement. (c) Target geometry of size 16×20. It describes for each site whether it will be occupied after sorting or not. The target geometry array is smaller than the total…

**Figure 9.** Figure 9: FPGA resource scaling of the atom rearrangement [PITH_FULL_IMAGE:figures/full_fig_p008_9.png]

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Amba 4 axi4, axi4-lite, and axi4- stream protocol assertions user guide,

ARM, “Amba 4 axi4, axi4-lite, and axi4- stream protocol assertions user guide,” 2012. [On- line]. Available: https://developer.arm.com/documentation/dui0534/b/ Parameter-Descriptions/Interface/AXI4-and-AXI4-Lite-interfaces

2012

Pith tools

Reviewed July 14, 2026 · model on record in the stance chip above.

[1] [1]

Quantum chemistry with provable convergence via randomized sample- based quantum diagonalization,

S. Piccinelli, A. Baiardi, M. Rossmannek, A. C. Vazquez, F. Tacchino, S. Mensa, E. Altamura, A. Alavi, M. Motta, J. Robledo-Morenoet al., “Quantum chemistry with provable convergence via randomized sample- based quantum diagonalization,”arXiv preprint arXiv:2508.02578, 2025

arXiv 2025

[2] [2]

Engineering high-coherence superconducting qubits,

I. Siddiqi, “Engineering high-coherence superconducting qubits,”Nature Reviews Materials, vol. 6, no. 10, pp. 875–891, 2021

2021

[3] [3]

Quantum computing with trapped ions: a beginner’s guide,

F. Bernardini, A. Chakraborty, and C. R. Ord ´o˜nez, “Quantum computing with trapped ions: a beginner’s guide,”European Journal of Physics, vol. 45, no. 1, p. 013001, 2024

2024

[4] [4]

A manufacturable platform for photonic quantum computing,

PsiQuantum team, “A manufacturable platform for photonic quantum computing,”Nature, vol. 641, no. 8064, pp. 876–883, 2025

2025

[5] [5]

Logical quantum processor based on reconfigurable atom arrays,

D. Bluvstein, S. J. Evered, A. A. Geim, S. H. Li, H. Zhou, T. Manovitz, S. Ebadi, M. Cain, M. Kalinowski, D. Hangleiteret al., “Logical quantum processor based on reconfigurable atom arrays,”Nature, vol. 626, no. 7997, pp. 58–65, 2024

2024

[6] [6]

Optimized measurement-free and fault-tolerant quantum error correction for neutral atoms,

S. Veroni, M. M ¨uller, and G. Giudice, “Optimized measurement-free and fault-tolerant quantum error correction for neutral atoms,”Physical Review Research, vol. 6, no. 4, p. 043253, 2024

2024

[7] [7]

High- fidelity parallel entangling gates on a neutral-atom quantum computer,

S. J. Evered, D. Bluvstein, M. Kalinowski, S. Ebadi, T. Manovitz, H. Zhou, S. H. Li, A. A. Geim, T. T. Wang, N. Maskaraet al., “High- fidelity parallel entangling gates on a neutral-atom quantum computer,” Nature, vol. 622, no. 7982, pp. 268–272, 2023

2023

[8] [8]

A tweezer array with 6,100 highly coherent atomic qubits,

H. J. Manetsch, G. Nomura, E. Bataille, X. Lv, K. H. Leung, and M. Endres, “A tweezer array with 6,100 highly coherent atomic qubits,” Nature, vol. 647, no. 8088, pp. 60–67, 2025

2025