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REVIEW 3 major objections 5 minor 47 references

From Circuits to Hardware: Benchmarking Standard and Qubit-Efficient Quantum Optimization on Real Hardware

T0 review · 3 major / 5 minor · reviewed 2026-07-14 · grok-4.5

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Pith's one-line read On present hardware, gate-based quantum optimizers become noise-dominated near 770 two-qubit gates, while dense assignment problems yield no feasible solutions at all.

desk verdict Solid, first-of-its-kind multi-family hardware baseline for quantum optimization; the F_est thresholds and QAP/QAOA claims hold up under the stated protocol. read the letter →

arxiv 2607.11637 v1 pith:SVNXUMZ3 submitted 2026-07-13 quant-ph

Monit Sharma , Hoong Chuin Lau This is my paper
classification quant-ph
keywords quantumoptimizationbenchmarkingVQEQAOAqubit-efficientencodingcombinatorialNISQhardwarefidelity
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper builds a common-protocol, real-hardware baseline for gate-based quantum optimization across four hard combinatorial problems and seven method families. It shows that practical outcomes are set by the joint effect of problem structure, encoding, compilation, and device noise, not by algorithmic qubit count alone. For packing and independent-set instances, an empirical fidelity proxy near 0.1—about 770 two-qubit gates at median Heron-r2 error—marks the transition into noise-dominated execution. Quadratic assignment is a separate failure mode: dense one-hot encodings and an exponentially sparse feasible set leave no tested hardware method able to return a valid assignment. Compiled QAOA-family circuits sit deep in the low-fidelity regime, and most of their feasible outputs fall inside a matched uniform-random control. Qubit-efficient encodings enlarge the set of runnable instances, but only inside that same fidelity budget.

What carries the argument

The independent-error gate-count fidelity proxy F_est ≈ (1 − ε_2Q)^N_2Q, built from transpiled two-qubit gate counts and backend calibration data, used as a diagnostic to separate signal-preserving from noise-dominated hardware regimes.

What would settle it

Re-run the same MDKP and MIS circuits after stronger routing or on lower-error hardware so F_est exceeds 0.1, and test whether QAOA-family solutions then systematically beat the matched random control and whether any method returns a feasible QAP assignment.

Watch

Extended reading notes

Core claim

Across 247 method–instance combinations on Heron-family processors, an independent-error gate-count fidelity near F_est ≈ 0.1 marks the onset of noise-dominated execution for multi-dimensional knapsack and maximum independent set; no tested hardware method produces a feasible quadratic-assignment solution; and most feasible low-fidelity QAOA-family outcomes lie within a matched uniform-random best-shot range under the same selection and local-refinement rules.

Load-bearing premise

A simple product of two-qubit error rates over gate count, under a fixed short optimizer budget, is enough to mark when hardware results stop carrying real algorithmic signal.

Editorial extensions

If this is right

  • Deployability should be judged by transpiled two-qubit count times gate error, not by qubit count alone.
  • Dense one-hot assignment problems remain outside the reliable operating regime of the tested end-to-end pipelines.
  • Deeply compiled QAOA-family implementations under this protocol should not be assumed to beat best-of-budget random selection.
  • Future hardware studies must report feasibility, transpiled resources, and a fidelity proxy alongside objective values.
  • Qubit-efficient encodings help only when the compressed circuits stay inside the empirical fidelity budget after routing and decoding.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • As two-qubit error rates fall, the ~770-gate threshold will move outward, but only if compilation expansion also shrinks for structured ansätze.
  • Encoding changes that enlarge the feasible-manifold fraction, not just width reduction, are likely required before QAP-like problems become hardware-accessible.
  • For the instance sizes tested, classical solvers remain the practical solvers; the lasting contribution is the diagnostic protocol itself.
  • Negative simulator–hardware gaps on some packing instances suggest finite-shot selection and trajectory effects can dominate idealized noise models.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 5 minor

Summary. The manuscript reports a unified real-hardware benchmark of gate-based quantum optimization methods (VQE, CVaR-VQE, standard/multi-angle/warm-start QAOA, PCE, and QRAO) across four NP-hard combinatorial problems (MDKP, MIS, QAP, MSP) on IBM Heron r1/r2 processors under a common fixed-budget protocol with resilience-level-2 mitigation. Across 247 method–instance combinations the authors report transpiled circuit resources, an independent-error gate-count fidelity proxy F_est, feasibility, and solution quality relative to classical references, together with matched uniform-random controls, MPS stability audits, and compilation-only counterfactuals. The central empirical claims are that an operating point near F_est ≈ 0.1 marks the onset of noise-dominated execution for MDKP and MIS, that no tested method recovers a feasible QAP assignment (attributed to dense one-hot encodings and an exponentially sparse feasible manifold), that most low-fidelity QAOA-family outcomes are compatible with random best-of-budget sampling, and that qubit-efficient encodings extend runnable sizes only within the empirical fidelity budget.

Significance. If the reported regimes hold, the work supplies a timely, reproducible empirical baseline that the community currently lacks: multi-family, multi-problem hardware results under one protocol, including the first real-hardware QRAO data and the first multi-problem PCE hardware benchmark. Strengths include the explicit F_est diagnostic tied to calibration data, the matched random-control design (Appendix N), the compilation counterfactuals that leave deep QAOA circuits below F_est = 10^{-3}, the MPS bond-cap audits, full backend-aware resource tables, and public code. These elements make the paper more than a collection of runs; they give practitioners concrete decision guidance (Table 20) and a diagnostic framework that can track progress as hardware improves. The honesty about scope (tested implementations, not QAOA in general; fixed-budget protocol rather than best-case) further increases its value as a reference.

major comments (3)
  1. Section 4.5 and Appendix C: the common protocol is a single COBYLA trajectory with a hard 200-evaluation cap and uniform [0, 2π] initialization. The reduced multi-seed simulator study (Table 26) already shows material initialization sensitivity for VQE and WS-QAOA (gaps ranging 8–50 % on MIS 1tc.32). Because the headline tables report only one primary execution per method–instance pair, the cross-family ranking is protocol-conditioned rather than robust. A short additional multi-seed hardware or high-fidelity simulator panel on a few representative instances (or an explicit statement that all claims are strictly under the stated fixed-budget protocol) is needed to keep the comparative claims load-bearing.
  2. Section 4.8 and the hardware-diagnostics appendices: backend heterogeneity (ibm_fez, ibm_torino, ibm_marrakesh) is acknowledged but not quantified. Different topologies, calibration windows, and routing overheads can shift both N_2Q and realized F_est. For the key claims that rest on absolute gate counts (the F_est ≈ 0.1 operating point and the QAOA random-control comparison), a brief sensitivity check—e.g., re-transpiling a subset of circuits under a single fixed backend calibration snapshot—would strengthen the claim that the observed regimes are not artifacts of device assignment.
  3. Section 5.4 and Appendix A: the QAP infeasibility conclusion is strong and well-supported by the feasible-fraction calculation (10!/2^100 ≈ 10^{-23.54}). However, only the direct one-hot encoding is tested. Because the paper’s broader thesis is that encoding choice interacts with hardware constraints, a short discussion (or a single alternative encoding experiment, even if only in simulation) of whether a more compact or hierarchical assignment encoding could move any QAP instance into the F_est ≳ 0.1 regime would make the structural-barrier claim more complete.
minor comments (5)
  1. Figure 5 caption and Section 5.8: the upper x-axis uses a fixed ε_2Q = 0.003 reference; it would help readers if the caption explicitly stated that backend-specific F_est values (Appendix O) can differ slightly from this visual reference.
  2. Table 1 and Appendix A: the coefficient dynamic-range column mixes scientific notation inconsistently (e.g., 8.53×10^3 vs 2.21×10^10); a uniform format would improve readability.
  3. Section 3.5: the MSP quality metrics (TDev, MDev, AR_TDev) are well-motivated, but a one-sentence reminder that AR_TDev = 1 is the certified optimum would help readers who jump directly to the tables.
  4. Appendix D: the multi-reoptimization and dynamic-perturbation enhancements are described in detail, yet the main-text PCE results use only the single-pass protocol. A clearer cross-reference early in Section 4.6 would prevent readers from assuming the full enhancement suite was applied.
  5. Minor typographical inconsistencies appear in a few places (e.g., “ans¨ atze”, “to ising()”, occasional missing spaces around em-dashes). A final copy-edit pass would polish the manuscript.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: empirical hardware benchmark with independent diagnostics, analytical penalties, and matched random controls.

full rationale

The paper is a fixed-protocol empirical comparison of VQE/CVaR-VQE, QAOA-family, PCE, and QRAO across MDKP, MIS, QAP, and MSP on IBM Heron hardware. Load-bearing claims rest on (i) feasibility and gap-to-BKS against classical references, (ii) transpiled N_2Q and backend calibration, (iii) the independent-error proxy F_est ≈ (1−ε_2Q)^N_2Q used only as a diagnostic, not as a fitted predictor of rankings, and (iv) a matched uniform-random best-shot control for low-fidelity QAOA-family runs. Penalty coefficients are fixed analytically by the pre-penalty objective-bound rule before any quantum execution and are not tuned to hardware outcomes. Thresholds F_est≈0.1 and 0.01 are explicitly labeled benchmark-specific empirical reference points, not first-principles predictions. Compilation counterfactuals hold circuits and parameters fixed and only re-route. No self-definitional loop, fitted-input-as-prediction, load-bearing self-citation uniqueness claim, or renaming of a known result as a derivation was found. The work is self-contained against external classical BKS and random baselines.

Assumptions & free parameters 5 free parameters · 4 assumptions · 1 invented entities

As an empirical benchmarking study the paper inherits standard quantum-computing and combinatorial-optimization background; its distinctive free choices are the fixed experimental protocol parameters and the diagnostic thresholds derived from them. No new physical entities are postulated.

free parameters (5)
  • CVaR confidence level α = 0.25
    Fixed at 0.25 for all CVaR-VQE runs; not swept.
  • QRAO compression parameter k = 3
    Set to 3 (highest usable compression under depth constraints).
  • Optimizer evaluation budget = 200 evals / 1000 shots
    Hard cap of 200 COBYLA evaluations and 1000 shots per evaluation used for every method–instance pair.
  • F_est diagnostic thresholds = 0.1 / 0.01
    Empirical operating points F_est ≈ 0.1 and 0.01 (≈770 and 1540 two-qubit gates at ε_2Q = 3e-3) chosen from observed data to separate signal-preserving from noise-dominated regimes.
  • Automatic QUBO penalty multiplier λ = instance-specific (Eq. 6)
    Selected once per instance by the Qiskit objective-bound rule before any quantum execution; not re-tuned to hardware outcomes.
assumptions (4)
  • domain assumption Independent, identically distributed depolarizing errors on two-qubit gates dominate the process-fidelity estimate F_est ≈ (1 − ε_2Q)^N_2Q.
    Stated explicitly in Sec. 4.13; coherent errors, crosstalk and readout are neglected.
  • domain assumption The Qiskit automatic penalty construction (Eq. 6) produces a valid unconstrained QUBO whose low-energy states correspond to high-quality feasible solutions of the original constrained problem.
    Used uniformly for all constrained instances (Sec. 4.3).
  • ad hoc to paper A single fixed-budget COBYLA trajectory with uniform [0, 2π] initialization is a fair common protocol for cross-method comparison.
    Adopted in Sec. 4.5; reduced multi-seed checks show initialization sensitivity but do not alter the protocol.
  • standard math Classical best-known or certified optima (BKS) from the cited libraries are correct reference values for gap reporting.
    Taken from QAPLIB, knapsack and market-share sources listed in Sec. 3.3.
invented entities (1)
  • Independent-error gate-count fidelity proxy F_est independent evidence
    purpose: Provide a single scalar that maps transpiled two-qubit gate count and backend error rate onto a signal-versus-noise diagnostic.
    Defined in Eq. (11); not a new physical quantity but a paper-specific diagnostic whose numerical thresholds are data-driven.

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Pith. "Pith review of From Circuits to Hardware: Benchmarking Standard and Qubit-Efficient Quantum Optimization on Real Hardware." pith.science (2026). https://pith.science/paper/SVNXUMZ3

@misc{pith2026260711637,
  author       = {Pith},
  title        = {Pith review of: From Circuits to Hardware: Benchmarking Standard and Qubit-Efficient Quantum Optimization on Real Hardware},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/SVNXUMZ3}},
  note         = {Machine review of arXiv:2607.11637}
}
abstract

Despite rapid progress in quantum optimization, broad real-hardware benchmarks comparing multiple algorithmic families across diverse combinatorial problems under a common protocol remain limited. We benchmark gate-based quantum optimization on four NP-hard problems: multi-dimensional knapsack (MDKP), maximum independent set (MIS), quadratic assignment (QAP), and market-share (MSP). We study VQE, CVaR-VQE, standard, multi-angle, and warm-start QAOA, together with qubit-efficient PCE and QRAO, on IBM Heron r1/r2 processors using resilience-level-2 mitigation. To our knowledge, this includes the first real-hardware QRAO results and the first multi-problem PCE hardware benchmark. Across 247 method-instance combinations, we report transpiled circuit size, hardware outcomes, and an independent-error gate-count fidelity proxy, $F_{\mathrm{est}}$. For MDKP and MIS, an empirical operating point near $F_{\mathrm{est}}\approx 0.1$, corresponding to about 770 two-qubit gates at the median Heron-r2 CZ error rate, marks the onset of noise-dominated execution. QAP exposes a separate bottleneck: dense one-hot encodings and an exponentially sparse feasible manifold, with feasible fraction $10!/2^{100}$ at $n=10$; no tested hardware method produces a feasible assignment. Compiled QAOA-family circuits are generally noise dominated, and a matched uniform-random control shows that most feasible low-fidelity outcomes fall within the random range, apart from one finite-sample MIS warm-start exception. A SWAP-aware, fractional-gate, Nighthawk-topology compilation counterfactual reduces two-qubit counts but leaves all circuits below $F_{\mathrm{est}}=10^{-3}$. These conclusions apply to the tested implementations rather than QAOA in general. Qubit-efficient methods extend runnable instance sizes, but only within the empirical fidelity budget.

Figures

Figures reproduced from arXiv: 2607.11637 by the authors.

Figure 1
Figure 1. MDKP simulator versus hardware performance across qubit-efficient and variational methods. Panel (a) compares PCE and QRAO on MDKP instances using gap to the optimal solution, while panel (b) reports the corresponding comparison for VQE and CVaR-VQE. The figure shows that simulator-side rankings do not transfer uniformly to hardware: some methods retain moderate performance degradation, whereas others exhibit larger… view at source ↗
Figure 2
Figure 2. Hardware performance and feasibility breakdown for MIS. Panel (a) reports finite optimality gaps for feasible method–instance outcomes; hatched bars denote infeasible outcomes. WS-QAOA is the only feasible method on 1tc.64. Panel (b) reports the number of feasible methods out of seven for each instance: 7/7, 7/7, 4/7, 1/7, 0/7, 0/7, and 0/7 from 1tc.8 through 1dc.128. Feasibility therefore collapses sharply with pro… view at source ↗
Figure 3
Figure 3. QAP simulator versus hardware comparison. The direct QAP encoding combines dense flow-distance couplings with row-and-column one-hot assignment constraints; for the tested n = 10 and n = 12 instances, valid assignments occupy approximately 10−23.54 to 10−34.67 of the full binary hypercube. PCE returns feasible simulator candidates on several instances, although with large optimality gaps, whereas none of the seven h… view at source ↗
Figures from the paper (8 more)
Figure 4
Figure 4. Figure 4: Historical QAOA-family two-qubit-gate counts before and after transpilation. Each row compares the same representative bound depth-3 circuit before backend mapping with the corresponding historically executed backend-native circuit. The four problem families are repres…
Figure 5
Figure 5. Figure 5: Backend-native circuit complexity, feasibility, and hardware solution quality. (a) Feasible MDKP and MIS hardware outcomes, plotted as optimality gap to BKS against the transpiled two-qubit-gate count N2Q. (b) Infeasible hardware outcomes, grouped into shaded problem-f…
Figure 6
Figure 6. Figure 6: Feasible MDKP and MIS hardware outcomes versus the independent-error gate-count fidelity proxy Fest. (a) Strongly noise-dominated regime, Fest < 10−3 . (b) Signal-preserving regime, Fest ≥ 10−3 . The panels are ordered from lower to higher fidelity to make the transiti…
Figure 7
Figure 7. Figure 7: Feasibility phase diagram. Cell colour indicates the fraction of hardware runs that returned feasible solutions for each (problem, method-family) pair. Cell annotation reports the median hardware gap to BKS among feasible runs (TDev for MSP, for which a target-deviatio…
Figure 8
Figure 8. Figure 8: Qubit count versus recovered hardware solution quality for MDKP and MIS. Filled markers denote MDKP results and open markers denote MIS results, with regions indicating PCE, QRAO, and full-width formulations. The scatter shows that lower qubit count does not by itself …
Figure 9
Figure 9. Figure 9: Compilation-only counterfactual audit for 12 representative bound QAOA-family circuits. Top: post-transpilation two-qubit-gate counts under reconstructed historical compilation, a SWAP-aware Heron surrogate, fractional-gate Heron compilation, and a topology-only SWAP-a…
Figure 10
Figure 10. Figure 10: QAOA-family transpilation expansion factors for the 12 representative circuits in [PITH_FULL_IMAGE:figures/full_fig_p044_10.png]
Figure 11
Figure 11. Figure 11: Matched uniform-random baseline for low-fidelity QAOA-family hardware runs. Filled circles show final hardware outcomes. Open circles show random medians, and vertical intervals show the central 2.5–97.5% range across 300 matched random replicates. Each random pool ma…

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