Hardware-Software Co-Design for Float16 On-Device Training on RISC-V Single-Core

Benjamin Hubinet; Jean-Baptiste Rigaud; Olivier Potin; Olivier Savry; Pierre-Alain Moellic

REVIEW 3 major objections 6 minor 13 references

Hardware-Software Co-Design for Float16 On-Device Training on RISC-V Single-Core

T0 review · 3 major / 6 minor · reviewed 2026-08-01 · deepseek-v4-flash

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Pith's one-line read Full float16 on-device training of small neural networks is achievable on a resource-constrained RISC-V single-core using the standard Zfh and Zvfh extensions, cutting memory use by about half versus float32 with minimal accuracy loss.

desk verdict Useful incremental result: float16 on-device training on single-core RISC-V works in simulation and Zfh area cost is cleanly measured; the Zvfh and 'on-device' claims outrun the evidence. read the letter →

arxiv 2607.21130 v1 pith:MQZQNWFH submitted 2026-07-23 cs.AR cs.AI

Benjamin Hubinet , Pierre-Alain Moellic , Olivier Savry , Olivier Potin , Jean-Baptiste Rigaud This is my paper · ORCID

classification cs.ARcs.AI

keywords on-devicetrainingfloat16RISC-VZfhZvfhAIfESFPGAmemoryfootprint

verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper tries to establish that complete on-device training of deep neural networks—not just inference or fine-tuning—can run on a resource-constrained RISC-V single-core when all training state is kept in float16. It does this by extending the AIfES DNN framework with hand-optimized kernels for the standard RISC-V extensions Zfh (scalar float16) and Zvfh (vector float16), reporting about 50% lower memory use than float32 and validation accuracies within roughly one point on MNIST, FashionMNIST, and an EMNIST fine-tuning task. The paper also quantifies the hardware cost: enabling Zfh in the NaxRiscv FPGA core costs about +1.15% LUTs and +0.05% flip-flops at 175 MHz, and it sketches a four-lane vector unit that would implement Zvfh. A sympathetic reader would care because this suggests standard RISC-V extensions alone could make full training practical on tiny edge devices that currently only support inference.

What carries the argument

The load-bearing mechanism is the pairing of the standard RISC-V Zfh/Zvfh extensions with a modular DNN training framework that can swap in hand-vectorized float16 kernels. Zfh and Zvfh are the RISC-V standard extensions for scalar and vector half-precision floating-point arithmetic; they matter because they let all training state live in float16 without custom accelerators or non-standard instruction sets. Zfh's implementation trick is nan-boxing: narrow float16 values are padded with ones and carried through the 64-bit FPU datapath, which is why adding support to the NaxRiscv FPU costs little. Zvfh's proposed vector unit uses four 64-bit lanes fed by crossbars, a vector register file merge

What would settle it

Train the same 5-layer MLP on MNIST in float16 on a physical Zfh-enabled RISC-V core (or the implemented NaxRiscv FPGA target) and compare validation accuracy, memory footprint, and runtime with the simulator results; divergence in accuracy beyond the reported roughly one point, memory above about 50% savings, or significantly different speed would falsify the central claim. For the Zvfh part, implement the four-lane VLEN=64 VPU and check that the float16 vector kernels produce correct results and the predicted 4x raw speed-up.

Watch

Extended reading notes

Core claim

On its own terms, the paper's central claim is that full float16 on-device training is possible on resource-constrained RISC-V single-core processors supporting the standard Zfh and/or Zvfh extensions, while requiring about 50% less memory than float32 training. The evidence consists of an extended AIfES framework with float16 math primitives, a model converter that can freeze layers for transfer learning, and training experiments run on a RISC-V ISA simulator: a 5-layer MLP trained from scratch on MNIST and FashionMNIST reaches validation accuracies within about one point of float32 (e.g., 97.29% vs 96.88% on MNIST/SGD), and fine-tuning a pretrained MLP on EMNIST shows a flat 50% reduction

Load-bearing premise

The weakest load-bearing premise is that the RISC-V ISA simulator used for all training results (Section 2.2) faithfully reproduces the numerical behavior and performance of the real NaxRiscv core, and, for the Zvfh part, that the vector unit described in Section 3.3 works as designed; the authors themselves state that measuring on the FPGA target is future work.

Editorial extensions

If this is right

A single-core RISC-V MCU with Zfh support can run end-to-end float16 training, cutting parameter memory to about half of float32 while keeping validation accuracy within about a point.
Because Zfh costs only about 1.15% extra LUTs and 0.05% extra flip-flops with no clock drop on the NaxRiscv FPGA core, adding half-precision training capability to existing RISC-V designs is cheap.
A Zvfh vector unit with four 64-bit lanes would give a raw 4x SIMD speed-up for float16 kernels while keeping standard vector code portable across RISC-V implementations.
Layer freezing in the converter enables on-device fine-tuning and transfer learning, with additional working-memory savings when only the last layer is trained.
The approach supports batch sizes greater than 1 in full float16 training, unlike some prior RISC-V training frameworks that are limited to batch size 1.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

The paper leaves implicit that the same framework should port to any Zvfh-capable RISC-V core, not just NaxRiscv, because Zvfh is a standard extension; that portability is testable once real Zvfh silicon exists.
A logical next experiment is to measure actual training energy and throughput on the FPGA target; if the simulator's cycle counts are close to silicon, float16 ODT could become viable for battery-powered sensors.
Because Adam stores two optimizer states per parameter, the 50% memory reduction is much smaller when Adam is used; with SGD and frozen early layers, working memory approaches the model size, making optimizer choice—not precision—the main memory lever.
The vrgather handling points to a boundary for the design: gather-like vector instructions need special treatment when register groups are split into micro-ops, so the proposed Zvfh support is best seen as a deliberate architectural approach rather than a proof that every RVV instruction maps cleanly onto lanes.

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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Desk Editor's Note

read the letter

Read it. The core result is a working open-source integration: AIfES extended with Zfh/Zvfh kernels, plus a measured Zfh implementation in NaxRiscv. The memory reduction is arithmetic — float16 halves model and gradient storage — and the Zfh area numbers (+1.15% LUT, +0.05% FF, no frequency drop) are clean synthesis results. That part deserves credit. The comparison against float32 on four dataset/optimizer combos is also good, not just a single demo.

The soft spots are about the gap between what they demonstrate and what the conclusion claims. Training is done on a RISC-V ISA simulator, not on the NaxRiscv core or real silicon. That doesn't invalidate the numerical feasibility — FP16 training converges within a point of FP32 — but it does mean 'on-device' is an extrapolation, especially because a simulator doesn't model microarchitectural FPU behavior or NaN-boxing edge cases. The accuracy results are single runs with no seeds or error bars; the differences (97.29 vs 96.88, etc.) are within run-to-run noise, so 'minimal degradation' is weaker than it looks. And Zvfh is design-only: no timing, no area, no measured speedup. The paper says as much in the future work, but the abstract and conclusion still put Zvfh alongside Zfh as if both are demonstrated. The vrgather micro-op discussion is thoughtful, but it's an architecture proposal, not a result.

One pushback: the reader's weakest assumption about simulator fidelity is real, but it's not load-bearing for the central claim. The Zfh area measurement and the memory arithmetic are the solid contributions; the training results are supporting evidence, not the main proof. The paper would be stronger if they ran Zfh training on the actual FPGA softcore and repeated benchmarks a few times.

Who is this for? Embedded ML engineers wanting fine-tuning on single-core RISC-V, and people designing cheap FP16-capable cores. It's an incremental but useful data point. Serious referee: yes — a real implementation with reproducible numbers. Ask for seeds/repeats, run on real hardware, and temper the Zvfh language. I'd bring it to a reading group as an example of honest co-design reporting, despite the overstated edges.

Referee Report

3 major / 6 minor

Summary. The paper presents a hardware–software co-design flow for float16 on-device training (ODT) on RISC-V single-core processors. The software contribution extends the open-source AIfES framework with RISC-V Zfh/Zvfh float16 kernels, a converter from PyTorch/TensorFlow models, and layer-freezing support for transfer learning. Training experiments on an MLP (512-256-128-64-10) on MNIST and FashionMNIST, run on a RISC-V ISA simulator, show F16 accuracy within about 0.7 percentage points of F32, and memory measurements report an approximately 50% reduction in model and work memory when using float16. The hardware contribution is an implementation of the scalar Zfh extension in the NaxRiscv out-of-order FPGA softcore, with a reported +1.15% LUT6 and +0.05% FF area overhead at 175 MHz, plus a design discussion of a Zvfh vector processing unit with four lanes and VLEN=64. The conclusion claims that full float16 ODT is possible on resource-constrained RISC-V single-cores with Zfh and/or Zvfh, with about 50% memory savings and minimal accuracy loss.

Significance. If the claims hold, this is a useful practical contribution: it would make full float16 training, not just inference or quantized fine-tuning, accessible on small RISC-V cores, with a solid arithmetic memory reduction and a measured low area cost for Zfh. The open-source release of the framework and the clean synthesis measurement for Zfh are strengths. The paper honestly states in the final paragraph that training was validated on an ISA simulator and that Zvfh performance evaluation is future work; however, the abstract and conclusion do not carry this caveat, and the central 'on-device' claim is therefore stronger than the evidence. The accuracy comparison is based on four single runs without seeds or error bars, so the 'minimal degradation' part of the claim is not yet statistically demonstrated. The Zvfh part is an architecture proposal, not an implemented and measured design. These are external-validation gaps rather than internal inconsistencies, and they are fixable, but they currently prevent the strongest form of the conclusion.

major comments (3)

[§2.2, Table 2] The claim of 'minimal model performance degradation' rests on four single training runs with no seeds, no error bars, and no repetition. The reported F16-vs-F32 differences are at most 0.68 percentage points (FashionMNIST SGD) and can readily be within run-to-run variation for MLPs at this scale. Please provide mean±standard deviation over at least 5 seeds (or otherwise quantify variance) and report the same hyperparameters for all datasets. Without this, the accuracy comparison is not load-bearing evidence for the conclusion.
[§2.2, Conclusion] All training experiments are performed on a RISC-V ISA simulator, not on the NaxRiscv FPGA target or any real Zfh/Zvfh core. The conclusion 'full float16 ODT is possible on resource-constrained RISC-V single-core' therefore assumes that the simulator faithfully reproduces Zfh/Zvfh functional behavior and, where performance is implied, timing. The paper's own final paragraph acknowledges this ('validating the ODT pipeline through the RISC-V ISA Simulator'), but the abstract and conclusion do not. Please either validate at least the scalar Zfh path on the implemented NaxRiscv (e.g., on FPGA) and report measured runtime, or explicitly qualify the on-device claim as 'functionally validated on an ISA simulator; hardware validation pending.'
[§3.3, Fig. 4–5, Conclusion] The Zvfh support is at the design-discussion stage: no RTL implementation, synthesis, area, timing, or measured speedup is reported. The 'raw 4× speed-up over scalar execution' is a theoretical peak based on four lanes and VLEN=64. Consequently, the conclusion's phrase 'supporting standard extensions (i.e. Zfh and/or Zvfh)' overreaches for Zvfh, and the inclusion of Zvfh in the central claim is premature. The memory reduction and Zfh area results are unaffected, but Section 3.3 should be clearly labeled as an architecture proposal and the conclusion should state that Zvfh results are projected, not measured.

minor comments (6)

[Introduction] Typo: 'Multipliy-and-Accumulate' should be 'Multiply-and-Accumulate'.
[§3.1] Typo: 'seemlessly' should be 'seamlessly'.
[§2.2, Fig. 2] Fig. 2 caption says 'our RISC-V Zvfh optimized kernels', but the text only says experiments were run on a RISC-V ISA simulator. Please specify which simulator was used, whether Zvfh vector instructions were functionally simulated, and the NMSIS-DSP version, so that readers can reproduce the experiments.
[Table 2] The table lists dataset, learning rate, and optimizer but not the number of epochs, batch size, or dataset split for FashionMNIST. The MNIST experiments use 20 epochs and batch size 128; please state whether the same settings were used for all rows.
[Table 3] The notation 'Frozen layer id 1-2' is not defined; clarify that it means the first two layers are frozen. Also, the caption says the 'Gradients' column includes gradients, optimizer, and activation memory; please make explicit how activation memory scales with batch size for the reported numbers.
[§3.3] The phrase 'in a ad-hoc fashion' should be 'in an ad hoc manner'.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: derivation is empirical and self-contained, with no fitted parameters presented as predictions and no load-bearing self-citations.

full rationale

The paper's central claims are (i) float16-only ODT is feasible with minimal accuracy loss compared to float32, (ii) memory footprint is approximately halved, and (iii) enabling Zfh on NaxRiscv has low area cost, with a Zvfh architecture discussed but not yet implemented. None of these reduces to its own inputs by construction. The accuracy/loss results in Fig. 2 and Table 2 are direct measurements from training runs on a RISC-V ISA simulator, compared against a float32 baseline; no parameter is fitted to a subset of data and then renamed as a prediction. The ~50% memory reduction in Table 3 follows from the float16 format halving parameter and work-memory width, but the paper reports actual measured memory usage for concrete configurations rather than deriving a claimed predictive law from that definition; this is an intrinsic property of the data format, not a circular derivation. The Zfh area overhead (+1.15% LUT6, +0.05% FF, no frequency degradation) is an empirical synthesis result; the Zvfh discussion is explicitly an architectural proposal with future evaluation, so it is not dressed up as a validated prediction. References to AIfES, NMSIS-DSP, PULP-Trainlib, Vicuna2, Ara2, and similar works are external and not self-citations, and the paper does not invoke an author-derived uniqueness theorem or ansatz to force its choices. The main weakness is external-validation risk: the training evaluation is on an ISA simulator and the Zvfh hardware is unbuilt, so the 'on-device' claim is not yet silicon/FPGA-validated for the vector path. That is a correctness/evidence gap, not a circularity, and does not raise the circularity score.

Assumptions & free parameters 0 free parameters · 4 assumptions · 0 invented entities

The central claim rests on simulator fidelity, third-party kernel correctness, representativeness of the benchmark workloads, and generalizability of one synthesis result. There are no free parameters fitted to make the result work, and the proposed VPU is a hardware design, not a newly invented physical entity.

assumptions (4)

domain assumption RISC-V ISA simulator faithfully models IEEE 754 binary16 behavior and Zvfh vector semantics of the target core.
All training experiments are run on the simulator (§2.2); no measurement on actual hardware is reported.
domain assumption NMSIS-DSP float16 kernels are numerically correct and portable across Zvfh-compliant implementations.
The framework delegates math to NMSIS-DSP (§2.1) without independent verification of its kernels.
domain assumption A 5-layer MLP on MNIST/FashionMNIST is representative of the 'complete on-device training' workloads claimed.
No CNN, transformer, or real MCU workload is evaluated; the central claim generalizes from this single architecture (§2.2).
domain assumption The single Zfh synthesis result on a Xilinx XC7K325T is representative of the Zfh cost on other FPGA/ASIC targets.
Area overhead is reported for one configuration/target (§3.2).

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Cite this review

Pith. "Pith review of Hardware-Software Co-Design for Float16 On-Device Training on RISC-V Single-Core." pith.science (2026). https://pith.science/paper/MQZQNWFH

@misc{pith2026260721130,
  author       = {Pith},
  title        = {Pith review of: Hardware-Software Co-Design for Float16 On-Device Training on RISC-V Single-Core},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/MQZQNWFH}},
  note         = {Machine review of arXiv:2607.21130}
}

read the original abstract

By leveraging standard RISC-V extensions, namely Zfh (scalar float16) and Zvfh (vector float16), this work proposes an open-source framework to enable complete on-device training on resource-constrained RISC-V single-core. Our approach allows memory footprint reduction by about 50% as compared to using float32 and with minimal model performance degradation. We also facilitate transfer learning and fine-tuning scenarios by incorporating layer-freezing capabilities. Our work builds onto AIfES, an open-source, modular and generic DNN training and inference framework for embedded systems that can be extended with custom hardware-specific functions. The benefits of float16 is further emphasized by outlining the low area overhead of Zfh on a RV64GC super-scalar out-of-order FPGA softcore (+1.15% LUT6 and +0.05% FF at 175MHz). Finally, we discuss the architecture of a Zvfh implementation within the same RISC-V core.

Figures

Figures reproduced from arXiv: 2607.21130 by the authors.

**Figure 2.** Training a MLP from scratch on MNIST, on 20 epochs, using our RISC-V Zvfh optimized kernels (left) [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗

**Figure 3.** High-level overview of the NaxRiscv 3.2 Scalar float16 (Zfh) support In order to achieve full Zvfh compliance, a float16 capable FPU is needed. First, the FPU is an actual building block of a Zvfh-compatible VPU. Moreover, the Zvfh specification mandates full scalar float16 compatiblity, that is Zfh support. Therefore, we extended the NaxRiscv instructions decoder, LSU and FPU to accomodate the 36 Zfh instructions. … view at source ↗

Figures from the paper (2 more)

**Figure 4.** Figure 4: High-level overview of the VPU to be processed than the number of lanes, processed elements are held in a writeback register until the instruction fully completes. Finally, the full result is written back to the correct register file. As we mostly emphasize on vector f…

**Figure 5.** Figure 5: vrgather example when LMUL=4 enable float16 ODT at the hardware level. Future work will focus on evaluating the performance gains brought by vector kernels on our VPU-enhanced NaxRiscv FPGA target, to complement with current results focused on validating the ODT pipeli…

Discussion (0). Continue with ORCID to comment.

Reference graph

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Reviewed August 1, 2026 · model on record in the stance chip above.

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