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Paper Citation Record · LEDGER

Hardware-Software Co-Design for Float16 On-Device Training on RISC-V Single-Core

As of 8 August 2026, this Paper Citation Record lists 13 of 13 outbound references and 0 inbound Pith citation observations for arXiv:2607.21130.

A citation records a reference. It does not transfer a finding from one paper to another.

pith.paper-citation-record.v1
2607.21130 v1

Coverage vector

measured 13 of 13 reference resolution

Typed states for the displayed outbound observations.

Source: paper_references, paper_reference_links, observed 2026-08-01T08:24:26.702107Z

measured 13 of 13 standing notices

One-hop event checks from named stored sources.

Source: scholarly_work_events, retraction_status_cache, observed 2026-08-08T06:32:00.761636+00:00

measured 0 of 0 inbound itemization

Pith citing papers itemized under the disclosed page cap.

Source: paper_references, paper_reference_links

measured 0 of 1 external citation measurements

A source-named dated measurement, never combined with another source.

Source: cited_works

Reference resolution

13 of 13 outbound references displayed

  • verified exact0
  • verified fuzzy0
  • unresolved13
  • parse uncertain0
  • malformed identifier0
  • metadata mismatch0

External citation measurements

No source-named external measurement is stored.

Outbound references

Observation 77acf553-0c07-4043-a6c0-4d9a378f85c0 · outbound

This paper cites Advances in Neural Information Processing Systems33, 11285–11297 (2020).

Hardware-Software Co-Design for Float16 On-Device Training on RISC-V Single-Core Advances in Neural Information Processing Systems33, 11285–11297 (2020)

Reference 1

Resolution
unresolved
no resolver link, observed 2026-08-01T08:24:25.589576Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

source=pdf_text observed=2026-08-01T08:24:25.589576Z digest=sha256:1fb605880d66cbc7cd8b0615df00b5a8678192d04e8a9835a7e5e1f5af71fefd

Observation e7ca3dcc-950d-4b3b-9fe5-c0f0961e4745 · outbound

This paper cites IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2024).

Hardware-Software Co-Design for Float16 On-Device Training on RISC-V Single-Core IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2024)

Reference 2

Resolution
unresolved
no resolver link, observed 2026-08-01T08:24:25.664023Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

source=pdf_text observed=2026-08-01T08:24:25.664023Z digest=sha256:4bf8c7635f0db30da96543b1f41bf8bb9338d3677983b8a246d1bd1ef47f780e

Observation dcd80e8d-d8d6-4b08-bde6-e25824c5e446 · outbound

This paper cites Gemmini: Enabling Systematic Deep-Learning Architecture Evaluation via Full-Stack Integration.

Hardware-Software Co-Design for Float16 On-Device Training on RISC-V Single-Core Gemmini: Enabling Systematic Deep-Learning Architecture Evaluation via Full-Stack Integration

Reference 3

Resolution
unresolved
no resolver link, observed 2026-08-01T08:24:25.785147Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

source=pdf_text observed=2026-08-01T08:24:25.785147Z digest=sha256:684f2e3c88d962eb4c28aa3bf3b4ffbda2466daef108847fb969e63681b5d523

Observation 02db8147-1a9f-46cd-9948-322b6abbd122 · outbound

This paper cites 0: Risc-v embedded vector unit with half- precision floating-point support for tinyml.

Hardware-Software Co-Design for Float16 On-Device Training on RISC-V Single-Core 0: Risc-v embedded vector unit with half- precision floating-point support for tinyml

Reference 4

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unresolved
no resolver link, observed 2026-08-01T08:24:25.843006Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

source=pdf_text observed=2026-08-01T08:24:25.843006Z digest=sha256:d9abfbbde89e016c59902139ba00b1c3cc7e321097a2e2357b068d1d8e063178

Observation 95beccbf-ee0a-4d80-8740-6c1314a0d5c9 · outbound

This paper cites IEEE Transactions on Computers (2026).

Hardware-Software Co-Design for Float16 On-Device Training on RISC-V Single-Core IEEE Transactions on Computers (2026)

Reference 5

Resolution
unresolved
no resolver link, observed 2026-08-01T08:24:25.969813Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

source=pdf_text observed=2026-08-01T08:24:25.969813Z digest=sha256:a3fbe608808c4a93c80e59049c2abe850507e6f5f9e5c369fd4a88b0f581d811

Observation 9235a2dc-cb68-43d7-9b5c-67126fc03d33 · outbound

This paper cites In: Proceedings of the 21st ACM International Conference on Computing Frontiers: Workshops and Special Sessions.

Hardware-Software Co-Design for Float16 On-Device Training on RISC-V Single-Core In: Proceedings of the 21st ACM International Conference on Computing Frontiers: Workshops and Special Sessions

Reference 6

Resolution
unresolved
no resolver link, observed 2026-08-01T08:24:26.076205Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

source=pdf_text observed=2026-08-01T08:24:26.076205Z digest=sha256:ff8469fe6764776a5e658147a78a98c29c7568f9b6174673ed905b0c362b652a

Observation df53e150-2994-418e-bfd1-e4ea1bc85247 · outbound

This paper cites In: 2025 33rd Telecommunications Forum (TELFOR).

Hardware-Software Co-Design for Float16 On-Device Training on RISC-V Single-Core In: 2025 33rd Telecommunications Forum (TELFOR)

Reference 7

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unresolved
no resolver link, observed 2026-08-01T08:24:26.170403Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

source=pdf_text observed=2026-08-01T08:24:26.170403Z digest=sha256:7eb0bd7434d576ed9d613649d1d2eb86213f4b6a32efe4d9159a3f70015da983

Observation 63837ba8-de2e-473b-b6df-5d5c7f757386 · outbound

This paper cites In: International Conference on Embedded Computer Systems.

Hardware-Software Co-Design for Float16 On-Device Training on RISC-V Single-Core In: International Conference on Embedded Computer Systems

Reference 8

Resolution
unresolved
no resolver link, observed 2026-08-01T08:24:26.274454Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

source=pdf_text observed=2026-08-01T08:24:26.274454Z digest=sha256:b2c7554a2ea55dc7d1d0c5184a470bcdd26bfbc2cd4b7a22073e35a313a8cbd2

Observation 6053f72c-5bdb-4efb-a5c3-53b99c680fec · outbound

This paper cites In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS).

Hardware-Software Co-Design for Float16 On-Device Training on RISC-V Single-Core In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS)

Reference 9

Resolution
unresolved
no resolver link, observed 2026-08-01T08:24:26.359738Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

source=pdf_text observed=2026-08-01T08:24:26.359738Z digest=sha256:af4d4c38d52ee998aa84e03b1a75d4c7858be5a53f2d62196e38f63ad82d06f5

Observation 8a0c0847-791f-408f-be6a-d6a104fb0f31 · outbound

This paper cites IEEE Transactions on Computers73(7), 1822–1836 (2024).

Hardware-Software Co-Design for Float16 On-Device Training on RISC-V Single-Core IEEE Transactions on Computers73(7), 1822–1836 (2024)

Reference 10

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unresolved
no resolver link, observed 2026-08-01T08:24:26.435926Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

source=pdf_text observed=2026-08-01T08:24:26.435926Z digest=sha256:afd5040f6a22ceced739d33fc594dd4f42ff196fc0bfa49c8470fa2f5b9af37b

Observation baf9d085-bd8c-4197-ad4d-621c23ae9dc5 · outbound

This paper cites In: International Conference on Data Science and Artificial Intelligence.

Hardware-Software Co-Design for Float16 On-Device Training on RISC-V Single-Core In: International Conference on Data Science and Artificial Intelligence

Reference 11

Resolution
unresolved
no resolver link, observed 2026-08-01T08:24:26.544061Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

source=pdf_text observed=2026-08-01T08:24:26.544061Z digest=sha256:ad8cf59fe2154a05d427a8aaafcf18568382925fae46c07e2765bfebbaed5c88

Observation d2069f0b-888a-47ae-a437-8c263640a95d · outbound

This paper cites In: 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Hardware-Software Co-Design for Float16 On-Device Training on RISC-V Single-Core In: 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE)

Reference 12

Resolution
unresolved
no resolver link, observed 2026-08-01T08:24:26.620581Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

source=pdf_text observed=2026-08-01T08:24:26.620581Z digest=sha256:e6676adab632a37cb5f5bb14539e5e732d32acdcefca8ce25a08624bd40ad273

Observation 8de5e572-1ab9-457d-9b1b-bba3ff9a9cb9 · outbound

This paper cites IEEE Transactions on Pattern Analysis and Machine Intelligence46(6), 4519–4533 (2024) 7.

Hardware-Software Co-Design for Float16 On-Device Training on RISC-V Single-Core IEEE Transactions on Pattern Analysis and Machine Intelligence46(6), 4519–4533 (2024) 7

Reference 13

Resolution
unresolved
no resolver link, observed 2026-08-01T08:24:26.702107Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

source=pdf_text observed=2026-08-01T08:24:26.702107Z digest=sha256:da3987bf5fffcc8de4c735cf8c2070e5e84601a6cd6071cdcbb1eb700fb5c669

Pith citing papers

No inbound Pith citation observations are available.