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REVIEW 3 major objections 5 minor 53 references

Hardware-aware memory control and contraction-path index ordering let a sequential tensor decision-diagram simulator run structured circuits such as QFT to 100 qubits with bounded RAM.

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2026-07-31 21:46 UTC pith:NOEQBRZV

load-bearing objection Solid FTDD systems paper: fixed-RAM memory model plus Path ordering give real, topology-conditional wins (QFT-100, big speedups on structured nets); claims need to stay scoped. the 3 major comments →

arxiv 2607.27971 v1 pith:NOEQBRZV submitted 2026-07-30 cs.ET

Optimizing Memory Efficiency and Index Ordering to Simulate Quantum Circuits Using Tensor Decision Diagrams

Vicente L\'opez Oliva , Jos\'e Manuel Bad\'ia Contelles , Maria Isabel Castillo Catal\'an This is my paper
classification cs.ET
keywords tensor decision diagramsquantum circuit simulationmemory managementindex orderingtensor networksFTDDcontraction pathexact simulation
verification ladder T0 review T1 audit T2 compute T3 formal T4 reserved

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

Exact classical simulation of quantum circuits hits a wall when state vectors or intermediate tensors grow without bound. This paper rebuilds the Fast Tensor Decision Diagram (FTDD) engine so that its two core hash tables sit in a fixed, hardware-sized footprint, nodes are reference-tracked and recycled, and only deep enough operations are cached. It also adds Path, an index order driven by the planned contraction sequence, and compares it with alphanumeric naming and Reverse Cuthill–McKee. On regular circuits the redesigned engine keeps memory flat and finishes QFT at 100 qubits; on some topologies Path or RCM cuts runtime by more than an order of magnitude. The practical message is that hybrid tensor–decision-diagram simulation becomes usable at larger scale once memory growth is capped and the diagram’s variable order matches how the circuit is contracted.

Core claim

A fixed-footprint, lifecycle-tracked redesign of FTDD’s UniqueTable and ComputeTable, together with a contraction-path-guided index order (Path), bounds peak memory on structured workloads and can reduce simulation time by more than 10× relative to the original alphanumeric order, enabling stable exact simulation of circuits such as QFT up to 100 qubits on a single core.

What carries the argument

Path index ordering: a static linear order of tensor indices obtained by simulating the contraction path, ranking indices by first contraction step then last-seen step so that early-eliminated indices sit high in the decision diagram and obsolete structure can be pruned; combined with hardware-aware table sizing (UniqueTable ~2^N−1, ComputeTable ~2^{N−1}−1 chosen so both occupy ~1% of RAM) and strict node reference tracking.

Load-bearing premise

The claim that large-n simulation stays stable mainly holds for structured, regular circuits under the paper’s fixed protocol; on high-entanglement workloads the same strict tracking that saves memory can sharply raise runtime.

What would settle it

Run the same optimized FTDD binary on QFT and on a deep random or variational circuit family past 50–100 qubits with identical table policy and index order: if QFT memory stays flat near 13 GiB while the entangled family either exhausts RAM or times out far earlier, the topology-dependent scalability claim stands; if both blow up or both stay bounded equally, it fails.

Watch this falsifier — get emailed when new claim-graph text bears on it.

If this is right

  • Exact sequential DD–TN simulators can reach 100-qubit structured circuits (e.g. QFT) on a high-memory server without distributed state-vector infrastructure.
  • Index order should be chosen per topology: Path for QFT-like circuits, RCM for graph-like interaction patterns; no single static order wins everywhere.
  • Hybrid or static table sizing near 1% of host RAM is preferable to pure exponential growth once n exceeds ~30.
  • For regular linear circuits a simple sequential contraction plan can outperform an expensive offline path optimizer that itself may run out of memory.
  • Future work can remove the internal 100-qubit cap and train a selector that picks the best index order from circuit structure.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • An adaptive controller that switches among alphanumeric, RCM, and Path (and among sequential vs optimized contraction) using cheap topology features would likely dominate any fixed configuration on mixed workloads.
  • The same lifecycle and fixed-footprint discipline could transfer to other canonical DD packages used in quantum verification, not only FTDD.
  • Because Path aligns diagram levels with elimination time, it is a practical surrogate for minimizing linear rank-width without solving that NP-hard problem directly.
  • Reporting wall-clock that includes path-search cost would reverse some cotengra “wins” on intermediate circuits and sharpen when advanced planners are worth calling.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit.

Referee Report

3 major / 5 minor

Summary. The paper optimizes the FTDD hybrid TN+DD quantum-circuit simulator along two axes. First, it replaces unbounded dynamic allocation with a hardware-aware fixed-footprint memory model: explicit node lifecycle/reference tracking between UniqueTable and ComputeTable, node recycling, selective ComputeTable caching (depth threshold 3), and three table-sizing policies (fully exponential, hybrid exp-fixed, static fixed) sized to a fraction of host RAM. Second, it studies static index orderings for TDDs, introducing Path (Algorithm 1), a contraction-path-guided heuristic that sorts indices by first-contraction step and last-seen time, and compares it to alphanumeric naming and RCM on the index interaction graph. On an MQTBench suite under sequential and cotengra contraction, single-core runs, |0⟩ input and open outputs, the optimized engine keeps QFT/GHZ/Graph memory essentially flat out to 100 qubits (~13 GiB, ~26 s for QFT-100), while Path and RCM yield topology-dependent speedups (Path >13× on QFT-100, RCM >35× on Graph-50). High-entanglement circuits (RQC, QNN) show the complementary trade-off: large RAM reductions at the cost of higher time and Max-bck.

Significance. Exact classical simulation of structured circuits beyond the ~50-qubit state-vector wall remains practically important for algorithm validation. The work is solid systems engineering: reproducible code is linked, adverse regimes (time penalties, cotengra OOMs on regular nets, Max-bck inflation) are reported rather than hidden, and the Path heuristic plus the three table policies are concrete, falsifiable contributions. If the topology-conditional claims hold, the paper supplies a usable sequential baseline that can run QFT-scale workloads on a high-memory server and a clear empirical map of when advanced contraction/ordering pays off. Strengths include open code, systematic ablation of memory policies (Table 3), and explicit documentation of trade-offs rather than only best-case speedups.

major comments (3)
  1. [§1 Introduction; §7 Conclusions] Sections 1 and 7 (and parts of the abstract) over-claim relative to the measured evidence. The text asserts that the optimizations “allow the enhanced FTDD simulator to execute previously intractable deep and highly entangled quantum circuits” and position it “competitively against state-of-the-art parallel simulators… for specific circuit families.” Tables 1–2 and Figure 5 show the opposite on RQC/QNN/AE: memory falls but wall time and Max-bck rise sharply, and no head-to-head numbers versus parallel state-vector or TN codes are given. The abstract’s safer phrasing (“bounds memory… under structured quantum workloads”) should govern the introduction and conclusions; supercomputer competitiveness should be removed or supported by direct comparison.
  2. [§6.1; Table 2] Section 6.1 states that cotengra is given one hour offline (56 threads) and that this search time is excluded from the reported contraction times used for SpeedUp in Table 2. For intermediate circuits (QWalk, QNN, RA, QPE) the paper itself notes that sequential is preferable once search cost is counted. Either fold path-search wall time into the critical path for every cotengra entry, or clearly label Table 2 as “contraction-only” and revise the Regime-2/3 recommendations so they cannot be read as end-to-end wins.
  3. [§5.3 Algorithm 1; §6.4 Figure 5] The Path heuristic (Algorithm 1, §5.3) is evaluated only against a fixed precomputed contraction path (sequential or cotengra). Because Path’s primary key is FirstStep along that path, the reported >13× QFT speedup is path-dependent; a different plan can change both the order and the node counts. A short sensitivity check—Path under at least two distinct plans on the same circuit, or a brief comparison to a dynamic sifting baseline mentioned in §3.4—would make the ordering claim load-bearing rather than conditional on the plan already chosen for Table 2.
minor comments (5)
  1. [Table 1] Table 1 header and caption use “MeM (GiB)” / “Max bck” while the text uses “MeM” and “Max bck” inconsistently; standardize units and spell out “maximum bucket occupancy” once.
  2. [Figure 5] Figure 5 y-axis is log-scaled speedup but the caption does not state the baseline (alphanumeric + sequential) explicitly; add it.
  3. Typos and grammar: “kind og DD” (§3.4), “Order de non-free” (Alg. 1), “T opologies” with stray spaces (several places in §6.2), “further improving the detection of nodes structurally identical” (§3.3).
  4. [§6.1] The 100-qubit hard cap is attributed to “other internal data structures” (§6.1) but never identified; a one-sentence note on which structure imposes the limit would help readers interpret the † markers.
  5. [§5.3; §2] Related Work cites FeynmanDD [51] for linear rank-width after Path is introduced; a forward pointer in §5.3 would clarify priority and difference.

Circularity Check

0 steps flagged

No significant circularity: empirical systems optimizations and measured speedups, not definitional or fitted predictions.

full rationale

This paper is hardware-aware systems engineering on FTDD: a fixed-footprint memory model, node lifecycle tracking, table-sizing policies, and a Path index-order heuristic, all evaluated by wall-clock time, RSS, Max-bck, hit ratio, and node counts on MQTBench circuits under a stated protocol (single core, |0⟩, open outputs, sequential vs cotengra, two-hour limit). The headline results (bounded memory and stable QFT-100; Path/RCM order-of-magnitude speedups on some topologies) are read off experiments (Tables 1–3, Figure 5), not algebraic restatements of fitted parameters or uniqueness theorems. Prior self-citations (original FTDD [8], authors’ contraction study [48]) supply the baseline tool and motivation; they do not force the measured memory bounds or Path speedups. Path is explicitly a static heuristic guided by the contraction path (Algorithm 1), compared empirically to alphanumeric and RCM—not claimed as a first-principles derivation that reduces to its inputs. Topology-conditional caveats (RQC/QNN time penalty; cotengra OOM on regular nets) are reported openly and do not create circular reduction. No self-definitional loop, fitted-as-prediction, or load-bearing uniqueness import appears.

Axiom & Free-Parameter Ledger

4 free parameters · 5 axioms · 2 invented entities

Load-bearing content is engineering and experimental, not a formal derivation. The claim stack rests on standard TN/DD semantics, the existing FTDD architecture, chosen sizing/caching heuristics, and the benchmark protocol. No new physical entities; free parameters are implementation knobs (cache depth threshold, table fraction of RAM, growth caps).

free parameters (4)
  • ComputeTable caching depth threshold = 3
    Operations are cached only when combined DD depth exceeds a threshold; paper sets this to 3 without a sweep justifying optimality across circuits.
  • UniqueTable+ComputeTable RAM fraction / N = ~1% of host RAM
    Hardware-aware policy sizes tables so combined footprint is about 1% of system memory (UniqueTable 2^N-1, ComputeTable 2^{N-1}-1); 1% and the 2^x-1 form are design choices.
  • Exponential table growth cap n=30 = 30 qubits / 2^30-style bounds
    Fully exponential and hybrid policies cap exponential scaling at 30 qubits / 2^30-scale structures to avoid allocation blow-up; cap is administrative.
  • cotengra search budget = 1 hour, 56 threads, combo
    One hour wall-clock, combo minimization, 56 threads; path quality and OOM behavior depend on this budget, which is not part of the timed contraction in SpeedUp.
axioms (5)
  • domain assumption Exact quantum circuit simulation via tensor-network contraction with TDD/FTDD semantics (canonicity for a fixed index order π(I)).
    Sections 3.1–3.4 treat TN contraction and TDD canonicity as given from Markov–Shi, Hong et al., and FTDD.
  • domain assumption UniqueTable + ComputeTable hash-table architecture (FNV 32-bit, buckets of size 2^x-1) is the right substrate for node sharing and op caching.
    Section 3.3–4.5 inherits Brace/Bryant-style BDD packaging as used in FTDD.
  • ad hoc to paper Index order quality can be pursued with static heuristics (alphanumeric names, RCM on the index interaction graph, Path from a fixed contraction plan) without dynamic sifting during contraction.
    Section 5 restricts the study to three static orders; dynamic reordering is discussed only as related work.
  • domain assumption MQTBench circuits plus structural groupings (regular / algorithmic / high-entanglement) are representative enough to characterize topological trade-offs.
    Section 6.1 selects nine circuits from MQTBench using metrics from cited topology work.
  • standard math Standard facts of sparse matrix bandwidth reduction (RCM) and TN treewidth/cut-width intuition transfer to TDD node counts.
    Sections 5.2–5.3 invoke RCM and cut-width/pathwidth motivation, citing classical graph and recent FeynmanDD-style arguments.
invented entities (2)
  • Path index-ordering heuristic no independent evidence
    purpose: Static permutation of tensor indices from the contraction path (FirstStep, LastSeen) to improve TDD sharing and prune early-contracted indices.
    Introduced in Section 5.3 and Algorithm 1; evaluated only inside this FTDD fork. Independent evidence is the empirical speedups on held-out-style circuit families in Figure 5, not an external formal proof of optimality.
  • Hardware-aware fixed-footprint FTDD memory model (lifecycle tracking, node recycle, selective cache, table policies) no independent evidence
    purpose: Bound RAM growth and avoid dangling UniqueTable/ComputeTable references during contraction.
    Section 4 redesign; validated by Table 1–3 comparisons to the prior FTDD implementation on the authors’ stack.

pith-pipeline@v1.2.0-daily-grok45 · 26278 in / 3942 out tokens · 73373 ms · 2026-07-31T21:46:01.494257+00:00 · methodology

0 comments
read the original abstract

Combining Tensor Networks (TNs) and Decision Diagrams (DDs) provides a high-performance framework for the exact simulation of quantum circuits on classical computers by exploiting structural redundancies and topological entanglement. However, improving the scalability of hybrid tools such as the Fast Tensor Decision Diagram (FTDD) requires addressing strict memory growth constraints and complex node management during tensor contractions. In this paper, we propose a hardware-aware architectural optimization of the FTDD framework, with two main contributions: first, we overhaul the internal memory management through a fixed-footprint memory model, strict node lifecycle tracking, and a systematic evaluation of table-sizing policies (exponential, static, and hybrid) to reduce allocation overhead and control memory growth; second, we introduce Path, a new index-ordering heuristic guided by the contraction path, and conduct a comprehensive study of variable index-ordering strategies, an important factor for DD compression. By comparing the original alphanumeric ordering, RCM, and our Path heuristic across diverse circuit topologies, we show that index permutation strongly affects node sharing and diagram density. Experimental evaluation confirms that our optimized FTDD engine bounds memory consumption under structured quantum workloads, enabling stable execution of circuits such as QFT with up to 100 qubits. Furthermore, we systematically characterize execution time, memory footprint, and topological trade-offs across diverse quantum benchmarks.

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