Pith. sign in

REVIEW 4 major objections 5 minor 42 references

ArchAgent v2: A Case Study with the Data Prefetching Championship

T0 review · 4 major / 5 minor · reviewed 2026-08-11 · deepseek-v4-flash

Challenge this review Re-run · record.json Download PDF Read on arXiv ↗

Pith's one-line read ArchAgent v2 claims that an LLM-driven evolutionary search can automatically design a three-level data prefetcher that outperforms the winning hand-designed DPC4 solution, BertiGO, reporting a 3.8% geometric-mean IPC speedup over baseline…

desk verdict A credible, well-scoped demonstration that agentic search can beat a hand-designed prefetcher under DPC4 rules, but the hardware-realizability claim needs code release and a corrected storage table before the result can be fully trusted. read the letter →

arxiv 2608.09874 v1 pith:IFXDGLYU submitted 2026-08-10 cs.AI cs.AR

Abraham Gonzalez , Raghav Gupta , Akanksha Jain , Hanna Alam , Alexander Novikov , Po-Sen Huang , Matej Balog , Marvin Eisenberger
show 7 more authors
Sergey Shirobokov Ngân Vũ Hank Levy Borivoje Nikolić Sagar Karandikar Martin Dixon Parthasarathy Ranganathan
This is my paper · ORCID
classification cs.AIcs.AR
keywords dataprefetchingagenticAIevolutionarysearchLLMcodegenerationcacheprefetcherdesignhardware-realizabilityfeedbackmulti-levelDPC4
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper tries to establish that an LLM-driven evolutionary search can scale from single cache-replacement policies to a much harder three-level data prefetching problem, and that it can beat a hand-designed championship winner. It introduces two fixes for scaling: cascaded search, which evolves and freezes prefetchers one cache level at a time, and a hardware-realizability feedback loop, which rejects over-budget designs during evolution. Under the official DPC4 rules the discovered prefetcher achieves a 3.8% geometric mean IPC speedup over the baseline and a 0.3% edge over the prior champion BertiGO, with a larger 4.6% gain on low-bandwidth single-core configurations. The paper also profiles over 12,000 evaluated candidates to show how the agent's improvements arise from compositional architectural changes. If the claims hold, agentic search becomes a practical tool for microarchitecture discovery, with multi-core evolution remaining an open bottleneck.

What carries the argument

Two load-bearing mechanisms carry the argument. The first is a cascaded divide-and-conquer evolutionary search that subdivides the design space by sequentially evolving and freezing prefetchers at L1D, then L2, then LLC, before running global multi-level optimizations; this makes a non-monotonic, combinatorially large search tractable. The second is a hardware-realizability feedback loop built around a per-prefetcher prefetcher_size() function that reports the candidate's storage footprint, with over-budget designs rejected at compile time so the agent receives a negative reward for violating the 32 KB, 128 KB, and 256 KB budgets. The final policy itself is also a mechanism: it uses dynamically scaled prefetch lookahead, bandwidth throttling driven by core and memory signals, and an arbitrator that routes confident prefetches to L1D while diverting speculative ones to lower cache levels.

What would settle it

Re-run the L1D evolution with an independent static size auditor that computes each candidate's table sizes from the source code, or run every accepted candidate through a hardware synthesis and area-estimation tool; if any accepted candidate exceeds the 32 KB, 128 KB, or 256 KB budgets, the hardware-realizability feedback loop did not enforce the constraint it claims to enforce.

Watch

Extended reading notes

Core claim

The central claim is that a multi-level prefetcher can be discovered automatically, without hand-written architectural intuition, by an evolutionary LLM agent, and that the discovered policy beats the best human-designed policy in a controlled competition setting. The discovered policy combines an enhanced Berti-style L1D engine with global stride tracking, a global delta history table, and a reinforcement-learning arbitrator; an upgraded Pythia-style L2 engine with richer RL features, power-of-two stride actions, sum-pooling confidence thresholds, and bandwidth throttling; and an LLC engine that switches between regular stride generation and irregular history replay based on a sliding-window measure of access chaos. Storage stays within the DPC4 budgets at 31.1 KB for L1D, 110.0 KB for L2, and 230.3 KB for LLC. The authors report a 3.8% geometric mean IPC speedup over the baseline and a 0.3% overall improvement over BertiGO, with the biggest margin in low-bandwidth single-core configurations (4.6% versus 2.6% for BertiGO), at the cost of roughly 1.5% in multi-core performance.

Load-bearing premise

The storage-budget guarantee rests on the assumption that the prefetcher_size() functions written by the LLM truthfully report physical storage for every candidate, because only the final output was manually checked; if intermediate designs under-report, an over-budget candidate could pass the realizability filter.

Editorial extensions

If this is right

  • Automated agentic search can produce competition-winning microarchitecture policies, not just single-component tweaks: the discovered three-level policy beats the prior hand-designed champion in the same evaluation harness.
  • Cascaded evolution, optimizing and freezing one cache level at a time, is a viable decomposition for multi-level designs where simultaneous search is slow and non-monotonic.
  • Embedding a storage-budget check into the compile-and-evaluate loop gives LLM optimizers a hard, per-candidate realizability signal, and the same pattern can be reused for any hardware policy with countable state.
  • The pipeline should improve as the underlying LLMs improve; the authors expect more reasoning and context to yield larger gains more rapidly and with better efficiency.
  • Multi-core prefetching remains the limiting frontier: the discovered policy loses about 1.5% to BertiGO on multi-core mixes, and simulation latency continues to impede evolution speed.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • Editorial inference: the single-core-first cascade likely explains the multi-core regression, because optimization pressure was weighted toward low-bandwidth single-core as a proxy and multi-core feedback entered only at the final stage; a cascade that front-loads contention-aware workloads might close that gap.
  • Editorial inference: the storage-budget guarantee depends on the LLM's own size reports, so an independent static analyzer or synthesis-based area estimator would make the realizability claim airtight and would be a natural extension of the method.
  • Editorial inference: the roughly fifty-percent discard rate among 12,000 candidates, combined with the flat average proposal quality over time, suggests that better mutation and selection priors could cut simulation cost while preserving the rare high-value architectural jumps.
  • Editorial inference: the same cascade-plus-budget-feedback architecture could generalize to other multi-level or multi-component hardware search problems, such as co-designing cache replacement with prefetching or searching across different cache hierarchy configurations.
Share X Bluesky LinkedIn Reddit HN

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

4 major / 5 minor

Summary. The paper presents ArchAgent v2, an extension of an LLM-based evolutionary search system for hardware prefetcher design. It adds a cascaded search that evolves L1D, L2, and LLC prefetchers in stages and a storage-size feedback loop that rejects candidate policies whose LLM-written prefetcher_size() exceeds DPC4 budgets. Using ChampSim on DPC4 traces, the authors report a 3.8% geometric-mean IPC improvement over the baseline and a 0.3% improvement over BertiGO, with larger gains on low-bandwidth single-core workloads. The paper also profiles one L1D evolution of over 12,000 candidates.

Significance. If the reported results are reproducible, the paper is a significant demonstration that automated evolutionary agents can navigate a multi-level hardware design space and produce a competitive prefetcher under external competition conditions. The comparison against DPC4 baselines, the separate training and validation traces, and the large candidate corpus are strengths, as is the staged cascade methodology. However, the hardware-realizability claim is not yet independently auditable because the code is not released and the storage accounting contains an arithmetic error; these points are load-bearing for the headline result.

major comments (4)
  1. [Section III.A / Table II] The L2 Q-Value Store row in Table II reports '5fts.×18acts.×16b' as 99.0 KB, but those factors multiply to 180 bytes; reproducing 99.0 KB requires an unstated dimension such as roughly 2,816 entries per feature. Since Section III.A makes the LLM-written prefetcher_size() the only per-candidate enforcement of the 128 KB L2 budget, this discrepancy casts doubt on the reported 110.0 KB L2 total and on the competition-legal status of the final design. Please correct the table, state the exact dimensions of every structure, and provide the final prefetcher_size() accounting so the budget can be verified independently.
  2. [Section III.A] The paper states that prefetcher_size() functions were written by the LLM, kept synchronized by offline LLM judges, and manually checked only on the final output. This means intermediate candidates that under-report their physical storage would not actually be rejected by the budget check, and because no code is released, even the final candidate's sizes cannot be audited from the manuscript. I ask the authors to release the final L1D/L2/LLC prefetcher code and the size-accounting functions, or to provide an independent tabulation of the physical storage for all final components.
  3. [Section III.C] The validation protocol is underspecified. The text says candidates were evolved on reduced-length traces and final selections were validated on the championship evaluation set, but it does not say whether the validation set was ever used to choose among finalists or to influence lineage decisions, nor how many times finalists were evaluated on it. To support the claim of beating BertiGO under DPC4 rules, please specify the selection protocol and, if available, report results on the official DPC4 hidden evaluation set.
  4. [Section IV.B / Figure 8] The 0.3% overall improvement over BertiGO is an aggregate of configurations, and the paper does not state the official DPC4 scoring formula or show how the overall geomean is computed. Because the policy loses on multi-core (about -1.5% versus BertiGO) and wins on single-core, the aggregate claim depends on the exact configuration weights. Please state the scoring formula and give per-component and per-workload results for the Overall row.
minor comments (5)
  1. [Figure 8] The y-axis label 'Geomean IPC Normalized to Berti@L1D/Pythia@L2' is ambiguous; please specify whether the normalization is the per-workload geomean of IPC ratios or the geomean of normalized IPC values for each configuration.
  2. [Table II] The abbreviations '5fts.' and '18acts.' are not defined in the table or text, and the reader cannot map them to concrete C++ types or hardware storage entries; please clarify the notation.
  3. [Section IV.B] The text says 'we see a 3.8% performance uplift ... winning the competition,' but the paper does not cite official DPC4 standings; please provide the official results or clarify that this is the authors' evaluation of their submission.
  4. [Abstract and Section IV.B] The abstract says '3.8% geometric mean IPC speedup' while Section IV.B says '3.8% performance uplift'; please be consistent about the baseline and about whether 'overall' includes multi-core configurations.
  5. [Figures 9 and 10] The captions of Figures 9 and 10 should explicitly state the difference between normalized IPC and harmonic IPC so the two figures are not mistaken for the same metric.

Circularity Check

0 steps flagged · score 1.0 of 10

No circular derivation: the performance claim is an externally measured search result; the self-reported storage-size check is an auditability concern, not a circular step.

full rationale

The paper's central claim, that ArchAgent v2 discovers a three-level prefetcher beating BertiGO, is an empirical, externally benchmarked result rather than a derivation from its own assumptions. The search is run on DPC4 training traces and the final policy is evaluated on a separate, longer, held-out validation set, with IPC measured by ChampSim against competition baselines (Berti/Pythia and BertiGO) that are not products of this paper. Nothing in the paper defines the predicted IPC in terms of the fitness function or the LLM prompts; the speedup is an output of simulation. The only self-referential element is the storage-enforcement mechanism in Section III.A: the LLM-written prefetcher_size() function is self-reported, with manual checking only on the final output, and the evolved code is not released. This is an auditability and hardware-realizability risk, especially given Table II's L2 'Q-Value Store' row, which lists '5fts. x 18acts. x 16b' as 99.0 KB when those factors multiply to 180 bytes. However, this is not a circular step: the performance comparison is not constructed from the size function, and there is no equation in which the claimed result equals its own input. Self-citations to ArchAgent [16] and AlphaEvolve [28] describe the harness used; they do not carry the performance proof. I therefore find no significant circularity; the modest score reflects minor self-reliance in the framework, not a circular derivation.

Assumptions & free parameters 3 free parameters · 4 assumptions · 0 invented entities

The central empirical claim rests on the ChampSim evaluation setup, the DPC4 traces and scoring rule, the integrity of the LLM-reported storage sizes, and the heuristic cascade decomposition. No new physical entities are introduced; the discovered prefetcher components are algorithmic structures composed from known building blocks.

free parameters (3)
  • Evolution-selected prefetcher hyperparameters = Not individually listed; storage totals in Table II are 31.1 KB L1D, 110.0 KB L2, 230.3 KB LLC
    The evolved policies contain many thresholds, table sizes, lookahead depths, and arbiter weights tuned on DPC4 training workloads by the evolutionary loop; these are fitted to the training traces.
  • Low-bandwidth weighting in single-core evolution = geomean(lowBW, lowBW, highBW)
    Section III.B.2 states the single-core cross-prefetcher optimization double-weighted the low-bandwidth configuration as a proxy for multi-core; this hand-chosen weighting shapes the final policy and its multi-core behavior.
  • Simulation lengths for evolution and validation = 60M/15M warmup (single-core training), 200M/50M (validation); 12.5M/5M and 50M/20M for multi-core
    Table I; these are pragmatic cutoffs chosen by the authors, affecting which behaviors are optimized.
assumptions (4)
  • domain assumption ChampSim simulation results accurately predict the relative performance of prefetching policies on target hardware.
    The entire evaluation is based on ChampSim IPC; the paper cites the simulator's use in DPC4 but provides no validation of ChampSim against real hardware.
  • domain assumption The official DPC4 training and held-out validation traces are representative, and geometric mean IPC is the correct competition objective.
    Evaluation and selection follow DPC4 rules (Section II.C, III.C); the paper does not justify the metric beyond competition convention.
  • domain assumption The LLM-written prefetcher_size() function accurately accounts for physical storage, and offline LLM judges keep it synchronized with the implementation.
    Section III.A: storage enforcement relies on the LLM updating both logic and size functions; only the final output received a manual size check, so this accuracy is assumed throughout evolution.
  • ad hoc to paper Cascaded stage ordering (L1D then L2 then LLC, with later global optimization) does not badly compromise the final design's quality.
    Section III.B: the cascade freezes lower-level prefetchers while evolving higher levels, an author-chosen decomposition that is not proven near-optimal; the paper acknowledges this ordering prioritized single-core performance and contributed to multi-core losses.

how reviews work

0 comments
Cite this review

Pith. "Pith review of ArchAgent v2: A Case Study with the Data Prefetching Championship." pith.science (2026). https://pith.science/paper/IFXDGLYU

@misc{pith2026260809874,
  author       = {Pith},
  title        = {Pith review of: ArchAgent v2: A Case Study with the Data Prefetching Championship},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/IFXDGLYU}},
  note         = {Machine review of arXiv:2608.09874}
}
read the original abstract

Agentic artificial intelligence has shown great promise in automating algorithm design, but scaling similar techniques to computer microarchitecture discovery remains challenging due to vast search spaces, strict hardware budgets, and long simulation times. In this work, we present ArchAgent v2, a framework which scales automated microarchitecture search to multi-level data prefetching. While the original ArchAgent successfully discovered single-level cache replacement policies in competition settings, it does not scale to multi-level prefetching where the design space and degrees of freedom are larger. To overcome this, we introduce two new additions to ArchAgent: a cascaded evolutionary search that subdivides the design space by sequentially evolving and freezing prefetchers at individual cache levels, and a hardware-realizability feedback loop that embeds real-time size-estimation directly into the evolution process. Evaluated under identical rules of the 4th Data Prefetching Championship (DPC4), ArchAgent v2 automatically designs a three-level prefetcher that outperforms the winning hand-designed solution, further demonstrating automated agentic discovery as a useful tool for computer architects. Our discovered policy achieves a 3.8\% geometric mean IPC speedup over the baseline overall and a 0.3\% improvement over the prior champion, BertiGO. On low-bandwidth single-core configurations, our policy yields a 4.6\% performance speedup compared to only 2.6\% for BertiGO. However, multi-core evolution still remains a significant challenge due to simulation latency impeding evolution speed. Finally, our profiling of an ArchAgent evolution of over 12,000 candidate designs provides key insights into how automated evolutionary agents explore and synthesize complex microarchitectural logic.

Figures

Figures reproduced from arXiv: 2608.09874 by the authors.

Figure 1
Figure 1. Cascaded divide-and-conquer evolutionary search. [PITH_FULL_IMAGE:figures/full_fig_p001_1.png] view at source ↗
Figure 2
Figure 2. Recap overview of the ArchAgent system. II. BACKGROUND In this section, we first review the general architecture of agentic LLM-based discovery systems. We then discuss the original ArchAgent [16] design, as shown in [PITH_FULL_IMAGE:figures/full_fig_p002_2.png] view at source ↗
Figure 3
Figure 3. Example storage budget restriction prompt. [PITH_FULL_IMAGE:figures/full_fig_p003_3.png] view at source ↗
Figures from the paper (10 more)
Figure 4
Figure 4. Figure 4: Evolutionary search “cascade” methodology. [PITH_FULL_IMAGE:figures/full_fig_p004_4.png]
Figure 5
Figure 5. Figure 5: High-level overview of the L1 modifications. Dotted [PITH_FULL_IMAGE:figures/full_fig_p005_5.png]
Figure 7
Figure 7. Figure 7: High-level overview of the LLC modifications. Dotted [PITH_FULL_IMAGE:figures/full_fig_p006_7.png]
Figure 8
Figure 8. Figure 8: ArchAgent’s policy compared against the baseline/SoTA prefetchers (i.e., EDP [27], Global Berti [32], and BertiGO [37]). [PITH_FULL_IMAGE:figures/full_fig_p007_8.png]
Figure 9
Figure 9. Figure 9: ArchAgent’s policy measured across distinct workload suites and single-core ChampSim championship configurations. [PITH_FULL_IMAGE:figures/full_fig_p007_9.png]
Figure 10
Figure 10. Figure 10: ArchAgent’s policy measured across distinct workload suites using the multi-core ChampSim championship configuration. [PITH_FULL_IMAGE:figures/full_fig_p007_10.png]
Figure 11
Figure 11. Figure 11: Success and failure of evaluated ideas. 0 5 10 15 20 25 30 35 40 Elapsed Days 0.6 0.7 0.8 0.9 1.0 Geomean IPC Normalized to Berti@L1D/Pythia@L2 Best Binned Min Binned Median Binned Average Min Trend Median Trend Average Trend Relative Score Frequency (Weighted by Volu…
Figure 12
Figure 12. Figure 12: Score and heatmap over time. evolution, ideas were equally split amongst these two categories. Given the scale of the evolution, we conclude that ArchAgent could, in parallel, iterate through many more ideas than a human could. However, the large failure rate also poi…
Figure 13
Figure 13. Figure 13: Annotated main lineage. • Named “Resonance Aware Dynamic Arbitrator”, this parent provided the highest performance boost (over 4.5% IPC boost over the main lineage’s parent). This change combined prior ideas on global stride and temporal predictors, checking if predic…
Figure 14
Figure 14. Figure 14: Where ideas are distributed throughout the evolution. [PITH_FULL_IMAGE:figures/full_fig_p011_14.png]

Discussion (0). Continue with ORCID to comment.

Reference graph

Works this paper leans on

42 extracted references · 28 canonical work pages

  1. [1]

    Alameldeen and S

    A. Alameldeen and S. Pugsley. [Online]. Available: https://dpc3.compas. cs.stonybrook.edu/

    work page

  2. [2]

    The first jilp data prefetching championship (dpc-1)

    A. R. Alameldeen and E. Rotenberg, “The first jilp data prefetching championship (dpc-1).” [Online]. Available: https://jilp.org/dpc/

    work page

  3. [3]

    ArchAgent: Agentic AI-driven computer architecture discovery,

    Anonymous, “ArchAgent: Agentic AI-driven computer architecture discovery,” OpenReview Anonymous Preprint, 2025, submission Number

    work page 2025

  4. [4]

    [Online]

    Anthropic. [Online]. Available: https://claude.com/product/claude-code

    work page

  5. [5]

    Mlarchsys 2026 home

    B. Asgari, T. D. Doudali, Q. Huang, A. Jain, G. Jeong, T. St. John, P. Panda, S. Pandey, S. Subramanian, N. J. Yadwadkar, and A. Yazdanbakhsh, “Mlarchsys 2026 home.” [Online]. Available: https://sites.google.com/corp/view/mlarchsys

    work page 2026

  6. [6]

    R. Bera, K. Kanellopoulos, and O. Mutlu, “Home.” [Online]. Available: https://sites.google.com/corp/view/dpc4-2026/home?authuser=0

    work page 2026

  7. [7]

    Pythia: A customizable hardware prefetching framework using online reinforcement learning,

    R. Bera, K. Kanellopoulos, A. Nori, T. Shahroodi, S. Subramoney, and O. Mutlu, “Pythia: A customizable hardware prefetching framework using online reinforcement learning,” inMICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021, pp. 1121–1137

    work page 2021

  8. [8]

    Agentic architect: An agentic ai framework for architecture design exploration and optimization,

    A. Blasberg, V . Kypriotis, and D. Skarlatos, “Agentic architect: An agentic ai framework for architecture design exploration and optimization,”arXiv preprint arXiv:2604.25083, 2026

    arXiv 2026

Show all 42 references
  1. [9]

    Micro-mama: Multi-agent reinforcement learning for multicore prefetching,

    C. Block, G. Gerogiannis, and J. Torrellas, “Micro-mama: Multi-agent reinforcement learning for multicore prefetching,” inProceedings of the 58th IEEE/ACM International Symposium on Microarchitecture, ser. MICRO ’25. New York, NY , USA: Association for Computing Machinery, 202...

    2025

  2. [10]

    Why do multi-agent llm systems fail?

    M. Cemri, M. Z. Pan, S. Yang, L. A. Agrawal, B. Chopra, R. Tiwari, K. Keutzer, A. Parameswaran, D. Klein, K. Ramchandranet al., “Why do multi-agent llm systems fail?”Advances in Neural Information Processing Systems, vol. 38, 2026

    2026

  3. [11]

    Barbarians at the gate: How ai is upending systems research,

    A. Cheng, S. Liu, M. Pan, Z. Li, B. Wang, A. Krentsel, T. Xia, M. Cemri, J. Park, S. Yang, J. Chen, L. Agrawal, A. Desai, J. Xing, K. Sen, M. Zaharia, and I. Stoica, “Barbarians at the gate: How ai is upending systems research,”arXiv preprint arXiv:2510.06189, 2025. [Online]. ...

  4. [12]

    Chia: An open-source framework for principled, agentic ai-driven hardware/software co-design research,

    A. Cui, F. Hermida-Rivera, J. Toubes, R. Gupta, J. Fang, C. L. Zhang, E. Schwarz, J. Kim, Y . S. Shao, B. Nikolic, C. W. Fletcher, and S. Karandikar, “Chia: An open-source framework for principled, agentic ai-driven hardware/software co-design research,” 2026. [Online]. Availa...

    2026 arXiv

  5. [13]

    The championship simulator: Architectural sim- ulation for education and competition,

    N. Gober, G. Chacon, L. Wang, P. V . Gratz, D. A. Jimenez, E. Teran, S. Pugsley, and J. Kim, “The championship simulator: Architectural sim- ulation for education and competition,”arXiv preprint arXiv:2210.14324, 2022

    2022 arXiv

  6. [14]

    [Online]

    Google. [Online]. Available: https://antigravity.google/

  7. [15]

    Google workload traces version 2,

    ——, “Google workload traces version 2,” https://console.cloud.google. com/storage/browser/external-traces-v2, accessed: 2025-11-13

    2025

  8. [16]

    Archagent: Agentic ai-driven computer architecture discovery,

    R. Gupta, A. Jain, A. Gonzalez, A. Novikov, P.-S. Huang, M. Balog, M. Eisenberger, S. Shirobokov, N. V ˜u, M. Dixonet al., “Archagent: Agentic ai-driven computer architecture discovery,”arXiv preprint arXiv:2602.22425, 2026

    2026

  9. [17]

    Glia: A human-inspired ai for automated systems design and optimization,

    P. Hamadanian, P. Karimi, A. Nasr-Esfahany, K. Noorbakhsh, J. Chandler, A. ParandehGheibi, M. Alizadeh, and H. Balakrishnan, “Glia: A human-inspired ai for automated systems design and optimization,”

  10. [18]

    [Online]

    Hparch. [Online]. Available: https://comparch-conf.gatech.edu/dpc2/

  11. [19]

    Linearizing irregular memory accesses for improved correlated prefetching,

    A. Jain and C. Lin, “Linearizing irregular memory accesses for improved correlated prefetching,” inProceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, ser. MICRO-46. New York, NY , USA: Association for Computing Machinery, 2013, p. 247–259. [O...

    2013

  12. [20]

    Improving coherence and persistence in agentic ai for system optimization,

    P. Karimi, K. Noorbakhsh, M. Alizadeh, and H. Balakrishnan, “Improving coherence and persistence in agentic ai for system optimization,” 2026. [Online]. Available: https://arxiv.org/abs/2603.21321 11

    2026

  13. [21]

    Shinkaevolve: Towards open-ended and sample-efficient program evolution,

    R. T. Lange, Y . Imajuku, and E. Cetin, “Shinkaevolve: Towards open-ended and sample-efficient program evolution,”arXiv preprint arXiv:2509.19349, 2025

    2025 arXiv

  14. [22]

    Skydiscover: A flexible, adaptive framework for ai-driven scientific and algorithmic discovery,

    S. Liu, M. Cemri, S. Agarwal, A. Krentsel, A. Naren, Q. Mang, Z. Li, A. Gupta, M. Maheswaran, A. Chenget al., “Skydiscover: A flexible, adaptive framework for ai-driven scientific and algorithmic discovery,” in Proceedings of the ACM Conference on AI and Agentic Systems, 2026,...

    2026

  15. [23]

    Scientistone: Towards human-level autonomous research via chain-of-evidence,

    R. Meng, B. Dalvi Mishra, J. Chen, C.-L. Li, P. Goyal, M. Parmar, Y . Song, Y . Song, R. Sinha, P. Ranganathan, B. Gokturk, J. Yoon, and T. Pfister, “Scientistone: Towards human-level autonomous research via chain-of-evidence,”arXiv preprint, 2026

    2026

  16. [24]

    Ieee international conference on llm-aided design, 2026

    A. Mirhosseini and Y . Liu, “Ieee international conference on llm-aided design, 2026.” [Online]. Available: https://iclad.ai/

    2026

  17. [25]

    Illuminating search spaces by mapping elites,

    J.-B. Mouret and J. Clune, “Illuminating search spaces by mapping elites,” 2015. [Online]. Available: https://arxiv.org/abs/1504.04909

    2015 arXiv

  18. [26]

    Berti: an accurate local-delta data prefetcher,

    A. Navarro-Torres, B. Panda, J. Alastruey-Bened ´e, P. Ib ´a˜nez, V . Vi˜nals- Y´ufera, and A. Ros, “Berti: an accurate local-delta data prefetcher,” in 2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO). IEEE, 2022, pp. 975–991

    2022

  19. [27]

    The entangling data prefetcher,

    A. Navarro-Torres, S. Singh, B. Panda, and A. Ros, “The entangling data prefetcher,”4th Data Prefetching Championship, Feb. 2026

    2026

  20. [28]

    Alphaevolve: A coding agent for scientific and algorithmic discovery,

    A. Novikov, N. V ˜u, M. Eisenberger, E. Dupont, P.-S. Huang, A. Z. Wagner, S. Shirobokov, B. Kozlovskii, F. J. R. Ruiz, A. Mehrabian, M. P. Kumar, A. See, S. Chaudhuri, G. Holland, A. Davies, S. Nowozin, P. Kohli, and M. Balog, “Alphaevolve: A coding agent for scientific and a...

    2025 arXiv

  21. [29]

    [Online]

    OpenAI. [Online]. Available: https://chatgpt.com/codex/

  22. [30]

    Semantic locality and context-based prefetching using reinforcement learning,

    L. Peled, S. Mannor, U. Weiser, and Y . Etsion, “Semantic locality and context-based prefetching using reinforcement learning,” in Proceedings of the 42nd Annual International Symposium on Computer Architecture, ser. ISCA ’15. New York, NY , USA: Association for Computing Mach...

    2015

  23. [31]

    What do evolutionary coding agents evolve?

    N. Pelleriti, S. H. Nelaturu, Z. Zhou, Z. Li, M. Zimmer, B. Han, and S. Pokutta, “What do evolutionary coding agents evolve?” 2026. [Online]. Available: https://arxiv.org/abs/2605.20086

    2026 arXiv

  24. [32]

    Global berti: Simultaneous streaming and spatial prefetching,

    G. Posluns and M. C. Jeffrey, “Global berti: Simultaneous streaming and spatial prefetching,”4th Data Prefetching Championship, Feb. 2026

    2026

  25. [33]

    Mathematical discoveries from program search with large language models

    B. Romera-Paredes, M. Barekatain, A. Novikov, M. Balog, M. P. Kumar, E. Dupont, F. J. R. Ruiz, J. S. Ellenberg, P. Wang, O. Fawzi, P. Kohli, and A. Fawzi, “Mathematical discoveries from program search with large language models.”Nat., vol. 625, no. 7995, pp. 468–475, January 2...

    2024

  26. [34]

    Computer architecture’s alphazero moment: Automated discovery in an encircled world,

    K. Sankaralingam, “Computer architecture’s alphazero moment: Automated discovery in an encircled world,” 2026. [Online]. Available: https://arxiv.org/abs/2604.03312

    2026 arXiv

  27. [35]

    Openevolve: an open-source evolutionary cod- ing agent,

    A. Sharma, “Openevolve: an open-source evolutionary cod- ing agent,” 2025. [Online]. Available: https://github.com/ algorithmicsuperintelligence/openevolve

    2025

  28. [36]

    Coordinated reinforcement learning prefetching architecture for multicore systems,

    M. H. Siddiqui, F. Guzman, Y . Wu, and R. Ann, “Coordinated reinforcement learning prefetching architecture for multicore systems,”

  29. [37]

    Pushing the limits of the berti prefetcher,

    S. Singh, A. Torres, and A. Ros, “Pushing the limits of the berti prefetcher,” 4th Data Prefetching Championship (DPC4), 2026

    2026

  30. [38]

    Opencode: The open-source ai coding agent,

    SST and OpenCode Contributors, “Opencode: The open-source ai coding agent,” 2026, accessed: 2026-07-31. [Online]. Available: https://github.com/anomalyco/opencode

    2026

  31. [39]

    Tanese,Distributed genetic algorithms for function optimization

    R. Tanese,Distributed genetic algorithms for function optimization. University of Michigan, 1989. 12

    1989

  32. [714]

    Available: https://openreview.net/forum?id=hcxN9l6zqZ

    [Online]. Available: https://openreview.net/forum?id=hcxN9l6zqZ

  33. [2025]

    Available: https://arxiv.org/abs/2509.10719

    [Online]. Available: https://arxiv.org/abs/2509.10719

    arXiv

  34. [2026]

    Available: https://arxiv.org/abs/2510.27176

    [Online]. Available: https://arxiv.org/abs/2510.27176

    arXiv

Pith tools

Reviewed August 11, 2026 · model on record in the stance chip above.