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Witnessing the architecture of quantum circuits

T0 review · 3 major / 5 minor · reviewed 2026-08-15 · deepseek-v4-flash

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Pith's one-line read The paper claims that compatibility of a unitary with a circuit architecture can be certified by a fidelity optimization: when the relaxed optimum is below one, a witness operator proves the architecture cannot realize the target.

desk verdict A genuinely new witness framework with a clean analytical core, but the Clifford LP rests on an unproven diagonalisation step and the numerical certificates need reproducible support before the strongest claims hold. read the letter →

arxiv 2608.13169 v1 pith:5RDYNNCA submitted 2026-08-13 quant-ph

Raphaël Mothe , Otfried Gühne This is my paper · ORCID
classification quant-ph PACS 03.67.-a03.67.Lx03.67.Mn
keywords quantumcircuitarchitecturewitnessesChoistatefidelityCliffordunitariesstabiliserformalismlinearprogramrelaxationsemidefiniteToffoligatedepth
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper introduces a way to prove that a given quantum unitary cannot be implemented within a prescribed circuit architecture, such as a fixed ordering of two-qubit gates on a chip. The method defines a fidelity between the target unitary and the best circuit of the allowed architecture, then relaxes the optimization: when the relaxed upper bound is below one, a constructed witness operator certifies incompatibility. For Clifford targets the semidefinite relaxation becomes a linear program, and for staircase architectures the authors derive analytical bounds by counting Bell pairs. These certificates give quantitative lower bounds on gate count and circuit depth, and they give experiments a threshold: seeing a fidelity above it certifies that the implemented device went beyond the tested architecture.

What carries the argument

The central object is the optimised Choi-state fidelity $\alpha_\Gamma(U)$, the maximum overlap between the Choi vector of the target unitary and the Choi vector of circuits built from the allowed gates, normalised so that value $1$ means the target is realisable. Because the exact maximisation is non-convex, the machinery is a two-stage relaxation: a semidefinite program over a positive operator $\tau$ with PPT and CPTP-marginal constraints for general targets, and a linear program for Clifford targets obtained by writing the Choi state as a graph state and restricting, without loss of generality, to operators diagonal in the graph-state basis. The analytical variant counts the number of Bell pairs that cross the cut between the last gate and the rest of the circuit; each such pair contributes a factor at most $1/2$, yielding bounds such as $1/4$ for SWAP staircases of arbitrary length.

What would settle it

Run a high-precision numerical search over feasible circuits for one of the reported examples, such as the five-gate Clifford pair or the Toffoli two-gate bounds; the paper's see-saw checks reach the claimed bounds up to $10^{-5}$ or $10^{-6}$, so any feasible circuit found with fidelity above the claimed upper bound beyond that tolerance would refute the method, while reaching it closely supports the claim.

Watch

Extended reading notes

Core claim

The central claim is that $\alpha_\Gamma(U)$, the maximum fidelity between the Choi state of $U$ and the Choi states of circuits compatible with architecture $\Gamma$, can be bounded from above by a convex relaxation, and whenever that upper bound is strictly below $1$ the operator $W=\alpha_\Gamma(U)\mathbb{1}-\tfrac18|U\rangle\rangle\langle\langle U|$ is a valid circuit-architecture witness. For arbitrary targets the relaxation is a semidefinite program over a positive operator $\tau$ with PPT and CPTP-marginal constraints. For Clifford targets, the stabiliser formalism identifies the relevant Choi state with a graph state, and a depolarisation step lets the authors restrict to graph-diagonal $\tau$, reducing the SDP to a linear program. The paper proves, among other examples, that the Toffoli gate is incompatible with every three-qubit architecture made of two two-qubit gates (depth at least $3$) and with every one made of three such gates (depth at least $4$), and that a five-gate Clifford circuit is incompatible with the mirrored five-gate architecture at tight fidelity $0.5$. The analytical Bell-pair technique is demonstrated for staircase architectures with no-signalling relations between inputs and outputs, and the authors leave the generalization to arbitrary architectures as work in progress.

Load-bearing premise

The load-bearing premise, made in the paper's Appendix C2, is that for Clifford targets an optimisation variable can be restricted to its diagonal part in a basis built from the target's graph state without changing the optimum; if that reduction failed, the linear-program upper bounds would cease to be valid upper bounds.

Editorial extensions

If this is right

  • The Toffoli gate cannot be implemented with two two-qubit gates on three qubits, so its circuit depth is at least 3, and it cannot be implemented with three such gates either, so the depth is at least 4.
  • For a Clifford target unitary, the linear-program formulation certifies architecture incompatibility for circuits with on the order of seven two-qubit gates, far beyond the reach of the general semidefinite relaxation.
  • An experimental measurement of the fidelity between the target and the implemented channel that exceeds the witness threshold is a quantitative certificate that the implemented channel goes beyond the tested architecture.
  • Architecture incompatibility becomes a separability problem, so two architectures that allow the same input-output signalling can still be distinguished, as shown by the three-gate and five-gate examples.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • If the graph-diagonal reduction survives further scrutiny, the linear-program route should scale to Clifford circuits well past seven two-qubit gates, making architecture certificates practical for compiled Clifford subcircuits in error-correction pipelines; the paper demonstrates only the smaller cases.
  • The Bell-pair-counting picture suggests a resource interpretation: a target fails an architecture because the architecture cannot supply enough Bell-pair-generating steps across a time cut; extending this to general architectures would require adding trace-preserving constraints that the current analytical method drops.
  • Because the general semidefinite relaxation only enforces the PPT condition, tighter separability hierarchies should produce stronger witness thresholds for non-Clifford targets; the paper notes this possibility but does not test it.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 5 minor

Summary. The paper proposes a framework for certifying that a target unitary cannot be implemented within a prescribed quantum circuit architecture. The central quantity is α_Γ(U), the maximum fidelity between the Choi state of the target unitary and the Choi states of circuits compatible with architecture Γ. Since the exact optimization is nonconvex, the authors relax it to a semidefinite program (Eq. (4)) and, for Clifford target unitaries, to a linear program (Eq. (C14)) via graph-state depolarization. They also give an analytical Bell-pair-counting method for staircase architectures (Appendix D). Numerical results for two-, three-, and five-gate examples yield upper bounds below 1, and the Toffoli gate is claimed to require circuit depth at least 3 and then at least 4 based on exhaustive checks over all two- and three-gate architectures. The witness operator in Eq. (2) converts a bound α_Γ(U)<1 into a linear functional that is nonnegative on all Γ-compatible unitaries and negative on the target unitary.

Significance. If the central reduction is proved, the framework would be a useful contribution: it provides quantitative incompatibility certificates, connects circuit-architecture questions to separability theory and convex relaxations, and the Clifford LP simplification is a genuine practical advance. The analytical Bell-pair-counting arguments in Appendix D are clean and give parameter-free bounds that scale to arbitrarily many gates. The agreement with the known five-gate Toffoli lower bound is also encouraging. At present, however, the advertised rigor is not fully delivered because the graph-diagonal WLOG step is unproved, the exhaustive Toffoli checks are unreported, and the numerical solver outputs are not accompanied by certificates.

major comments (3)
  1. [Appendix C2, Eqs. (C9)-(C14)] The WLOG reduction to graph-diagonal operators is the load-bearing step for all Clifford results, but it is asserted rather than proved. The text states that the depolarisation procedure of Ref. [30] removes off-diagonal components while preserving the overlap with the graph state and the relevant positivity, normalisation, PPT and trace-preserving constraints. This is not immediate: the constraints in Eq. (C9) involve partial traces over specific subsystems B^O_k and partial transposes across the partitions B^IO_1|...|B^IO_m, whereas a stabilizer twirl acts globally on the full Hilbert space. One must prove that the twirl commutes with these subsystem operations, or otherwise exhibit a feasible graph-diagonal replacement for every feasible τ. Without such a proof, the LP in Eq. (C14) is not established as an upper bound on α_Γ(U), and the Clifford witnesses in Tables I and II, the five-gate example, and the Toffoli depth claims are unsupported. Please provide a complete proof of this reduction or replace it by a relaxation whose validity is proven.
  2. [Examples I and II, Toffoli depth claims] The claimed lower bounds on the Toffoli circuit depth rest on exhaustive checks that are not reported. The text states that 'we obtained for all the six possible circuit architectures made of 2 two-qubit gates the same upper bound' and that 'Checking analogously the incompatibility of the Toffoli gate with all the 12 possible circuit architectures...' yields depth at least 4, but no list of the architectures, no per-architecture upper bounds, no solver settings, and no code are given. These exhaustive statements are central advertised conclusions and must be independently reproducible. Please include the full enumeration data or a script that reproduces the checks and reports the certified upper bound for each architecture.
  3. [Tables I, II and the five-gate example] The numerical values are presented as rigorous upper bounds, but no certification is provided. The tables report approximate values such as ≃0.6366, ≤0.6798, and ≃0.857 obtained from LP/SDP/see-saw computations, without solver tolerances, dual certificates, or reproducible code. A floating-point optimum is not a mathematical certificate: for the witness construction one needs a guaranteed upper bound strictly below 1, and the see-saw tightness claims are likewise heuristic. Please provide either exact rational or interval-arithmetic-verified bounds, or make available code with fixed tolerances that yields certified values; the term 'rigorous certificate' should be reserved for data that actually certify the bound.
minor comments (5)
  1. [Abstract] The abstract claims that the LP enables 'more efficient numerical certification for circuits containing on the order of seven two-qubit gates', but the largest reported numerical LP example involves five gates; please add a seven-gate example or adjust the wording.
  2. [Eq. (C10)] The expression 'Tr[I_Γ]^2 diag(U†_LC τ U_LC) = ...' appears garbled; the normalisation factor Tr[I_Γ]^2 should be placed and defined explicitly.
  3. [Eq. (2)] The identity operator 1 in the witness definition is not defined; it should be the identity on H_{i1i2i3 o1o2o3} (or the corresponding full space in the general case).
  4. [Table I] The caption of Table I does not specify the composition convention for the gates A1 and A2; please state explicitly whether U = A2∘A1 or A1∘A2.
  5. [Appendix D2, Eq. (D7)] The sentence 'We thus retrieve the upper bound obtained in Appendix D1 for the case n=3' applies to the SWAP-SWAP example; the distinction from the general Clifford case should be made explicit to avoid overgeneralisation.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: the witness upper bounds are computed from the stated SDP/LP relaxations and analytical stabilizer counting, not fitted to or defined by the conclusions.

full rationale

The paper's derivation chain is self-contained relative to its inputs. The exact fidelity problem (Eq. 1) is relaxed to the SDP of Eq. (4) by replacing product Choi states with a PPT-positive τ under CPTP marginal constraints; this is a genuine relaxation, and the claimed upper-bound status of the SDP optimum follows from the feasible set being enlarged, not from any fitted value. For Clifford targets, the LP of Eq. (C14) is obtained by mapping the stabilizer Choi state to a graph state and then invoking the graph-state-basis depolarization procedure of Ref. [30]. Although Ref. [30] shares an author, it is a general published mathematical result about twirling with the stabilizer group, and Appendix C2 explicitly translates the positivity, normalization, PPT, and partial-trace constraints into linear conditions; this is a legitimate external tool, not an ansatz that assumes the target incompatibility. The numerical values in Tables I and II are solver outputs for the stated optimization problems, and the analytical bound in Appendix D is derived by counting Bell pairs across a bipartition, not by fitting. The Toffoli depth statements are separate exhaustive checks of the listed architectures, and agreement with Ref. [32] is a consistency check rather than a load-bearing input. The only delicate step is the asserted preservation of the partial-trace constraints under the depolarization twirl, which is argued in one sentence with a citation rather than proved in the appendix; that is a correctness risk, not circularity, because the step is a standard twirling argument and is not equivalent to the paper's conclusions by construction.

Assumptions & free parameters 0 free parameters · 6 assumptions · 0 invented entities

The framework is mostly self-contained; it postulates no physical entities and fits no free parameters. It relies on standard mathematical tools (Choi isomorphism, link product, graph states, PPT relaxation) and on the domain assumption that internal wires have fixed qubit dimension. The most fragile input is the graph-state depolarisation lemma of Appendix C2, which is cited from prior work rather than proved in full. Numerical outputs depend on solver precision and are not accompanied by machine-checked certificates.

assumptions (6)
  • domain assumption All internal wires of the circuit architecture carry a qubit (or d-dimensional) system.
    Stated in the main text and Appendix A1. This assumption prevents trivial decompositions where a wire carries an arbitrarily large system.
  • standard math The Choi-Jamiolkowski isomorphism and link product correctly represent unitary composition in the objective function.
    Used in Eqs. (1), (3) and Appendix A2; standard quantum information background.
  • standard math Any stabiliser state is local-Clifford equivalent to a graph state, and any feasible tau can be depolarised to graph-diagonal form while preserving the relevant constraints.
    Invoked in Appendix C2 via Refs. [29,30]; this is the load-bearing WLOG step.
  • standard math A product of unitary Choi matrices satisfies the PPT and CPTP constraints of the SDP relaxation.
    Needed for the relaxation in Eq. (4) to be a valid upper bound.
  • domain assumption For the analytical method, staircase architectures have no-signalling relations between input and output systems, allowing unitary constraints to be dropped.
    Stated in the main text and Appendix D; the authors note the technique is not yet general.
  • standard math The maximum overlap between a Bell state and a two-qubit separable state is 1/2.
    Used in the Bell-pair counting bounds of Appendix D.

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Cite this review

Pith. "Pith review of Witnessing the architecture of quantum circuits." pith.science (2026). https://pith.science/paper/5RDYNNCA

@misc{pith2026260813169,
  author       = {Pith},
  title        = {Pith review of: Witnessing the architecture of quantum circuits},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/5RDYNNCA}},
  note         = {Machine review of arXiv:2608.13169}
}
read the original abstract

Determining whether a target unitary can be implemented within a prescribed quantum circuit architecture is a fundamental problem in quantum information, with direct implications for optimisation and compilation of quantum circuits, and hardware-efficient quantum computation. While existing synthesis and compilation methods are primarily constructive, they generally do not provide rigorous certificates that a unitary cannot be realised using given implementation resources. Here we introduce a general framework to define quantum circuit architecture witnesses, which certify the incompatibility of a unitary transformation with a specified quantum circuit architecture. We formulate the witness construction as a semidefinite program by maximising the fidelity between the Choi state of the target unitary and those of tested circuits. The resulting witnesses provide practical and quantitative certificates of incompatibility, implying lower bounds on implementation resources such as the gate count or circuit depth, and can also be used experimentally to benchmark quantum devices by certifying that an implemented unitary channel goes beyond the capabilities of a given circuit architecture. For Clifford unitaries, we exploit the stabiliser formalism to reduce the construction to linear programming, enabling both more efficient numerical certification for circuits containing on the order of seven two-qubit gates, and analytical witnesses for some families of architectures made of an arbitrary number of gates.

Figures

Figures reproduced from arXiv: 2608.13169 by the authors.

Figure 1
Figure 1. Illustration of a potential decomposition of the unitary [PITH_FULL_IMAGE:figures/full_fig_p001_1.png] view at source ↗
Figure 2
Figure 2. a) Minimal example of the architecture incompatibility [PITH_FULL_IMAGE:figures/full_fig_p002_2.png] view at source ↗
Figure 3
Figure 3. Illustration of the incompatibility problem between [PITH_FULL_IMAGE:figures/full_fig_p004_3.png] view at source ↗
Figures from the paper (7 more)
Figure 4
Figure 4. Figure 4: Illustration of the incompatibility problem between [PITH_FULL_IMAGE:figures/full_fig_p005_4.png]
Figure 5
Figure 5. Figure 5: Illustration of the incompatibility problem between the [PITH_FULL_IMAGE:figures/full_fig_p006_5.png]
Figure 6
Figure 6. Figure 6: Illustration of the incompatibility problem between the tripartite unitary [PITH_FULL_IMAGE:figures/full_fig_p008_6.png]
Figure 7
Figure 7. Figure 7: The quantum circuit defined as the composition of [PITH_FULL_IMAGE:figures/full_fig_p011_7.png]
Figure 8
Figure 8. Figure 8: Illustration of the graph state |U⟩⟩⟨⟨U|⊗|1⟩⟩⟨⟨1| when the target unitary U is made of the composition of two SWAP gates arranged according to the staircase circuit architecture Γ = ({2, 3}, {1, 2}). Each line corresponds to a Bell pair between the input and output sys…
Figure 9
Figure 9. Figure 9: Graphical representation of a quantum circuit made of the composition of [PITH_FULL_IMAGE:figures/full_fig_p016_9.png]
Figure 10
Figure 10. Figure 10: Illustration of the graph state |U⟩⟩⟨⟨U|⊗|1⟩⟩⟨⟨1| when the target unitary U is made of the composition of n − 1 SWAP gates arranged according to the staircase circuit architecture Γ = ({n − 1, n}, {n − 2, n − 1}, . . . , {1, 2}). Each line corresponds to a Bell pair b…

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    SDP relaxation for the general case We now show that the SDP relaxation provided above for the minimal quantum circuit architectureΓ = ({1,2},{2,3}) can be extended to any quantum circuit architecture. Consider a target unitary operatorU:H i1...in →H o1...on that transformsnin...

  36. [45]

    As illustrated in Fig

    Quantum comb framework We consider the two gatesB1 :H i1i2→H o1c andB 2 :H ci3→H o2o3 composed according toΓ = ({1,2},{2,3}), where the systems inHc is a qubit. As illustrated in Fig. 7, the circuit obtained by composing the two gates can be rewritten in a quantum comb shape. ...

  37. [46]

    (1) in the main text

    Building a witness We consider the architecture incompatibility problem presented in Eq. (1) in the main text. An upper bound on the optimal fidelity can thus be obtained by optimising over the Choi matrix of the quantum comb characterised in Eq. (B1) and solving the following...

  38. [47]

    [29] for a review

    Graph States and the Stabiliser Formalism We review the basic features related to graph states and the stabiliser formalism that we employ in this paper, see Ref. [29] for a review. LetG= (V,E)be a simple undirected graph with|V|=n. To each vertexv∈Vwe associate a qubit. Thegr...

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    (A7) to witness the incompatibility with a general quantum circuit architecture can be turned to linear programming ifUis a Clifford unitary applied on qubits (d= 2)

    Turning Eq.(4)in the main text and Eq.(A7)into LPs We show that the SDP problem defined in Eq. (A7) to witness the incompatibility with a general quantum circuit architecture can be turned to linear programming ifUis a Clifford unitary applied on qubits (d= 2). That Eq. (4) in...

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    3 for an illustration

    A minimal example Weconsiderthefollowingincompatibilityproblem: givenaunitaryUmadeoftwoSWAPoperationscomposedaccording to the architectureΓtarget = ({2,3},{1,2}), show the incompatibility ofUwith the quantum circuit architectureΓ test = ({1,2},{2,3}), see Fig. 3 for an illustr...

  41. [50]

    Generalisation to am-gates architecture To illustrate this technique, we consider the example of a target unitaryUmade of the composition ofm=n−1SWAP gatesarrangedaccordingtoastaircasequantumcircuitarchitectureΓ n target = ({n−1,n},{n−2,n−1},...,{1,2}). Thetest circuit archite...

  42. [2022]

    39–74, arXiv:2112.00187 [quant-ph]

    pp. 39–74, arXiv:2112.00187 [quant-ph]

    arXiv

Pith tools

Reviewed August 15, 2026 · model on record in the stance chip above.