Range, Not Precision: Block-Floating-Point Half-Precision FFT and SAR Imaging on Apple Silicon

Mohamed Amine Bergach

REVIEW 1 major objections 2 minor 12 references

Range, Not Precision: Block-Floating-Point Half-Precision FFT and SAR Imaging on Apple Silicon

T0 review · 1 major / 2 minor · reviewed 2026-06-29 · grok-4.3

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Pith's one-line read A fixed 1/N scale before each inverse transform resolves FP16 overflow in SAR, matching FP32 quality at 42 dB SQNR while delivering 2.2x FFT speed on Apple Silicon.

desk verdict The paper shows a fixed 1/N BFP scaling before IFFTs, combined with a cascade effect, keeps a full FP16 SAR pipeline inside representable range on Apple Silicon while matching FP32 quality to 0.1 dB and doubling FFT throughput. read the letter →

arxiv 2605.28451 v1 pith:26D2DV2C submitted 2026-05-27 cs.PF cs.AR

Mohamed Amine Bergach This is my paper · ORCID

classification cs.PFcs.AR

keywords half-precisionblockfloatingpointFFTSARimagingdynamicrangesignalprocessingAppleSilicon

verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper shows that half-precision floating point fails in SAR imaging not because its 10-bit mantissa lacks precision but because its 5-bit exponent cannot accommodate the magnitude growth that occurs across a cascade of FFTs and multiplications. A single fixed scaling factor of 1/N applied before each inverse transform in a block-floating-point schedule keeps every intermediate value below the FP16 maximum. This produces the first end-to-end FP16 SAR pipeline whose image metrics match a full-precision reference. The approach also yields a radix-8 FP16 FFT that runs at 306 GFLOPS on an M1 chip.

What carries the argument

block-floating-point schedule: a single fixed 1/N scale applied before each inverse transform to bound magnitudes across the SAR cascade

What would settle it

Running the complete FP16 SAR pipeline without the 1/N scaling and checking whether outputs become NaN or image metrics deviate more than 0.1 dB from the FP32 reference.

Watch

Extended reading notes

Core claim

An FP16 FFT is mantissa-limited at 56-61 dB SQNR, yet a naive FP16 SAR pipeline produces NaN because conjugate-FFT-conjugate inverse transforms grow magnitudes by N and matched-filter products reach ~5 million at N=4096. A fixed-shift block-floating-point schedule applies a single 1/N scale before each inverse transform, bounding every intermediate below 4096. Range-compression output becomes O(1) instead of O(N), keeping downstream azimuth-FFT output FP16-loadable. The resulting pipeline matches FP32 in peak and integrated sidelobe ratios, target SNR, and resolution to within 0.1 dB at 42 dB end-to-end SQNR, while radix-8 FP16 FFT reaches 306 GFLOPS.

Load-bearing premise

A single fixed 1/N scale applied before each inverse transform is sufficient to bound all intermediates below the FP16 maximum without quality loss or per-block exponent tracking in the full SAR cascade.

Editorial extensions

If this is right

Peak and integrated sidelobe ratios, target SNR, and resolution in the FP16 SAR image match the FP32 reference to within 0.1 dB.
Radix-8 FP16 FFT reaches 306 GFLOPS, 2.2 times the 139 GFLOPS FP32 baseline on M1.
Range-compression output stays O(1) and azimuth-FFT output remains FP16-loadable instead of growing to O(N^2).
FP8 (E4M3/E5M2) collapses to 14-20 dB SQNR, establishing FP16 as the current precision floor for FFT-based radar.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

Fixed scaling of this form may apply to other multi-stage FFT pipelines where intermediate magnitudes grow linearly with problem size.
Hardware with still narrower exponents may require adaptive per-block scaling once fixed 1/N becomes insufficient for larger N.
The result indicates that dynamic-range management can be the decisive lever for lowering precision in FFT-heavy applications rather than mantissa width alone.

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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit.

Desk Editor's Note

read the letter

The core result is that FP16 works for radar-grade SAR once you manage exponent range instead of assuming the 10-bit mantissa is the problem. They measure a naive FP16 pipeline hitting NaN from both IFFT growth by N and the matched-filter product at ~5e6, then apply a single 1/N scale before each inverse transform. This turns range-compression output into O(1), which prevents the azimuth stage from blowing up to O(N^2). End-to-end they get 42 dB SQNR with sidelobe ratios, target SNR, and resolution within 0.1 dB of FP32, plus a radix-8 FP16 FFT at 306 GFLOPS versus 139 for FP32 on an M1.

What stands out is the explicit tailoring to the conjugate-FFT-conjugate structure and the concrete hardware numbers on real silicon rather than simulation. The claim that FP8 drops to 14-20 dB SQNR while FP16 stays usable also feels like a useful boundary.

The stress-test note about the product step overflowing before the 1/N scale is worth checking in the full text. The abstract says the cascade keeps everything below 4096, so they must be handling the product either by earlier scaling or by the way the blocks are arranged; if the methods section shows the exact placement and no post-hoc adjustment, the central claim holds. The work is narrow (one chip family, one SAR flow) but the measurements are direct and the SQNR numbers are specific enough to reproduce.

This is useful for anyone doing embedded FFT workloads on mobile GPUs or low-precision radar pipelines. It deserves a serious referee because the experimental claims are falsifiable and the mechanism is simple enough to test.

Referee Report

1 major / 2 minor

Summary. The manuscript claims that dynamic range (exponent) limitations, not mantissa precision, are the binding constraint for FP16 in FFT and SAR imaging. It introduces a fixed-shift block-floating-point schedule consisting of a single 1/N scale before each inverse transform; this is asserted to bound all intermediates below 4096, enabling a fully FP16 SAR pipeline (range compression through azimuth processing) that matches FP32 reference performance to within 0.1 dB at 42 dB end-to-end SQNR while delivering 306 GFLOPS (2.2× FP32) for a radix-8 FP16 FFT on Apple M1. FP8 formats are shown to collapse to 14–20 dB SQNR.

Significance. If the central claims are substantiated, the work provides direct hardware evidence that simple range management via scaling suffices for radar-grade FP16 SAR on consumer Apple Silicon, with concrete SQNR, sidelobe, and throughput numbers. This reframes low-precision FFT viability around exponent handling rather than mantissa bits and supplies reproducible throughput baselines (139 GFLOPS FP32 vs. 306 GFLOPS FP16) that could inform hardware-aware signal-processing implementations.

major comments (1)

[Abstract] Abstract (BFP schedule paragraph): the single 1/N scale is stated to be applied before each inverse transform and to bound every intermediate below 4096. However, the matched-filter product (~5×10^6 at N=4096) occurs in range compression prior to the inverse transform; no pre-multiplication scaling, per-stage normalization, or higher-precision accumulator is described that would keep this product inside FP16’s 65504 maximum. Because the central claim requires an end-to-end FP16 pipeline without quality loss, this omission is load-bearing.

minor comments (2)

The manuscript does not report error bars, dataset size, or full experimental methods for the SAR imaging results; these details would strengthen verifiability of the 0.1 dB fidelity claim.
[Abstract] The term “block-floating-point” is used in the title and abstract, yet only a fixed global 1/N shift is described; clarifying whether per-block exponents are employed (and their block size) would improve precision of the method description.

Simulated Author's Rebuttal

1 responses · 0 unresolved

We thank the referee for the thorough review and for highlighting the need for greater precision in the abstract's description of the BFP schedule. The point is well taken and we will revise accordingly.

read point-by-point responses

Referee: [Abstract] Abstract (BFP schedule paragraph): the single 1/N scale is stated to be applied before each inverse transform and to bound every intermediate below 4096. However, the matched-filter product (~5×10^6 at N=4096) occurs in range compression prior to the inverse transform; no pre-multiplication scaling, per-stage normalization, or higher-precision accumulator is described that would keep this product inside FP16’s 65504 maximum. Because the central claim requires an end-to-end FP16 pipeline without quality loss, this omission is load-bearing.

Authors: We agree the abstract paragraph is too concise and does not explicitly state the pre-multiplication scaling required to keep the matched-filter product inside FP16 range. The full manuscript describes a complete fixed-shift BFP schedule that applies scaling after forward FFTs (in addition to the 1/N before each inverse FFT) so that range-compression outputs remain O(1) and all intermediates stay below 4096; this produces the reported 42 dB SQNR with no quality loss relative to FP32. To make the abstract self-contained and address the load-bearing concern, we will expand it to enumerate the full scaling cascade, including the factors applied before multiplication. revision: yes

Circularity Check

0 steps flagged · score 0.0 of 10

No circularity; claims rest on hardware measurements of FP16 FFT and SAR pipeline

full rationale

The paper reports direct empirical results: measured SQNR of 56-61 dB for FP16 FFT, 306 GFLOPS throughput, and end-to-end SAR metrics (sidelobe ratios, SNR, resolution) matching FP32 within 0.1 dB at 42 dB SQNR. The BFP schedule (single 1/N scale before inverse transforms) is presented as an engineering choice that bounds intermediates, with no equations or derivations shown that reduce these measured outcomes to quantities defined only by the paper's own inputs. No self-citations, fitted parameters renamed as predictions, or self-definitional steps appear in the provided text. The central claims are falsifiable via external hardware runs and do not rely on load-bearing self-referential logic.

Assumptions & free parameters 1 free parameters · 1 assumptions · 0 invented entities

The central claim rests on standard FFT magnitude-growth properties and a single ad-hoc scaling choice chosen to fit FP16 limits; no new physical entities or fitted constants beyond the explicit 1/N factor are introduced.

free parameters (1)

fixed 1/N scale factor
Chosen to bound intermediates below 4096 for N=4096; directly tied to the overflow threshold of FP16.

assumptions (1)

standard math Conjugate-FFT-conjugate inverse grows magnitudes by factor N
Invoked to explain why naive FP16 SAR produces NaN.

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Cite this review

Pith. "Pith review of Range, Not Precision: Block-Floating-Point Half-Precision FFT and SAR Imaging on Apple Silicon." pith.science (2026). https://pith.science/paper/26D2DV2C

@misc{pith2026260528451,
  author       = {Pith},
  title        = {Pith review of: Range, Not Precision: Block-Floating-Point Half-Precision FFT and SAR Imaging on Apple Silicon},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/26D2DV2C}},
  note         = {Machine review of arXiv:2605.28451}
}

abstract

Half precision (FP16) promises to double FFT throughput on GPUs, but the prevailing view is that its 10-bit mantissa makes it unsuitable for radar-grade signal processing. We show this framing is wrong on Apple Silicon: the binding constraint for FFT and Synthetic Aperture Radar (SAR) is not mantissa \emph{precision} but the 5-bit exponent's \emph{dynamic range}. We first measure that an FP16 FFT is mantissa-limited at 56--61~dB signal-to-quantization-noise ratio (SQNR) -- comfortably radar-usable -- yet a na\"ive FP16 SAR pipeline produces \emph{only} \texttt{NaN}, because the conjugate--FFT--conjugate inverse transform grows magnitudes by a factor of $N$, and the matched-filter product ($\sim\!5\times10^6$ at $N\!=\!4096$) overflows FP16's 65{,}504 ceiling. We resolve this with a fixed-shift \emph{block-floating-point} (BFP) schedule: a single $1/N$ scale applied before each inverse transform bounds every intermediate below 4096. A cascade follows: range-compression output becomes $O(1)$ instead of $O(N)$, which in turn keeps the downstream azimuth-FFT output FP16-loadable instead of overflowing at $O(N^2)$. The result is the first quality-preserving FP16 SAR pipeline: peak/integrated sidelobe ratios, target SNR, and resolution match the FP32 reference to within $0.1$~dB at $42$~dB end-to-end SQNR, while a radix-8 FP16 FFT reaches 306~GFLOPS -- $2.2\times$ over the 139~GFLOPS FP32 baseline -- on a fanless Apple~M1. Finally, we measure that FP8 (E4M3/E5M2) collapses to 14--20~dB SQNR, making FP16 \emph{today's} precision floor for FFT-based radar -- one that future precision-recovery methods may yet lower -- and showing that the lever for low precision here is range management, not mantissa bits.

Figures

Figures reproduced from arXiv: 2605.28451 by the authors.

Discussion (0). Continue with ORCID to comment.

Reference graph

Works this paper leans on

12 extracted references · 4 canonical work pages

[1]

I. G. Cumming and F. H. Wong,Digital Processing of Synthetic Aperture Radar Data: Algorithms and Implementation. Artech House, 2005

2005
[2]

Spectral methods via FFTs in emerging machine number formats: OFP8, bfloat16, posit, and takum arithmetics,

L. Hunhold and J. Gustafson, “Spectral methods via FFTs in emerging machine number formats: OFP8, bfloat16, posit, and takum arithmetics,” arXiv:2504.21197, 2025

work page arXiv 2025
[3]

tcFFT: A fast half-precision FFT library for NVIDIA Tensor Cores,

B. Li and S. Cheng, “tcFFT: A fast half-precision FFT library for NVIDIA Tensor Cores,” inIEEE Int. Parallel Distrib. Process. Symp. Workshops (IPDPSW), 2021. arXiv:2104.11471

work page arXiv 2021
[4]

MFFT: A GPU accelerated highly efficient mixed- precision large-scale FFT framework,

Y . Zhaoet al., “MFFT: A GPU accelerated highly efficient mixed- precision large-scale FFT framework,”ACM Trans. Archit. Code Optim., vol. 20, no. 3, 2023

2023
[5]

A block floating point implementation for anN- point FFT on the TMS320C55x DSP,

Texas Instruments, “A block floating point implementation for anN- point FFT on the TMS320C55x DSP,” Application Report SPRA948, 2003

2003
[6]

FPGA implementation of an efficient FFT processor for FMCW radar signal processing,

J. Kimet al., “FPGA implementation of an efficient FFT processor for FMCW radar signal processing,”Sensors, vol. 21, no. 19, p. 6443, 2021

2021
[7]

An FPGA-based four-channel 128k-point FFT processor suitable for spaceborne SAR,

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2021
[8]

VkFFT—a performant, cross-platform and open-source GPU FFT library,

D. Tolmachev, “VkFFT—a performant, cross-platform and open-source GPU FFT library,”IEEE Access, vol. 11, pp. 12 039–12 058, 2023

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[9]

Beating vDSP: A 138 GFLOPS radix-8 Stockham FFT on Apple Silicon via two-tier register-threadgroup memory decomposi- tion,

M. A. Bergach, “Beating vDSP: A 138 GFLOPS radix-8 Stockham FFT on Apple Silicon via two-tier register-threadgroup memory decomposi- tion,”arXiv:2603.27569, 2026

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From 8 seconds to 370 ms: Kernel-fused SAR imaging on Apple Silicon via single-dispatch FFT pipelines,

M. A. Bergach, “From 8 seconds to 370 ms: Kernel-fused SAR imaging on Apple Silicon via single-dispatch FFT pipelines,”arXiv:2604.03585, 2026

2026 arXiv
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M. A. Bergach, “Dual-select FMA butterfly for FFT: Eliminating twiddle factor singularities with bounded precomputed ratios,” submitted, 2026

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Apple Machine Learning Research, “Exploring LLMs with MLX and the neural accelerators in the M5 GPU,” 2025. [Online]. Available: https: //machinelearning.apple.com/research/exploring-llms-mlx-m5

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Pith tools

Reviewed June 29, 2026 · model on record in the stance chip above.

[1] [1]

I. G. Cumming and F. H. Wong,Digital Processing of Synthetic Aperture Radar Data: Algorithms and Implementation. Artech House, 2005

2005

[2] [2]

Spectral methods via FFTs in emerging machine number formats: OFP8, bfloat16, posit, and takum arithmetics,

L. Hunhold and J. Gustafson, “Spectral methods via FFTs in emerging machine number formats: OFP8, bfloat16, posit, and takum arithmetics,” arXiv:2504.21197, 2025

work page arXiv 2025

[3] [3]

tcFFT: A fast half-precision FFT library for NVIDIA Tensor Cores,

B. Li and S. Cheng, “tcFFT: A fast half-precision FFT library for NVIDIA Tensor Cores,” inIEEE Int. Parallel Distrib. Process. Symp. Workshops (IPDPSW), 2021. arXiv:2104.11471

work page arXiv 2021

[4] [4]

MFFT: A GPU accelerated highly efficient mixed- precision large-scale FFT framework,

Y . Zhaoet al., “MFFT: A GPU accelerated highly efficient mixed- precision large-scale FFT framework,”ACM Trans. Archit. Code Optim., vol. 20, no. 3, 2023

2023

[5] [5]

A block floating point implementation for anN- point FFT on the TMS320C55x DSP,

Texas Instruments, “A block floating point implementation for anN- point FFT on the TMS320C55x DSP,” Application Report SPRA948, 2003

2003

[6] [6]

FPGA implementation of an efficient FFT processor for FMCW radar signal processing,

J. Kimet al., “FPGA implementation of an efficient FFT processor for FMCW radar signal processing,”Sensors, vol. 21, no. 19, p. 6443, 2021

2021

[7] [7]

An FPGA-based four-channel 128k-point FFT processor suitable for spaceborne SAR,

“An FPGA-based four-channel 128k-point FFT processor suitable for spaceborne SAR,”Electronics, vol. 10, no. 7, p. 816, 2021

2021

[8] [8]

VkFFT—a performant, cross-platform and open-source GPU FFT library,

D. Tolmachev, “VkFFT—a performant, cross-platform and open-source GPU FFT library,”IEEE Access, vol. 11, pp. 12 039–12 058, 2023

2023