Paper Citation Record · LEDGER

Design and Implementation of a RISC-V SoC with Custom DSP Accelerators for Edge Computing

As of 9 August 2026, this Paper Citation Record lists 9 of 9 outbound references and 0 inbound Pith citation observations for arXiv:2506.06693.

A citation records a reference. It does not transfer a finding from one paper to another.

pith.paper-citation-record.v1
2506.06693 v1

Coverage vector

measured 9 of 9 reference resolution

Typed states for the displayed outbound observations.

Source: paper_references, paper_reference_links, observed 2026-08-07T05:55:46.107957Z

measured 9 of 9 standing notices

One-hop event checks from named stored sources.

Source: scholarly_work_events, retraction_status_cache, observed 2026-08-09T06:31:02.800959+00:00

measured 0 of 0 inbound itemization

Pith citing papers itemized under the disclosed page cap.

Source: paper_references, paper_reference_links

measured 0 of 1 external citation measurements

A source-named dated measurement, never combined with another source.

Source: cited_works

Reference resolution

9 of 9 outbound references displayed

verified exact0
verified fuzzy8
unresolved1
parse uncertain0
malformed identifier0
metadata mismatch0

External citation measurements

No source-named external measurement is stored.

Outbound references

Observation 4bff99bd-0549-4ade-9bc8-d225e9b2b81c · outbound

This paper cites The RISC-V Instruction Set Manual, Volume I: User-Level ISA,.

Design and Implementation of a RISC-V SoC with Custom DSP Accelerators for Edge Computing The RISC-V Instruction Set Manual, Volume I: User-Level ISA,

Reference 1

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:55:46.230857Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-09T06:31:02.800959+00:00.

Observation 3c580e07-bb73-4d5d-a869-afbdea45dfbf · outbound

This paper cites Instruction Sets Should Be Free: The Case For RISC-V,.

Design and Implementation of a RISC-V SoC with Custom DSP Accelerators for Edge Computing Instruction Sets Should Be Free: The Case For RISC-V,

Reference 2

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:55:46.219944Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-09T06:31:02.800959+00:00.

Observation b9ed8bec-6f38-4a35-bcdc-7ac6294e585b · outbound

This paper cites RISC-V Vector ISA Specification,.

Design and Implementation of a RISC-V SoC with Custom DSP Accelerators for Edge Computing RISC-V Vector ISA Specification,

Reference 3

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:55:46.208208Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-09T06:31:02.800959+00:00.

Observation d516a278-ff7d-454d-b5fa-670702310aba · outbound

This paper cites an unresolved cited work.

Design and Implementation of a RISC-V SoC with Custom DSP Accelerators for Edge Computing Unresolved cited work

Reference 4

Resolution: unresolved; raw_fallback, observed 2026-08-07T05:55:46.196126Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-09T06:31:02.800959+00:00.

Observation c3b375ec-bdee-4eb5-8876-ea53c0cdc661 · outbound

This paper cites Mi-V Ecosystem and DSP Modules,.

Design and Implementation of a RISC-V SoC with Custom DSP Accelerators for Edge Computing Mi-V Ecosystem and DSP Modules,

Reference 5

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:55:46.184094Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-09T06:31:02.800959+00:00.

Observation 96d95e67-0554-4464-9c42-eeccd93fa224 · outbound

This paper cites Shakti Processor Project: Enabling Custom ISA Extensions,.

Design and Implementation of a RISC-V SoC with Custom DSP Accelerators for Edge Computing Shakti Processor Project: Enabling Custom ISA Extensions,

Reference 6

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:55:46.172900Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-09T06:31:02.800959+00:00.

Observation 3a478847-43b3-44a1-a6df-635515b0a8d4 · outbound

This paper cites PULP Platform for Ultra-Low-Power Deep Learning,.

Design and Implementation of a RISC-V SoC with Custom DSP Accelerators for Edge Computing PULP Platform for Ultra-Low-Power Deep Learning,

Reference 7

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:55:46.161017Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-09T06:31:02.800959+00:00.

Observation 37a8fe65-3a36-4f86-a7bd-ff10cf351643 · outbound

This paper cites 1.1 Computing’s Energy Problem (and what we can do about it),.

Design and Implementation of a RISC-V SoC with Custom DSP Accelerators for Edge Computing 1.1 Computing’s Energy Problem (and what we can do about it),

Reference 8

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:55:46.149632Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-09T06:31:02.800959+00:00.

Observation c95cdb8d-8c6e-4ba8-bb52-3b4113eb3101 · outbound

This paper cites CMSIS-DSP Software Library,.

Design and Implementation of a RISC-V SoC with Custom DSP Accelerators for Edge Computing CMSIS-DSP Software Library,

Reference 9

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:55:46.136980Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-09T06:31:02.800959+00:00.

Pith citing papers

No inbound Pith citation observations are available.