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arxiv: 2605.16114 · v1 · pith:3222RQAVnew · submitted 2026-05-15 · 💻 cs.NE · cs.LG

Scalable neuromorphic computing from autonomous spiking dynamics in a clockless reconfigurable chip

Eric Oliveira Gomes , Damien Rontani This is my paper

Pith reviewed 2026-05-19 17:51 UTC · model grok-4.3

classification 💻 cs.NE cs.LG
keywords neuromorphic computingspiking neuronsclockless FPGAasynchronous circuitsaudio classificationlow-power hardwarereconfigurable chipsBoolean spiking networks
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The pith

Clockless asynchronous circuits on standard FPGAs generate autonomous spiking dynamics that solve machine-learning tasks at competitive accuracy with low power.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

This paper establishes that spiking neuron networks can emerge directly from the natural time-continuous evolution of clockless digital logic on ordinary commercial FPGAs. The authors configure these dynamics through adjustable excitatory and inhibitory synaptic weights to process spike-encoded inputs and perform classification. On an audio classification benchmark the resulting system reaches accuracy levels comparable to other neuromorphic approaches while drawing substantially less power than conventional digital hardware. The work positions reconfigurable chips as a practical route to energy-efficient, quasi-analog neuromorphic processors without requiring custom analog fabrication.

Core claim

Autonomous spiking dynamics arise from the asynchronous, time-continuous evolution of clockless digital circuits on FPGAs; when these circuits are arranged as networks of Boolean spiking neurons whose excitatory and inhibitory synaptic weights are set appropriately, the resulting system handles spike-encoded data and achieves competitive performance on machine-learning tasks such as audio classification while consuming significantly less power than traditional digital implementations.

What carries the argument

Networks of interacting Boolean spiking neurons whose excitatory and inhibitory synaptic weights are configured on clockless asynchronous digital circuits whose time-continuous evolution produces the spiking activity.

If this is right

  • Spike-based encoding combined with the inherent high-speed evolution of asynchronous circuits yields fast processing for sensory data.
  • Power consumption drops markedly relative to clocked digital designs that perform equivalent neural computations.
  • Reconfigurable commercial hardware can serve as an intermediate platform between conventional digital processors and dedicated analog neuromorphic chips.
  • Clockless digital circuits become a viable substrate for neuromorphic computing without specialized fabrication steps.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • Existing FPGA development boards could support rapid prototyping and deployment of neuromorphic algorithms in field settings.
  • The same reconfigurability might allow the hardware to switch between different sensory modalities or to incorporate limited on-chip adaptation rules.
  • Further efficiency gains could appear if the approach is combined with other asynchronous or event-driven sensor interfaces.

Load-bearing premise

Synaptic weights can be chosen so that the autonomous spiking dynamics of the clockless circuits remain stable and accurate when scaled to solve machine-learning tasks.

What would settle it

The FPGA implementation fails to reach competitive accuracy on the audio classification task or produces unstable spiking patterns once the network size or input rate is increased.

Figures

Figures reproduced from arXiv: 2605.16114 by Damien Rontani, Eric Oliveira Gomes.

Figure 1
Figure 1. Figure 1: Overview of the spiking Boolean neuron architecture. (a) Internal structure of the Boolean neurons depicting the interconnection between the two functional blocks implementing the soma and synapses (b) Detailed diagram of the Boolean neuron circuit. The soma module is composed of a bidirectional asynchronous counter module (ACM), modeling membrane depolarization and allowing for excitation and inhibition, … view at source ↗
Figure 2
Figure 2. Figure 2: Overview of a typical B-SNN comprising 196 neurons arranged in a 7×7×4 grid, driven by spiking stimuli. (a) Raster plot over 3.2µs of a spiking input sample representing the spoken English digit “one”. The highlighted region illustrates a representative spike with a full width at half maximum (FWHM) of 2.07ns, measured using a high-speed oscilloscope. (b) Raster plot of the corresponding spiking output, ob… view at source ↗
Figure 3
Figure 3. Figure 3: System pipeline and classification performance of a B-SNN for voice recognition. (a) Overview of the complete experimental pipeline, consisting of event-driven input transmission to the FPGA, retrieval of Boolean-SNN spike events by a custom-built multi-channel time-tagger, and subsequent feature encoding for classification. (b) Accuracies obtained using features derived from rate encoding, latency encodin… view at source ↗
read the original abstract

We propose a scalable neuromorphic architecture based on spiking dynamics emerging from the autonomous time-continuous evolution of clockless (asynchronous) digital circuits. Implemented on commercially available field-programmable gate arrays (FPGAs), our system implements networks of interacting Boolean spiking neurons with configurable excitatory and inhibitory synaptic weights. A complete processing pipeline enables efficient handling of spike-encoded data for solving machine-learning tasks. We demonstrate competitive performance for an audio classification task with spike-based encoding and high-speed processing. Power consumption is significantly lower than traditional digital implementations; this makes our approach an efficient alternative that bridges the gap to dedicated analog neuromorphic systems without the need for specialized hardware design. More generally, our approach establishes clockless digital hardware as a viable platform for neuromorphic computing. It paves the way for reconfigurable chips to be turned into energy-efficient quasi-analog neuromorphic processors.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 2 minor

Summary. The manuscript proposes a scalable neuromorphic architecture that exploits autonomous spiking dynamics arising from the time-continuous evolution of clockless (asynchronous) Boolean circuits implemented on commercial FPGAs. Networks of interacting spiking neurons are configured solely through excitatory and inhibitory synaptic weights; a complete spike-encoded processing pipeline is described and applied to an audio classification task, with claims of competitive accuracy, high-speed operation, and substantially lower power than conventional digital implementations.

Significance. If the central claims are substantiated, the work would demonstrate that clockless digital fabrics on off-the-shelf FPGAs can be turned into reconfigurable, energy-efficient neuromorphic processors without custom analog hardware, thereby bridging digital reconfigurable platforms and dedicated neuromorphic systems.

major comments (2)
  1. [Abstract and §4] Abstract and §4 (audio-classification results): the manuscript asserts 'competitive performance' and 'significantly lower' power but supplies no numerical accuracy figures, baseline comparisons, error bars, dataset size, or power measurements in the provided text; without these data the central empirical claim cannot be evaluated.
  2. [§3 and §5] §3 (network implementation) and §5 (scaling discussion): the assumption that propagation delays, routing skew, and hazards in the asynchronous FPGA fabric remain benign when weights are set for a concrete ML objective is load-bearing, yet no quantitative characterization (e.g., measured spike-timing jitter, accuracy versus network size, or comparison against a clocked baseline on the same fabric) is reported for the audio task.
minor comments (2)
  1. [§2] Clarify the precise Boolean neuron model and the mapping from synaptic weights to FPGA LUT/RAM resources.
  2. Add a table or figure that directly compares power and latency against at least one clocked digital baseline on the same FPGA device.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the constructive feedback and the opportunity to improve the manuscript. We address each major comment below and will revise the paper accordingly to strengthen the presentation of results and supporting characterizations.

read point-by-point responses

  1. Referee: [Abstract and §4] Abstract and §4 (audio-classification results): the manuscript asserts 'competitive performance' and 'significantly lower' power but supplies no numerical accuracy figures, baseline comparisons, error bars, dataset size, or power measurements in the provided text; without these data the central empirical claim cannot be evaluated.

    Authors: We agree that the abstract and §4 would benefit from explicit numerical reporting to allow readers to evaluate the claims directly from the text. Although the results are supported by figures in §4, we will revise both the abstract and §4 to include specific accuracy values with error bars, dataset size and split details, baseline comparisons, and quantitative power measurements (including the measurement methodology). revision: yes

  2. Referee: [§3 and §5] §3 (network implementation) and §5 (scaling discussion): the assumption that propagation delays, routing skew, and hazards in the asynchronous FPGA fabric remain benign when weights are set for a concrete ML objective is load-bearing, yet no quantitative characterization (e.g., measured spike-timing jitter, accuracy versus network size, or comparison against a clocked baseline on the same fabric) is reported for the audio task.

    Authors: We acknowledge that additional quantitative evidence would strengthen the claims regarding timing stability under ML-derived weights. The current manuscript relies on observed functional stability for the audio task, but we will add measured spike-timing jitter statistics, accuracy as a function of network size, and a direct comparison against a clocked baseline implemented on the same FPGA fabric. These data will be incorporated into a revised §3 and an expanded §5. revision: yes

Circularity Check

0 steps flagged

No circularity in derivation; claims rest on hardware implementation and empirical demonstration

full rationale

The paper describes a neuromorphic architecture implemented on commercial FPGAs using clockless asynchronous digital circuits to generate autonomous spiking dynamics, configured via excitatory/inhibitory weights for an audio classification task. No equations, fitted parameters, or first-principles derivations appear in the abstract or described claims that reduce by construction to self-defined inputs or predictions. Performance results are presented as experimental outcomes from the physical FPGA realization rather than statistical fits or self-referential models. The central premise is supported by direct hardware behavior and task accuracy measurements, which are externally falsifiable and independent of any internal redefinition or self-citation chain. This is a standard non-circular finding for an implementation-focused hardware paper.

Axiom & Free-Parameter Ledger

1 free parameters · 1 axioms · 0 invented entities

The central claim rests on the domain assumption that clockless digital circuits naturally produce usable spiking dynamics and on the free parameter of configurable synaptic weights; no new physical entities are postulated.

free parameters (1)
  • excitatory and inhibitory synaptic weights
    Weights are described as configurable parameters that must be set to realize functional networks for the audio task.
axioms (1)
  • domain assumption Spiking dynamics emerge autonomously from the time-continuous evolution of clockless digital circuits.
    This premise is invoked to justify the entire neuromorphic architecture without a clock.

pith-pipeline@v0.9.0 · 5677 in / 1316 out tokens · 48574 ms · 2026-05-19T17:51:36.469262+00:00 · methodology

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