FREESS: A Web-Based Educational Simulator for a RISC-V-Inspired Superscalar Processor with Tomasulo-Style Dynamic Scheduling

Miquel Moret\'o Planas; Roberto Giorgi

arxiv: 2605.30377 · v1 · pith:33YFMOENnew · submitted 2026-05-26 · 💻 cs.AR · cs.PF

FREESS: A Web-Based Educational Simulator for a RISC-V-Inspired Superscalar Processor with Tomasulo-Style Dynamic Scheduling

Roberto Giorgi , Miquel Moret\'o Planas This is my paper

Pith reviewed 2026-07-01 15:54 UTC · model grok-4.3

classification 💻 cs.AR cs.PF

keywords educational simulatorsuperscalar processorTomasulo algorithmRISC-Vregister renamingreorder bufferout-of-order executioninstruction window

0 comments

The pith

FREESS gives a single textual view of register renaming, issue, execution, and commit in a Tomasulo-style superscalar processor.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper presents FREESS as an open-source web simulator that displays the internal state of a RISC-V-inspired superscalar processor using Tomasulo dynamic scheduling. It aims to let students track how instructions move through renaming, issue, execution, write-back, commit, and memory ordering on a cycle-by-cycle basis. The tool combines the register map, free pool, instruction window, reorder buffer, and load/store queues into one readable representation that updates each cycle. Runtime parameters such as issue width, queue sizes, and functional-unit latencies can be adjusted to compare different processor organizations directly. The simulator has been used in advanced computer architecture courses for about fifteen years.

Core claim

FREESS is an open-source web-based simulator for a RISC-V-inspired superscalar processor that implements Tomasulo-style dynamic scheduling. It provides a compact, cycle-by-cycle view of register renaming, issue, execution, write-back, commit, and memory ordering. The simulator exposes the register map, free pool, instruction window, reorder buffer, and load/store queues in one textual representation so that the evolution of the hardware state can be followed on screen and reproduced on paper. Runtime parameters such as issue width, queue sizes, and functional-unit latencies can be changed easily to enable direct comparison among alternative superscalar organizations.

What carries the argument

The single textual representation that combines the register map, free pool, instruction window, reorder buffer, and load/store queues and updates each cycle.

If this is right

Alternative superscalar organizations can be compared directly by varying issue width, queue sizes, and functional-unit latencies at runtime.
Students can follow the evolution of hardware state on screen and reproduce it on paper for any chosen parameter set.
The tool supports teaching of instruction-level parallelism and dynamic scheduling in advanced computer architecture courses.
Public availability allows repeated use and sharing of specific configuration examples across classrooms.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

The combined display of multiple structures may help learners see how register renaming interacts with the reorder buffer and load/store queues in one glance.
If the model holds, the simulator can serve as a reference for checking student hand simulations of Tomasulo execution.
The ability to change parameters on the fly suggests the same interface could support quick exploration of design trade-offs in related out-of-order mechanisms.

Load-bearing premise

The simulator's internal model correctly implements Tomasulo-style dynamic scheduling and RISC-V semantics for the exposed hardware structures.

What would settle it

Running a known instruction sequence through the simulator and comparing its cycle-by-cycle state changes against an independent manual Tomasulo simulation with identical parameters would reveal any mismatch in the model.

Figures

Figures reproduced from arXiv: 2605.30377 by Miquel Moret\'o Planas, Roberto Giorgi.

**Figure 1.** Figure 1: Architectural view used by FREESS to explain the stages and structures of a Tomasulo-based superscalar pipeline. Modeled machine and execution environment FREESS models a compact superscalar processor around seven instructions: ADD, ADDI, BEQ, BNE, LW, MUL, and SW. The instruction set is intentionally minimal but sufficient to expose the main mechanisms of a superscalar CPU: fetch, renaming, out-of-order … view at source ↗

**Figure 2.** Figure 2: Cycle snapshot showing issued instructions, completed out-of-order operations, instruction-window state, reorder-buffer entries, and stall explanations. pact visibility of full-machine evolution over richer but more fragmented interaction [3–5]. That design choice makes it effective for understanding why instructions may complete out of order while still committing in order, and why limits in queues, or … view at source ↗

read the original abstract

FREESS (Free Educational Superscalar Simulator) is an open-source teaching environment for instruction-level parallelism in a RISC-V-inspired superscalar processor. It provides a compact, cycle-by-cycle view of register renaming, issue, execution, write-back, commit, and memory ordering in a Tomasulo-style machine. The simulator exposes the register map, free pool, instruction window, reorder buffer, and load/store queues in one textual representation, so the evolution of the hardware state can be followed on screen and reproduced on paper. Runtime parameters such as issue width, queue sizes, and functional-unit latencies can be changed easily, enabling direct comparison among alternative superscalar organizations. The tool has supported Advanced Computer Architecture teaching for about fifteen years and is publicly available on GitHub.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Desk Editor's Note private letter to a colleague

FREESS is a straightforward open-source web simulator for teaching Tomasulo scheduling on RISC-V, with 15 years of classroom use but no new algorithms or measurements.

read the letter

FREESS is a web-based educational simulator for a RISC-V-inspired superscalar processor that uses Tomasulo-style dynamic scheduling. The paper's core contribution is a compact cycle-by-cycle display of register renaming, issue, execution, write-back, commit, and memory ordering, with all the main structures shown in one textual view and runtime parameters that can be adjusted on the fly.

It does a few things well. The single-screen representation of the register map, free pool, instruction window, reorder buffer, and load/store queues makes the state evolution easy to follow and reproduce on paper. The ability to change issue width, queue sizes, and functional-unit latencies supports quick comparisons between different superscalar setups. Public GitHub availability and fifteen years of use in advanced computer architecture courses provide some practical grounding.

The soft spots are the absence of any verification data. There is no comparison against real hardware, no error analysis, and no student outcome measurements. Correctness of the internal Tomasulo model and RISC-V semantics therefore rests on the open code and classroom experience rather than on anything reported in the paper. This is typical for tool descriptions, but it means the work adds an incremental RISC-V-specific implementation rather than a new technique.

The paper is for computer architecture instructors who want a free, customizable simulator for illustrating dynamic scheduling. Readers looking for novel results, performance data, or formal validation will not find them here.

I would send it to peer review in an education or tools track because the description is clear and the long classroom history is real evidence of utility. In a standard research venue it would be a weaker fit.

Referee Report

0 major / 1 minor

Summary. The manuscript describes FREESS, a web-based open-source educational simulator for a RISC-V-inspired superscalar processor with Tomasulo-style dynamic scheduling. It provides a compact, cycle-by-cycle view of register renaming, issue, execution, write-back, commit, and memory ordering, exposing the register map, free pool, instruction window, reorder buffer, and load/store queues in one textual representation. Runtime parameters such as issue width, queue sizes, and functional-unit latencies can be changed to compare superscalar organizations. The tool has supported Advanced Computer Architecture teaching for about fifteen years and is publicly available on GitHub.

Significance. If the simulator's internal model matches the described behaviors, FREESS provides a practical educational resource for visualizing instruction-level parallelism and Tomasulo structures. The open-source GitHub release and fifteen years of documented classroom deployment are explicit strengths that support reproducibility and direct auditing by users.

minor comments (1)

The abstract states that the tool 'exposes' multiple hardware structures in one textual representation, but the manuscript would benefit from including at least one concrete cycle-by-cycle example trace (with parameter settings) to illustrate the claimed compactness and reproducibility on paper.

Simulated Author's Rebuttal

0 responses · 0 unresolved

We thank the referee for the thorough summary of the manuscript and for the recommendation to accept. The report contains no major comments.

Circularity Check

0 steps flagged

No significant circularity; tool-description paper with no derivations

full rationale

The manuscript is a description of an open-source educational simulator (FREESS) exposing Tomasulo-style structures in a RISC-V-inspired processor. No equations, predictions, fitted parameters, or load-bearing derivations appear in the abstract or stated claims. The central assertions concern the tool's UI features, parameter configurability, GitHub availability, and fifteen years of classroom use; these are externally verifiable and do not reduce to self-definition or self-citation chains. No steps match any enumerated circularity pattern.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 0 invented entities

No mathematical models, fitted parameters, or new physical entities are introduced; the paper is a software tool description.

pith-pipeline@v0.9.1-grok · 5669 in / 944 out tokens · 31008 ms · 2026-07-01T15:54:20.611486+00:00 · methodology

discussion (0)

Reference graph

Works this paper leans on

5 extracted references · 4 canonical work pages

[1]

Tomasulo

Robert M. Tomasulo. An efficient algorithm for exploiting multiple arithmetic units.IBM Journal of Research and Development, 11(1):25–33, 1967

1967
[2]

FREESS: An educational simulator of a RISC-V-inspired superscalar processor based on tomasulo’s algorithm

Roberto Giorgi. FREESS: An educational simulator of a RISC-V-inspired superscalar processor based on tomasulo’s algorithm. InWCAE-25, pages 1–8, June 2025. doi: 10. 1145/3743646.3750018

work page arXiv 2025
[3]

Castilla, L

I. Castilla, L. Moreno, C. González, et al. Simde: An educational simulator of ilp architectures with dynamic and static scheduling.Comp. App. in Eng. Education, 15(4): 309–318, 2007. doi: 10.1002/cae.20154

work page doi:10.1002/cae.20154 2007
[4]

S. Wolff. Satsim: A superscalar architecture trace simulator using interactive visualization. InISCA-WCAE’00, pages 1– 7, New York, NY, USA, 2000. ACM. doi: 10.1145/1275240. 1275249

work page doi:10.1145/1275240 2000
[5]

J. Jaros. Web-based simulator of superscalar risc-v proces- sors. InICS’24, pages 1–6, Piscataway, NJ, USA, 2024. IEEE. doi: 10.1109/SCW63240.2024.00209. 2 RISC-V Summit Europe, Bologna, 8-12th June 2026

work page doi:10.1109/scw63240.2024.00209 2024

[1] [1]

Tomasulo

Robert M. Tomasulo. An efficient algorithm for exploiting multiple arithmetic units.IBM Journal of Research and Development, 11(1):25–33, 1967

1967

[2] [2]

FREESS: An educational simulator of a RISC-V-inspired superscalar processor based on tomasulo’s algorithm

Roberto Giorgi. FREESS: An educational simulator of a RISC-V-inspired superscalar processor based on tomasulo’s algorithm. InWCAE-25, pages 1–8, June 2025. doi: 10. 1145/3743646.3750018

work page arXiv 2025

[3] [3]

Castilla, L

I. Castilla, L. Moreno, C. González, et al. Simde: An educational simulator of ilp architectures with dynamic and static scheduling.Comp. App. in Eng. Education, 15(4): 309–318, 2007. doi: 10.1002/cae.20154

work page doi:10.1002/cae.20154 2007

[4] [4]

S. Wolff. Satsim: A superscalar architecture trace simulator using interactive visualization. InISCA-WCAE’00, pages 1– 7, New York, NY, USA, 2000. ACM. doi: 10.1145/1275240. 1275249

work page doi:10.1145/1275240 2000

[5] [5]

J. Jaros. Web-based simulator of superscalar risc-v proces- sors. InICS’24, pages 1–6, Piscataway, NJ, USA, 2024. IEEE. doi: 10.1109/SCW63240.2024.00209. 2 RISC-V Summit Europe, Bologna, 8-12th June 2026

work page doi:10.1109/scw63240.2024.00209 2024