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REVIEW 4 major objections 5 minor 36 references

High-Level Surface Code Decoding via Parallel FFNNs on CIM Platforms

T0 review · 4 major / 5 minor · reviewed 2026-08-12 · deepseek-v4-flash

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Pith's one-line read A fully feedforward high-level surface-code decoder can run both modules in parallel on compute-in-memory hardware, reaching a 14.22% decoding threshold and sub-440-nanosecond latencies for distances 3 through 9.

desk verdict Useful engineering result on CIM-based parallel FFNN decoding, but the headline threshold is inherited from PED and needs stability checks at larger distances. read the letter →

arxiv 2411.18090 v2 pith:3LGWQOCW submitted 2024-11-27 cs.AR

Hao Wang , Erjia Xiao , Wenbo Mu , Songhuan He , Zhongyi Ni , Lingfeng Zhang , Xiaokun Zhan , Yifei Cui
show 4 more authors
Jinguo Liu Cheng Wang Zhongrui Wang Renjing Xu
This is my paper · ORCID
classification cs.AR
keywords surfacecodedecodingquantumerrorcorrectionfeedforwardneuralnetworkhigh-leveldecodercomputing-in-memorylatencythresholdcryogenicelectronics
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper's central claim is that a high-level surface-code decoder built entirely from feedforward neural networks does not have to run serially. By training one small FFNN to imitate a pure-error decoder and running it alongside a second FFNN classifier on a computing-in-memory (CIM) platform, the two modules execute in parallel, so total latency is set by the slower module rather than their sum. Under a depolarizing noise model the decoder reaches a 14.22% threshold, above the 10.3% minimum-weight perfect matching (MWPM) baseline, with pseudo-thresholds of 10.4% to 12% and simulated latencies of 197 to 252 ns for distances 3, 5, 7, and 9 at room temperature. A 4K cryogenic extrapolation lowers the distance-9 latency to 221 ns. If these numbers hold on real hardware, fully neural decoders become competitive with matching-based decoders on the two metrics that matter for real-time quantum error correction: accuracy and speed.

What carries the argument

The load-bearing object is a pair of two-layer feedforward neural networks—a simple decoder and a classifier—each mapping the error syndrome to a fixed-category output, executed in parallel as matrix-vector multiplications on NVM-based compute-in-memory crossbars. A Pure Error Decoder (PED) is used only offline to generate training labels, converting syndrome-to-correction into a one-to-one classification task; the FFNN simple decoder learns to reproduce PED's output, so the decoder keeps PED-level accuracy while dropping PED from the latency path. Parallelism is what breaks the serial bottleneck: latency is max(t_simple, t_classifier), not t_simple + t_classifier. The CIM simulation supplies the hardware parameters—digital frequency, buffer bitwidth, inter-tile and intra-tile bandwidth, and number of ADC/DACs—and captures non-idealities such as stuck-at-faults, finite on/off ratio, and resistance variation.

What would settle it

Measure the distance-9 decoder on an actual NVM-based CIM accelerator at 4 K with a 0.4 V supply: if end-to-end latency is above 221 ns, or if total power cannot be removed by the cryostat at 4 K, the cryogenic latency claim fails. Simpler still, rerun the same simulation with any one hardware parameter moved from its maximum to a conservative typical value, such as 1 GHz digital frequency or 64 GB/s inter-tile bandwidth, and check whether latency crosses 440 ns.

Watch

Extended reading notes

Core claim

The paper establishes that replacing the non-neural simple decoder in a high-level decoder with an FFNN trained on labels generated by a Pure Error Decoder (PED) preserves the PED's decoding accuracy while making the whole decoder parallel and hardware-mappable. The classifier and simple decoder both take the same error syndrome as input and emit respectively the logical error and the data-qubit correction; because neither depends on the other's output, they can run concurrently. On an NVM-based CIM simulator configured with maximum currently available hardware parameters, the decoder achieves a threshold of 14.22% under depolarizing noise and pseudo-thresholds of 10.4%, 11.3%, 12%, and 11.6% at distances 3, 5, 7, and 9. The simulated latencies are 197.03 ns, 234.87 ns, 243.73 ns, and 251.65 ns at 300K, all below the 440 ns real-time decoding budget; applying cryogenic scaling from a published CIM study at 4K and 0.4 V gives 221.07 ns at distance 9 with 3.98W power. Hardware non-idealities modeled by the simulator change the results by less than 0.5% at the chosen network sizes.

Load-bearing premise

The central assumption is that a single real CIM chip can simultaneously run at the maximum values assumed for every hardware parameter (about 2 GHz digital clock, 256 GB/s inter-tile bandwidth, 19,600-bit buffers, and up to 256 ADC/DACs) and that the published 300K-to-4K scaling of a smaller cryogenic CIM chip transfers unchanged to a decoder that dissipates about 4 W at distance 9.

Editorial extensions

If this is right

  • Distance-3 to distance-9 decoders all complete in under 440 ns at 300K simulation, so a fully neural high-level decoder can meet the real-time QEC pace instead of only offline analysis.
  • The 14.22% decoding threshold exceeds the 10.3% MWPM baseline under depolarizing noise, and pseudo-thresholds stay above 10% for every tested distance.
  • Because PED is removed from the runtime path, latency growth with code distance is governed by the FFNN and CIM array sizes, not by exponential lookup or matching growth.
  • At 4K and 0.4V, the distance-9 latency drops to 221.07 ns and power to 3.98W, supporting the idea that such a decoder could sit inside a cryogenic quantum control stack.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • The decoder's logical accuracy is inherited from the PED rule used to label training data; the FFNN contribution is hardware acceleration and parallelization, so the 14.22% threshold should be read as 'PED accuracy, made fast,' not as a new decoding algorithm.
  • The room-temperature and 4K latency numbers assume a single chip simultaneously sustains the maximum values of all five hardware parameters; a real system will likely trade some of them off, so the 440 ns margin should be tested under parameter sweeps rather than only at the maxima.
  • If the same parallelization is applied to larger distances, the classifier and simple-decoder network widths would grow roughly with distance; whether the 4K cooling budget of a few watts can absorb that growth is an open question the paper does not answer.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

4 major / 5 minor

Summary. The paper proposes a parallel fully feedforward neural network (FFNN) high-level decoder for surface codes, in which both the simple decoder and the classifier are two-layer FFNNs trained on labels generated by the Pure Error Decoder (PED). The decoder is evaluated under a depolarizing noise model for distances 3, 5, 7, and 9, and its latency is simulated with the MNSIM 2.0 computing-in-memory (CIM) platform. The authors claim a decoding threshold of 14.22%, pseudo-thresholds of 10.4%, 11.3%, 12%, and 11.6% for d=3, 5, 7, and 9, and sub-440 ns latencies on an NVM-based CIM architecture, with results extrapolated to a 4 K cryogenic environment.

Significance. If the threshold and latency claims are substantiated, the architectural contribution is significant: it would be the first demonstration of a fully neural-network high-level surface code decoder whose two modules run in parallel, and the first CIM-based evaluation of such a decoder with sub-440 ns latency. The use of MNSIM 2.0 to analyze hardware non-idealities and the discussion of hardware parameter impacts are useful for the quantum error correction architecture community. However, the headline accuracy numbers are inherited from the PED teacher rather than derived from the FFNN itself, and the threshold estimate relies on a small range of code distances; the significance is therefore conditional on additional validation.

major comments (4)
  1. [IV-C, Fig. 6(a)] The claimed 14.22% decoding threshold is determined from only four distances (3, 5, 7, 9) and a single training physical error rate p_train=0.15. The claimed threshold lies only 0.8 percentage points from p_train, and the pseudo-thresholds are non-monotonic (12% at d=7 vs. 11.6% at d=9), so the crossing in Fig. 6(a) has not been shown to be stable against finite-size effects. A genuine decoding threshold should persist to larger distances; the authors should add d=11 and d=13 results (even with reduced sample counts) and a sensitivity check over p_train in, say, [0.12, 0.18]. Without such evidence, the statement that the decoder 'surpasses MWPM' at threshold is not supported by the data presented.
  2. [Table III] Table III mixes decoder thresholds with pseudo-thresholds. The column labeled Dth lists 14.22% for Ours next to '>12.49%' for PED+NN [14] and '>12.45%' for LUT+NN [2], which are pseudo-thresholds, while the MWPM entries 1.81% and 2.90% are thresholds under different noise models (self-modified and circuit-level, respectively). The 10.3% MWPM baseline quoted in the abstract appears nowhere in the table. A credible comparison requires a single noise model, a single metric, and separate columns for threshold and pseudo-threshold.
  3. [III-C] The paper states that 'the actual decoding rules match the PED-based high-level decoder', which means the 14.22% threshold is inherited from the PED teacher, not independently established by the FFNN. To substantiate the headline threshold as an FFNN property, the authors should quantify the FFNN-versus-PED output disagreement as a function of physical error rate across the full test range [0.03, 0.3], especially for p>0.15 where high-weight syndromes are rare in training. The '<0.5%' non-ideality impact reported in Fig. 6(e) is a hardware non-ideality measure and does not address this student-teacher divergence.
  4. [IV-C, 4K Cryogenic Environment; Table I] The 4K extrapolation applies the cooling-derived latency reduction of [36] to the entire decoder, but Table III reports 3.98W total power at d=9 and 0.4V, and the paper does not explain how this power is managed at 4K given the limited cooling power typical of cryostats for quantum processors. Moreover, Table I sets each of the five main hardware parameters to maxima taken from different sources (2GHz digital frequency, 256 GB/s inter-tile bandwidth, 19600-bit buffer, 256 ADC/DACs); no evidence is given that these values can be co-satisfied in a single CIM system. The sub-440ns latency claim should be presented as an optimistic upper-bound configuration and supplemented with an analysis of a realistic combined configuration.
minor comments (5)
  1. [Abstract] The abstract in the submission metadata includes the phrase 'surpassing the MWPM baseline of 10.3%', but the abstract in the paper body omits it; please reconcile the two versions.
  2. [Fig. 1] Figure 1 is difficult to read: the 'd=3' annotation and the Chinese characters appear to be artifacts of the source, and the legend is not self-contained. Please clean up the figure.
  3. [Throughout] There are several typos, including 'Suface code' in the Section III heading, 'it is easy to implement' in the Introduction, 'constructe' in Section III-C, and 'Larency' in the Fig. 6 legend.
  4. [Table II] For d=9, the simple decoder has larger area and power (479.34 mm^2, 4.23 W) than the classifier (296.93 mm^2, 2.94 W) despite the classifier having a larger hidden-layer multiplier (n=80 vs. n=35). A sentence explaining this in terms of the output layer size (4*d^2 vs. 4 neurons) would help the reader.
  5. [IV-A] The authors state that open-source code is provided in [14], but it is not clear whether the training and testing code of this paper will be released; please clarify the code availability statement.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: the FFNN is a disclosed distillation of the external PED decoder, and the reported threshold and latency are measured outputs rather than fitted inputs.

full rationale

The paper's only apparent circularity risk is that the FFNN simple decoder and classifier are trained to reproduce the outputs of the PED-based high-level decoder of [14]. The text is explicit: 'we employed the PED-based simple decoder from [14] to generate training data for our NN-Based simple decoder' and 'Since the actual decoding rules match the PED-based high-level decoder, our decoder maintains the superior decoding performance of the PED-based high-level decoder.' This means the 14.22% threshold is inherited from PED rather than independently derived from the FFNN architecture. However, this is not circular in the analyzer's sense. PED is an external, open-source reference decoder, not a claim of the present paper. The network weights are fitted to syndrome-to-error labels, not to the threshold value; the threshold is obtained from logical-error-rate simulations across p in [0.03, 0.3], and no equation defines the threshold in terms of the training labels. The latency and energy numbers come from MNSIM 2.0 with explicitly listed hardware parameters and are not self-referential. No load-bearing self-citation chain exists: [14] is by other authors, and MNSIM 2.0 is an external simulator whose non-ideality defaults are validated against real chips. The paper also discloses its own limitation, stating in the conclusion that 'Future research could explore the decoder's performance at greater distances,' which is a generalization concern rather than a circularity. The finite-distance threshold stability at d=3 to 9 is a correctness risk, not a circularity risk.

Assumptions & free parameters 8 free parameters · 4 assumptions · 0 invented entities

No new physical entities are introduced. The central claims rest on the PED target, the depolarizing noise model, MNSIM 2.0 simulator fidelity, optimistic hardware parameter choices, and hand-chosen network sizes.

free parameters (8)
  • NN-Based classifier hidden layer multiplier n = 20 (d=3), 40 (d=5), 60 (d=7), 80 (d=9)
    Chosen by hand in Section IV.B to balance accuracy under hardware non-idealities against latency; n=35 was needed to keep classifier accuracy at 99.9% under non-idealities.
  • NN-Based simple decoder hidden layer multiplier n = 5 (d=3), 15 (d=5), 25 (d=7), 35 (d=9)
    Chosen by hand in Section IV.B; the simple decoder matches PED output nearly 100%, so smaller n suffices.
  • Training physical error rate = 0.15
    Fixed training error rate per dataset guidelines from [2],[14]; the test range is 0.03-0.3, so training at one point is a modeling choice that affects the threshold and pseudo-threshold measurements.
  • Digital Frequency = 1500 MHz (max 2000 MHz)
    Latency decreases with frequency; the paper sets this to a maximum value, which directly supports the sub-440ns claim.
  • Inter-Tile Bandwidth = 1000-1500 Gbps
    Set to maximum values based on Tesla Dojo [30]; higher bandwidth lowers data transfer time in the latency model.
  • Intra-Tile Bandwidth = 600-1000 Gbps
    Set to maximum values to minimize intra-tile communication latency.
  • Buffer Bitwidth = 2000-11000 bits
    Based on NVIDIA HBM [31]; larger bitwidth reduces buffer read/write latency.
  • Number of ADC/DAC = 64-256
    Maximum 256 per 256x256 crossbar; more ADC/DACs speed up analogue-to-digital conversion in the CIM array.
assumptions (4)
  • domain assumption Depolarizing noise model with physical error rates 0.03-0.3
    Dataset generation follows [2] and [14]; all threshold and pseudo-threshold claims are specific to this noise model.
  • domain assumption PED decoder from [14] provides the correct target mapping for the simple decoder
    Section III.C: training data for the NN simple decoder is generated by PED; the threshold claim inherits PED's accuracy.
  • domain assumption MNSIM 2.0 faithfully models CIM hardware including non-idealities (stuck-at-faults, on/off ratio, resistance variations)
    Section IV.C: latency, power, and non-ideality impact are all produced by MNSIM 2.0 with default non-idealities [20],[32],[33].
  • domain assumption Cryogenic scaling from [36] extrapolates to the proposed CIM decoder
    Section IV.C '4K Cryogenic Environment': latency decreases ~12.15%, energy unchanged from 300K to 4K, and 0.4V reduces energy ~43%, applied without accounting for the 3.98W power level at d=9.

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Pith. "Pith review of High-Level Surface Code Decoding via Parallel FFNNs on CIM Platforms." pith.science (2026). https://pith.science/paper/3LGWQOCW

@misc{pith2026241118090,
  author       = {Pith},
  title        = {Pith review of: High-Level Surface Code Decoding via Parallel FFNNs on CIM Platforms},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/3LGWQOCW}},
  note         = {Machine review of arXiv:2411.18090}
}
read the original abstract

Due to the high sensitivity of qubits to environmental noise, which leads to decoherence and information loss, active quantum error correction(QEC) is essential. Surface codes represent one of the most promising fault-tolerant QEC schemes, but they require decoders that are accurate, fast, and scalable to large-scale quantum platforms. In all types of decoders, fully neural network-based high-level decoders offer decoding thresholds that surpass baseline decoder-Minimum Weight Perfect Matching (MWPM), and exhibit strong scalability, making them one of the ideal solutions for addressing surface code challenges. However, current fully neural network-based high-level decoders can only operate serially and do not meet the current latency requirements (below 440 ns). To address these challenges, we first propose a parallel fully feedforward neural network (FFNN) high-level surface code decoder, and comprehensively measure its decoding performance on a computing-in-memory (CIM) hardware simulation platform. With the currently available hardware specifications, our work achieves a decoding threshold of 14.22%, surpassing the MWPM baseline of 10.3%, and achieves high pseudo-thresholds of 10.4%, 11.3%, 12%, and 11.6% with decoding latencies of 197.03 ns, 234.87 ns, 243.73 ns, and 251.65 ns for distances of 3, 5, 7 and 9, respectively. The impact of hardware parameters and non-idealities on these results is discussed, and the hardware simulation results are extrapolated to a 4K quantum cryogenic environment.

Figures

Figures reproduced from arXiv: 2411.18090 by the authors.

Figure 1
Figure 1. Comparison of distance = 9 (except for special annotations) surface code decoder performances. The datasets—Dataset1, Dataset2, and Dataset3—represent the data from the Circuit-Level Noise Model, the Modified Depolarizing Noise Model, and the Depolarizing Noise Model, respectively. Several decoders, such as Union Find (UF) [9], Look￾Up Table (LUT) [10], Neural Network (NN)-based [11]–[15], Minimum-Weight Perfect Mat… view at source ↗
Figure 2
Figure 2. Distance = 5 Surface Code Structure. (a) Two-Dimensional Schematic of the Surface Code; (b) X-Ancillas Circuits; (c) Z-Ancillas Circuits. Fully NN-based high-level decoders offer improved scalabil￾ity but have yet to meet the desired decoding performance and latency. [11] introduced an LSTM-based simple decoder but did not report decoding latency or threshold. [19] implemented FFNN/CNN-based simple decoders, achievi… view at source ↗
Figure 3
Figure 3. Schematic of NN-Based Neural Network Decoders. (a) Low-Level Decoder; (b) High-Level Decoder (HD); (c) Example of a High-Level Decoder for Distance = 5 surface code. multiple combinations of data qubit errors can produce the same error syndrome, the decoder can only output the most likely correction operation, making this computation NP-hard [17]. MWPM is the most commonly used quantum decoder [16] [22] [23]. B. NN-… view at source ↗
Figures from the paper (3 more)
Figure 4
Figure 4. Figure 4: Structure of the Parallel fully NN-Based High-Level Decoder and CIM Simulator.(a) Our Parallel fully NN-Based High-Level Decoder; (b) MNSIM 2.0 Simulator Architecture(Adapted from [20]); (c) NVM-Based Array for MNSIM; (d) SRAM-Based Array for MNSIM. FFNN Neural Network…
Figure 5
Figure 5. Figure 5: (a) Decoder Training Process; (b) Decoding Thresholds and Pseudo-Thresholds; (c) Impact of NN Model Size on the Classifier; (d) Impact of NN Model Size on the Simple Decoder [PITH_FULL_IMAGE:figures/full_fig_p005_5.png]
Figure 6
Figure 6. Figure 6: Decoder hardware performance. (a) NN-Based classifier results; (b) Relationship between 5 hardware parameters and latency; (c) NN-Based simple decoder results; (d) Proportion of each hardware parameter in total latency and energy; (e) Maximum impact of hardware non-ide…

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