Typed states for the displayed outbound observations.
Source: paper_references, paper_reference_links
Paper Citation Record · LEDGER
VeriDebug: A Unified LLM for Verilog Debugging via Contrastive Embedding and Guided Correction
As of 7 August 2026, this Paper Citation Record lists 0 of 0 outbound references and 3 inbound Pith citation observations for arXiv:2504.19099.
A citation records a reference. It does not transfer a finding from one paper to another.
Coverage vector
One-hop event checks from named stored sources.
Source: scholarly_work_events, retraction_status_cache, observed 2026-08-07T06:34:17.273281+00:00
Pith citing papers itemized under the disclosed page cap.
Source: paper_references, paper_reference_links, observed 2026-08-07T13:20:54.735772Z
A source-named dated measurement, never combined with another source.
Source: pith, observed 2026-08-05T05:50:30.043766Z
Reference resolution
0 of 0 outbound references displayed
- verified exact0
- verified fuzzy0
- unresolved0
- parse uncertain0
- malformed identifier0
- metadata mismatch0
External citation measurements
No source-named external measurement is stored.
Outbound references
No outbound reference observations are available for this paper version.
Pith citing papers
Observation af6188d9-7e3b-4024-8183-14dbc35767fe · inbound
iDSE: Navigating Design Space Exploration in High-Level Synthesis Using LLMs cites this paper.
iDSE: Navigating Design Space Exploration in High-Level Synthesis Using LLMs VeriDebug: A Unified LLM for Verilog Debugging via Contrastive Embedding and Guided Correction
Reference 57
- Resolution
- unresolved
- no resolver link, observed 2026-08-07T13:20:54.735772Z
Source-reported events for the cited work
Unavailable: canonical work link unavailable.
Observation 7504df44-2fe8-492d-ae16-599cfe940c0e · inbound
SV-LLM: An Agentic Approach for SoC Security Verification using Large Language Models cites this paper.
SV-LLM: An Agentic Approach for SoC Security Verification using Large Language Models VeriDebug: A Unified LLM for Verilog Debugging via Contrastive Embedding and Guided Correction
Reference 75
- Resolution
- unresolved
- no resolver link, observed 2026-08-06T22:55:09.365872Z
Source-reported events for the cited work
Unavailable: canonical work link unavailable.
Observation be6ce78f-e184-4b37-b94d-94f4063a2c1d · inbound
Revolution or Hype? Seeking the Limits of Large Models in Hardware Design cites this paper.
Revolution or Hype? Seeking the Limits of Large Models in Hardware Design VeriDebug: A Unified LLM for Verilog Debugging via Contrastive Embedding and Guided Correction
Reference 38
- Resolution
- verified exact
- local_arxiv, observed 2026-08-05T05:50:30.148024Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.