REVIEW 3 major objections 6 minor 1 cited by
SOGRAND decoding of LDPC codes
T0 review · 3 major / 6 minor · reviewed 2026-07-11 · grok-4.5
Pith's one-line read Specializing SOGRAND to single-parity-check codes yields two hardware-friendly check-node updates that match or beat sum-product and normalized min-sum on 5G LDPC codes.
desk verdict Solid, modest engineering paper: two concrete SPC CN updates from SOGRAND that match SPA/NMS on 5G LDPC with small fixed tables; useful for VLSI people, not a foundational shift. read the letter →
The pith
A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.
The reading
What carries the argument
The two SOGRAND check-node formulae (equations 5 and 6): a short list L of ORBGRAND noise patterns of correct parity is scored by channel likelihood; residual probability mass is apportioned according to the per-bit hard decisions; the resulting block posteriors are marginalized to produce each bit’s APP LLR, from which the extrinsic message is obtained by subtraction and damping.
What would settle it
Re-run the same 5G NR LDPC simulations (n=256 rate-1/2 and n=1024 rate-2/3) with L=10 and α=0.9; if either SOGRAND rule produces a clear BLER or BER gap of more than a few tenths of a decibel relative to SPA or normalized min-sum at any operating point of interest, the central performance claim is refuted.
Extended reading notes
Core claim
When SOGRAND’s soft-output formula is restricted to single-parity-check codes, the resulting check-node update (either the even-parity version that needs the Gallager parity probability Ψ or the non-even version that simply doubles the list size) yields extrinsic LLRs whose iterative decoding performance on 5G LDPC codes equals or exceeds that of the classical sum-product algorithm and of normalized min-sum, provided the list contains roughly ten noise patterns and a mild global damping factor α ≈ 0.9 is applied.
Load-bearing premise
That a fixed table of only the seven or eight least-reliable bit flips, damped by a single global factor, is enough to keep the quality of the extrinsic messages equal to exact sum-product across the practical SNR range.
Editorial extensions
If this is right
- LDPC decoders can replace the classical check-node arithmetic with a short, parallel table-driven SOGRAND update without loss of error-rate performance.
- Because the update re-uses existing ORBGRAND pattern generators already fabricated for soft GRAND chips, the same silicon can serve both universal soft decoding and LDPC check-node processing.
- The even and non-even variants give designers a concrete trade-off: compute the Gallager parity probability once and use L patterns, or skip that probability and double the list size.
- The same specialization technique can be applied to other short even component codes that appear in product, staircase or OFEC constructions.
Reading between the lines
- If the residual-mass term in the SOGRAND formulae is replaced by a more accurate estimate of the unqueried probability, the required list size may drop below eight, further simplifying the hardware.
- Because SOGRAND already produces block-wise soft output, the same check-node engine can be reused without redesign for hybrid decoding of product codes that mix LDPC and other component codes.
- The method opens a path to joint multi-check-node updates that score a single noise list against several parity checks at once, potentially reducing message-passing iterations.
Signed reviews
Editorial analysis
A structured set of objections, weighed in public.
Referee Report
Summary. The paper specializes Soft-Output GRAND (SOGRAND) to single-parity-check (SPC) component codes and derives two explicit check-node (CN) update rules for iterative LDPC decoding (Eqs. 5 and 6). One rule exploits the even-code property of SPCs (requiring the parity likelihood Ψ of Eq. 3) while the other does not; both produce extrinsic LLRs from a short list of ORBGRAND noise patterns. With list size L ≈ 8–10 and a global damping factor α = 0.9, simulations on two 5G NR LDPC codes (n = 256 rate-1/2 and n = 1024 rate-2/3) over BPSK-AWGN show block- and bit-error rates that match or slightly improve upon Gallager SPA and normalized min-sum (Imax = 50). The authors argue that the updates are hardware-friendly because existing GRAND circuits already evaluate the needed likelihoods and fixed pattern tables in a few clock cycles.
Significance. If the reported performance holds more broadly, the work supplies a genuinely alternative CN philosophy: block-wise SOGRAND posteriors are marginalized rather than computing leave-one-out tanh products or min-sums. The algebraic specialization from the general SOGRAND formula (Eqs. 1/4) to the SPC APP expressions is short and correct, the even/non-even variants are shown to be equivalent, and the empirical match to SPA/NMS with only L ≈ 10 patterns is practically interesting. Hardware friendliness is made plausible by reference to already-fabricated GRAND chips. The free parameters (α, L, fixed pattern table) are ordinary engineering knobs whose modest sensitivity is acknowledged. The contribution is therefore a clean, usable algorithmic alternative rather than a fundamental capacity or complexity breakthrough.
major comments (3)
- Section V and Figs. 2–6 evaluate only two 5G NR LDPC codes. While the BLER/BER curves support the claim for these instances, the abstract and introduction present the CN updates as a general alternative to SPA/NMS. At least one additional irregular or higher-rate 5G base-graph code (or a classical regular ensemble) is needed to substantiate that the same small L and fixed ORBGRAND table remain competitive across the practical design space.
- The fixed ORBGRAND pattern table (Fig. 1) and the single global damping α = 0.9 are purely empirical. The paper reports that α ∈ [0.8,1] changes performance by only ~0.05 dB (data not shown) and that L ≥ 8 saturates, yet no analysis is given of why the particular 7–8 least-reliable-bit patterns suffice across SNR. A short ablation (different pattern generators, SNR-dependent L, or per-check α) would clarify whether the observed match to SPA is robust or fortuitous for the two tested codes.
- Hardware claims (Section IV, final paragraph) rest entirely on citations to prior GRAND ASICs that compute likelihoods and pattern lookups in 1–3 cycles. No gate-count, critical-path, or area comparison against a standard SPA or NMS CN is supplied for the proposed updates themselves. A brief complexity table (operations per CN, memory for the pattern table, estimated latency) would make the “hardware-friendly” assertion quantitative rather than referential.
minor comments (6)
- Abstract and Introduction: the phrase “alternative existing Check Node (CN) update” is awkward; “alternative to existing CN updates” is clearer.
- Eq. (5) multiplies the residual probability mass by a factor of 2; a one-sentence justification (or a pointer to the non-even SOGRAND derivation) would help readers who have not memorized the earlier paper.
- Section V: “data not shown” for the α-sensitivity study should be replaced by a short table or inset, given that α is a free parameter of the algorithm.
- Fig. 1 caption and surrounding text: clarify whether the same fixed table is used for every check degree or whether degree-dependent tables are required for irregular 5G graphs.
- References: several recent hardware-oriented LDPC CN approximations (e.g., adjusted min-sum variants) are omitted; a brief comparison or citation would situate the work more completely.
- Notation: λ^n and N^n are used for both vectors and their components; a consistent bold/vector convention would improve readability.
Circularity Check
Minor self-citation of the SOGRAND soft-output formula from overlapping authors; the specialization to SPC CN updates and the empirical SPA/NMS comparisons are independent and not forced by construction.
-
self citation load bearing
[Section III, eqs. (1) and (4); citation [20]]
"A detailed derivation of SOGRAND's SO formula can be found in [20]. Here, we solely recapitulate the algorithmic result. ... the blockwise soft output is the a posteriori probability that bxn,ql is the transmitted codeword is pXn|Λn(bxn,ql|λn)≈..."
The soft-output expressions that are later specialized to obtain the CN updates are taken wholesale from a prior paper whose author list overlaps with the present one. While the subsequent algebraic specialization and the empirical comparisons against SPA/NMS are independent, the accuracy premise of the SO formula itself rests on that self-citation rather than a re-derivation or external verification inside this manuscript.
full rationale
The paper takes the block-wise soft-output approximation of SOGRAND (eqs. 1 and 4) from prior work by overlapping authors and algebraically specializes it to single-parity-check codes, yielding the two CN update rules (eqs. 5 and 6). That specialization is a short, self-contained derivation that does not redefine its inputs in terms of its outputs. The free damping parameter alpha is reported to have only minor effect (order 0.05 dB) over a range and is not fitted so as to force the claimed performance; list size L is likewise an ordinary engineering choice validated by simulation. Performance claims rest on direct BLER/BER comparisons against Gallager SPA and normalized min-sum on two 5G NR LDPC codes (Figs. 2-6), which constitute independent external benchmarks. Hardware-friendliness arguments reference already-fabricated GRAND circuits but are secondary and do not underwrite the decoding-performance claim. No equation reduces to its own inputs by construction, no uniqueness theorem is imported, and no fitted quantity is relabeled a prediction. The single self-citation is therefore non-load-bearing for the central result, producing only a trivial circularity score.
Assumptions & free parameters
free parameters (2)
- alpha (extrinsic damping) =
0.9
- list size L =
8-12
assumptions (3)
- domain assumption SOGRAND block-wise soft-output formula (eq. 1 / corrected eq. 4) accurately approximates the true a-posteriori codeword probabilities from a short list of noise effects.
- standard math An SPC code is an even-parity code, so only noise patterns whose parity matches the received parity can be codewords.
- ad hoc to paper A fixed ORBGRAND-derived table of the 7-8 least-reliable bits is a sufficiently rich set of candidate noise patterns for practical SNRs.
Cite this review
Pith. "Pith review of SOGRAND decoding of LDPC codes." pith.science (2026). https://pith.science/paper/44UCD237
@misc{pith2026260704045,
author = {Pith},
title = {Pith review of: SOGRAND decoding of LDPC codes},
year = {2026},
howpublished = {\url{https://pith.science/paper/44UCD237}},
note = {Machine review of arXiv:2607.04045}
}
read the original abstract
Long forward error correction codes are typically constructed by concatenating shorter component codes that are then decoded through iterative Soft-Input Soft-Output (SISO) of their components. The recently introduced Soft Output Guessing Random Additive Noise Decoding (SOGRAND) has been shown to enable accurate SISO component decoding for a broad range of component codes. Here we establish that by specializing its SISO computation to Single Parity Check codes, SOGRAND offers an alternative existing Check Node (CN) update for decoding Low Density Parity Check codes. Simulation results demonstrate similar or better decoding performance than Gallager's sum-product algorithm and norm-min-sum, while offering two distinct low complexity, hardware friendly CN update algorithms.
Figures
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Forward citations
Cited by 1 Pith paper
-
Tail-Calibrated Soft-Output GRAND for Finite-Memory Noise-Effect Posteriors
A tail-calibrated soft-output GRAND decoder for finite-memory noise posteriors is introduced, with proven ML, unbiased missing-list estimation, and correlation-aware gains in simulations.
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