Pith. sign in

REVIEW 3 major objections 5 minor 63 references

400-Gbps/$\lambda$ Ultrafast Silicon Microring Modulator for Scalable Optical Compute Interconnects

T0 review · 3 major / 5 minor · reviewed 2026-08-05 · deepseek-v4-flash

Challenge this review Re-run · record.json Download PDF Read on arXiv ↗ Review JSON

Pith's one-line read A wafer-scale silicon microring modulator with a heavily doped narrow trench is claimed to reach 400 Gbps per wavelength, breaking the usual speed-efficiency trade-off.

desk verdict A credible high-bandwidth silicon MRM with solid low-voltage results, but the 400-Gbps/λ headline is carried by an averaged, equalized open eye and should not be taken as device capability as written. read the letter →

arxiv 2509.01555 v1 pith:4CJCOKVS submitted 2025-09-01 physics.optics physics.app-ph

Fangchen Hu , Fengxin Yu , Xingyu Liu , Aoxue Wang , Xiao Hu , Haiwen Cai , Wei Chu This is my paper · ORCID
classification physics.opticsphysics.app-ph PACS 42.79.Hp42.82.-m
keywords siliconmicroringmodulator400Gbpsperwavelengthphotonicsopticalinterconnectswafer-scaleuniformityself-biasingmodulationPAM6energy-efficientI/O
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper reports a silicon microring modulator fabricated on a 300-mm CMOS-compatible silicon photonics platform and claims it can support 400 Gbps per wavelength, the first wafer-scale silicon ring solution to claim that rate. The key is a heavily doped narrow-trench ring that deliberately lowers the optical quality factor and lowers series resistance at the same time, decoupling the usual trade-off between modulation efficiency and speed. The device runs in two modes: a zero-bias self-biasing mode for energy-efficient short-reach links, achieving error-free 32-Gbps NRZ at 0.43 Vpp and 0.97 fJ/bit, and a reverse-biased depletion mode for ultrafast scale-out links, with open eyes at 200 Gbps NRZ, 360 Gbps PAM4, and 400 Gbps PAM6. If the headline rate holds under error-counting rather than open-eye criteria, it would make CMOS-compatible silicon photonics competitive with lithium-niobate and InP modulators for next-generation AI interconnects.

What carries the argument

The central mechanism is the heavily doped narrow-trench PN junction inside the ring waveguide. By adding controlled propagation loss, the trench lowers the Q factor and raises the photon-lifetime-limited optical bandwidth; by reducing series resistance, the same geometry raises the RC-limited electrical bandwidth. This decouples the two terms in the combined electro-optic bandwidth formula 1/f_EO^2 = 1/f_ph^2 + 1/f_e^2, which is the design equation the paper uses to place the device above 100 GHz. Heavy doping also enhances the plasma-dispersion modulation efficiency and preserves spectral symmetry at zero bias, enabling distortion-free self-biasing operation.

What would settle it

Run the same 400-Gbps PAM6 transmission with a higher-bandwidth AWG above 80 GHz and a wideband receiver, then count bit errors at a forward-error-correction threshold rather than relying on an averaged open eye. If the bit-error rate cannot be met without aggressive equalization, or if the electrical and optical eyes diverge once the bench bandwidth is lifted, the device is not actually 400-Gbps capable.

Watch

Extended reading notes

Core claim

The paper's central claim is that the bandwidth-efficiency trade-off that has capped silicon microring modulators can be broken by a structural change: a symmetric, heavily doped P+N+ junction placed in a narrow-trench rib waveguide. The trench adds controlled optical loss, lowering the cavity Q factor and raising the photon-lifetime-limited bandwidth; the heavy doping lowers series resistance and increases carrier density, improving electrical bandwidth and modulation efficiency. Together these effects give an electro-optic bandwidth above 110 GHz at -3 V and roughly 80-83 GHz at zero bias, while keeping modulation efficiency at Vπ·L ≈ 0.57 V·cm. The authors demonstrate two operating regime

Load-bearing premise

The 400-Gbps-per-wavelength figure is based on open eyes after digital equalization and 16x averaging through a test bench limited to roughly 55 GHz, with no bit-error measurement at that rate; the claim assumes the microring, not the test bench or the DSP, is the limiting component.

Editorial extensions

If this is right

  • A six-channel WDM array of these depletion-mode rings would carry roughly 2.4 Tbps per fiber, and a 16-channel self-biased array about 2 Tbps, using the ring's free spectral range to set channel spacing.
  • Silicon-photonics transceivers could move from 200G PAM4 to 400G-class per-lane links without abandoning CMOS manufacturing.
  • Self-biasing mode removes the bias tee and driver circuit, so transmitter energy can approach sub-fJ/bit levels compatible with UCIe 2.0 voltage swings.
  • Wafer-level bandwidth spread of about 10 GHz across nine dies indicates the design is manufacturable rather than a one-off laboratory device.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • The decisive test is whether a wider-bandwidth AWG preserves the 400G eye; if the equalizer is currently correcting the ring's own roll-off, the practical device-limited rate is lower than claimed.
  • A bit-error-rate measurement at 400G under a forward-error-correction threshold would convert the open-eye result into a system-level claim; without it, 400G remains a modulation demonstration rather than a link specification.
  • The trench-doping approach is not obviously limited to O-band racetrack geometries; porting it to add-drop rings, C-band operation, or other resonant electro-optic materials could be a fast path to similar bandwidth gains.
Share X Bluesky LinkedIn Reddit HN

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 5 minor

Summary. The paper reports a silicon microring modulator (MRM) fabricated on a 300-mm SOI platform, using a heavily doped narrow-trench design to increase optical and electrical bandwidth while maintaining modulation efficiency. The authors report an electro-optic bandwidth exceeding 110 GHz at -3 V bias and >80 GHz at 0 V, a Vπ·L of ~0.57 V·cm, and good wafer-scale uniformity across nine dies. In a self-biasing mode, they demonstrate error-free 32-Gbps NRZ transmission over 2 km with 0.43-Vpp drive and 0.97 fJ/bit, plus error-free 80-Gbps NRZ with a 3-tap FFE. In a depletion mode, they report open eye diagrams at 200 Gbps NRZ, 360 Gbps PAM4, and 400 Gbps PAM6, claiming the first wafer-scale silicon MRM reaching 400 Gbps/λ.

Significance. If the headline 400-Gbps/λ result is established, this would be a significant advance for silicon photonic transmitters: it combines a credible >110-GHz EO response with wafer-scale manufacturability and a low-voltage, sub-fJ/bit operating mode, offering a path toward both scale-up and scale-out optical interconnects. The DC, S21, and low-voltage BER measurements are internally consistent and support the device's high-bandwidth, low-energy claims. However, the central novelty claim—the 400-Gbps/λ record—rests on open-eye measurements with heavy receiver-side equalization, averaging, and a test bench limited to ~55 GHz, without BER, FEC-threshold, or quantitative signal-quality metrics at the headline rates. The paper's own Methods section concedes that 155-Gbaud PAM4 eyes were barely discernible. The result is therefore plausible but currently underdetermined; the central claim needs either stronger evidence or a more limited statement.

major comments (3)
  1. [Fig. 5(c), Methods, Supplementary Note 3.E] The 400-Gbps/λ claim is supported only by an open PAM6 eye after 16× averaging, a 16-tap FFE, a half-baud Bessel filter, and an AWG/RF chain whose effective bandwidth is ~55 GHz. No BER, FEC-threshold margin, TDECQ, or SNR is reported for 360G PAM4 or 400G PAM6. The Methods explicitly state that 'eye openings at 155 Gbaud PAM4 were barely discernible' and that a clearer eye is expected with higher-bandwidth AWGs. Since PAM6 at 133.3 Gbaud is more SNR-hungry than PAM4 at a similar baud, this statement directly undermines the conclusion that the device—rather than the equalizer, averaging, or test bench—achieved 400 Gbps. The claim should be downgraded to 'equalized open-eye demonstration subject to test-bench limitations' or supported by quantitative link metrics (e.g., TDECQ under a defined FEC limit, or BER) at 360G/400G.
  2. [Supplementary Note 3.D, Fig. S11] The similarity between E/E and E/O/E eyes is used to argue that the MRM is not the bottleneck. This argument is not decisive because the FFE taps are re-optimized for best eye quality (Fig. S9), so an adaptive equalizer can compensate the combined MRM-plus-bench response. Matching post-equalized eyes only shows that the optical link can be made to mimic the electrical back-to-back after DSP; it does not isolate the modulator's intrinsic penalty. The authors should provide a quantitative comparison of pre-FFE SNR/TDECQ, or a channel penalty estimate, to separate modulator distortion/roll-off from AWG/connector roll-off.
  3. [Discussion, Fig. 5 caption] The claim that the device 'breaks the bandwidth–efficiency trade-off' and 'dispels the prevailing concern that silicon modulators cannot support 400 Gbps-per-wavelength' is stronger than the evidence. The device has a Q of ~1500 and a Vπ·L of 0.57 V·cm, which is competitive but not a fundamental break; the 400G demonstration is not yet validated as error-free or FEC-clean. I recommend tempering the Discussion to state that the device shows a promising path toward 400G/λ, pending link-level validation with a test bench capable of the baud rate.
minor comments (5)
  1. [Fig. 5 caption] The caption says the driving signal is amplified to '1 Vpp', while the main text and Methods state the device is driven at 2 Vpp. Please clarify the actual swing at the DUT and reconcile the voltage reported in Fig. 5(b).
  2. [Methods, Eye diagram measurements] The text states the AWG has 'nominal analog bandwidth exceeding 80 GHz' but later says the actual direct link is limited to ~55 GHz. Since Fig. S10(a) shows calibration flattening over 0–90 GHz, the discrepancy between nominal AWG bandwidth, calibrated channel response, and the 55-GHz limitation should be stated more clearly.
  3. [Supplementary Note 3.C, Fig. S9] The FFE tap count is varied only for 128 Gbaud PAM4. It would be helpful to state the number of taps used for the 180-Gbaud NRZ, 140-Gbaud PAM4, and 155-Gbaud PAM6 measurements, since the eye quality depends strongly on this choice.
  4. [Throughout] There are several typographical errors: 'MRMS' in the abstract, 'capaticance' in Fig. S2, 'out MRM' in the Methods, 'mircroring' in Table S2, and an apparent duplicate reference [19] in the reference list. Please proofread carefully.
  5. [Supplementary Table 2] The table reports line rates but does not indicate whether the cited results are BER-verified or open-eye-only. Adding a column with 'BER' or 'open eye' would help readers compare the strength of evidence across prior work and this paper.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: the 400-Gbps claim is an empirical eye-diagram result and the energy-efficiency numbers follow from independent simulated capacitance and measured drive voltage.

full rationale

The paper's central derivation chain is: device geometry → simulated Q, R, C → Eqs. (1)–(3) for optical, electrical, and EO bandwidth → measured S21. No equation is defined in terms of the headline 400 Gbps rate, and the bandwidth values are compared with, not fitted to, the measured S21. The 400-Gbps/λ claim is presented as an experimental eye-diagram observation (Fig. 5c), not as a quantity derived from an assumed result. The use of a 16-tap FFE optimized for best eye quality (Fig. S9) and 16× averaging is disclosed; this affects the strength of the evidence but is not circular, because the eye diagram is not a fitted parameter being used to predict itself. The energy-efficiency calculation (0.97 fJ/bit at 0.43 Vpp) uses the standard capacitive energy formula with a junction capacitance Cj ≈ 21 fF obtained from Synopsys process/device simulation, not fitted to the reported BER or eye results; so it is model-dependent but not circular. The only self-citation (ref. 25, Hu et al., Communications Engineering 2023) appears as a prior benchmark in a literature list and is not load-bearing; no uniqueness theorem or ansatz is imported from the authors' prior work. The Methods admission that 'Due to the limited bandwidth of the measurement setup, eye openings at 155 Gbaud PAM4 were barely discernible... It's expected to get a clearer eye diagram for 400 Gbps PAM6 signal with higher-bandwidth AWGs and improved RF components' is a genuine limitation on the 400-Gbps evidence and is flagged here, but it is a validity/correctness concern, not a circularity. Overall, the derivations and claims are self-contained against external benchmarks, with no step reducing by construction to its own inputs.

Assumptions & free parameters 2 free parameters · 4 assumptions · 0 invented entities

No new physical entities are introduced. The central quantitative results depend on two simulated capacitance values and on standard silicon-photonics assumptions (plasma dispersion, RC bandwidth, critical coupling). The energy-efficiency number is a model-based estimate, not a direct measurement.

free parameters (2)
  • Junction capacitance Cj at 0V = 21 fF (simulated)
    Used in the energy-per-bit formula to obtain 0.97 fJ/bit; not directly measured, so the headline efficiency depends on this simulated value.
  • Junction capacitance Cj at -3V = 16 fF (simulated)
    Used for depletion-mode energy estimates (e.g., 16 fJ/bit at 2 Vpp NRZ).
assumptions (4)
  • domain assumption Free-carrier plasma dispersion is the modulation mechanism and its efficiency scales with doping
    Standard silicon photonics physics; the heavy-doping design relies on it (Device design section).
  • domain assumption The fabricated doping profile matches Sentaurus Process simulation
    The paper simulates Cj, Rs, and optical loss based on process simulation; if the real doping deviates, the energy and bandwidth claims (especially Cj=21 fF) shift. Stated in Supplementary Note 1.C.
  • domain assumption Critical coupling holds at 0 V and Q=1500 from the spectrum gives the photon lifetime
    Used to relate Q to optical bandwidth via Eq. 2; the paper asserts critical coupling at 0 V based on ER diminishing in both bias directions (Fig. 3b).
  • domain assumption Modulator energy is fully captured by CV^2 charging; thermal tuning, heater power, and leakage are ignored
    The 0.97 fJ/bit and other Ebit values are calculated from Cj and Vpp only (Methods, 'Modulator energy efficiency analysis'). In a practical OIO link, heater power for wavelength stabilization is typically required, which would add to the energy budget.

how reviews work

0 comments
Cite this review

Pith. "Pith review of 400-Gbps/$\lambda$ Ultrafast Silicon Microring Modulator for Scalable Optical Compute Interconnects." pith.science (2026). https://pith.science/paper/4CJCOKVS

@misc{pith2026250901555,
  author       = {Pith},
  title        = {Pith review of: 400-Gbps/$\lambda$ Ultrafast Silicon Microring Modulator for Scalable Optical Compute Interconnects},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/4CJCOKVS}},
  note         = {Machine review of arXiv:2509.01555}
}
abstract

The exponential growth of artificial intelligence (AI) workloads is driving an urgent demand for optical interconnects with ultrahigh bandwidth, energy efficiency, and scalability. Silicon photonics, with its CMOS compatibility and wafer-scale manufacturability, has emerged as a promising platform for optical interconnect architectures. Silicon microring modulators (MRMs), with their compact footprint, low power consumption, and high modulation efficiency, have become ideal devices for modulation in interconnects. However, silicon MRMS have so far been constrained by the trade-off between modulation efficiency and bandwidth, hindering their potential for 400 Gbps-per-wavelength operation. To mitigate this trade-off, here we demonstrate a wafer-level fabricated and high-bandwidth silicon MRM with a novel heavily-doped trench-integrated structure on a 300-mm silicon photonic platform, achieving both outstanding device performance and remarkable wafer-scale uniformity. Exploiting dual operation modes: self-biasing for energy-efficient scale-up interconnects and depletion driving for ultrafast scale-out links, the device supports error-free 32-Gbps NRZ transmission over 2-km SSMF with only 0.43-Vpp drive and zero electrical bias, yielding energy efficiency of 0.97 fJ/bit without DSP. At higher swings, it further supports 280-Gbps PAM4 and error-free 80-Gbps NRZ optical modulation. For scale-out interconnects, open eye diagrams are achieved at 200 Gbps (NRZ), 360 Gbps (PAM4), and a record 400 Gbps (PAM6), establishing the first wafer-scale silicon MRM solution reaching 400 Gbps/$\lambda$. The sub-fJ/bit energy efficiency and high bandwidth demonstrated in this work establish the MRM as a scalable, high-performance solution for next-generation optical interconnect architectures in AI computing networks

Discussion (0). Continue with ORCID to comment.

Reference graph

Works this paper leans on

63 extracted references · 59 canonical work pages

  1. [1]

    Introduction The rapid advancement of modern artificial intelligence (AI), exemplified by large language models (LLMs), multimodal systems, and generative architectures, has led to exponentially increasing computational demands for efficient model training and inference1,2,3. However, the slowdown of Moore ’s Law imposes fundamental constraints on the com...

    work page

  2. [2]

    Results Device design The EO bandwidth (fEO) of silicon MRMs is fundamentally governed by three factors: the optical bandwidth (fph), determined by photon lifetimes (or equivalently, the quality factor Q) of optical mode, the electrical bandwidth ( fe), determined by RC time constants of the PN junction and metal contacts, and the wavelength detuning from...

    work page

  3. [3]

    Discussion By c o-optimizing modulation efficiency, optical bandwidth, and electrical bandwidth via a novel heavily -doped narrow trench structure, we realize a high - performance silicon MRM that breaks the bandwidth –efficiency trade-off, marking a significant advancement over previously reported silicon depletion mode MRMs. This represents the first re...

    work page

  4. [4]

    Innovations For Energy Efficient Generative AI,

    S. Naffziger, "Innovations For Energy Efficient Generative AI," in 2023 International Electron Devices Meeting (IEDM), 2023, pp. 1-4

    work page 2023

  5. [5]

    Machine Learning Model Sizes and the Parameter Gap,

    P. Villalobos, J. Sevilla, T. Besiroglu, L. Heim, A. Ho, M. Hobbhahn, “Machine Learning Model Sizes and the Parameter Gap,” arXiv: 2207.02852

    arXiv

  6. [6]

    Zero++: Extremely efficient collective communication for giant model training,

    G. Wang et al. , "Zero++: Extremely efficient collective communication for giant model training," arXiv preprint arXiv:2306.10209, 2023

    arXiv 2023

  7. [7]

    Sevilla, J. et al. Compute trends across three eras of machine learning. In 2022 International Joint Conference on Neural Networks (IJCNN) 1–8 (IEEE, 2022)

    work page 2022

  8. [8]

    A Comparison of the Cerebras Wafer -Scale Integration Technology with Nvidia GPU -based Systems for Artificial Intelligence,

    Y . Kundu et al., "A Comparison of the Cerebras Wafer -Scale Integration Technology with Nvidia GPU -based Systems for Artificial Intelligence," arXiv preprint arXiv:2503.11698, 2025

    arXiv 2025

Show all 63 references
  1. [9]

    AI Networking Challenges – A System Perspective,

    S. Amiralizadeh and J. K. Doylend, "AI Networking Challenges – A System Perspective," IEEE Journal of Selected Topics in Quantum Electronics, vol. 31, no. 3: AI/ML Integrated Opto-electronics, pp. 1-7, 2025

    2025

  2. [10]

    Disaggregated memory for expansion and sharing in blade servers,

    K. Lim, J. Chang, T. Mudge, P. Ranganathan, S. K. Reinhardt, and T. F. Wenisch, “Disaggregated memory for expansion and sharing in blade servers,” in Proc. 36th Annu. Int. Symp. Comput. Archit. New York, NY , USA: Association for Computing Machinery, Jun. 2009, pp. 267–278

    2009

  3. [11]

    Disaggregated Data Centers: Challenges and Trade-offs,

    R. Lin, Y . Cheng, M. D. Andrade, L. Wosinska, and J. Chen, "Disaggregated Data Centers: Challenges and Trade-offs," IEEE Communications Magazine, vol. 58, no. 2, pp. 20-26, 2020

    2020

  4. [12]

    Recent advances in optical technologies for data centers: a review,

    Q. Cheng, M. Bahadori, M. Glick, S. Rumley, and K. Bergman, "Recent advances in optical technologies for data centers: a review," Optica, vol. 5, no. 11, pp. 1354 -1370, 2018/11/20 2018

    2018

  5. [13]

    Roadmapping the next generation of silicon photonics,

    S. Shekhar et al. , "Roadmapping the next generation of silicon photonics," Nature Communications, vol. 15, no. 1, p. 751, 2024/01/25 2024

    2024

  6. [14]

    Mahajan, R. et al. Co-packaged photonics for high performance computing: status, challenges and opportunities. J. Lightwave Technol. 40, 379–392 (2021)

    2021

  7. [16]

    Resonant plasmonic micro-racetrack modulators with high bandwidth and high temperature tolerance,

    M. Eppenberger et al., "Resonant plasmonic micro-racetrack modulators with high bandwidth and high temperature tolerance," Nature Photonics, vol. 17, no. 4, pp. 360 -367, 2023/04/01 2023

    2023

  8. [17]

    An 8 × 160 Gb s −1 all -silicon avalanche photodiode chip,

    Y . Peng et al., "An 8 × 160 Gb s −1 all -silicon avalanche photodiode chip," Nature Photonics, vol. 18, no. 9, pp. 928-934, 2024/09/01 2024

    2024

  9. [18]

    Design Approach for Die-to-Die Interfaces to Enable Energy-Efficient Chiplet Systems,

    V . Jain et al., "Design Approach for Die-to-Die Interfaces to Enable Energy-Efficient Chiplet Systems," presented at the Proceedings of the 29th ACM/IEEE International Symposium on Low Power Electronics and Design, Newport Beach, CA, USA, 2024. [Online]

    2024

  10. [19]

    Massively scalable Kerr comb-driven silicon photonic link,

    A. Rizzo et al., "Massively scalable Kerr comb-driven silicon photonic link," Nature Photonics, 2023/06/29 2023

    2023

  11. [20]

    An ultralow power athermal silicon modulator,

    E. Timurdogan, C. M. Sorace-Agaskar, J. Sun, E. Shah Hosseini, A. Biberman, and M. R. Watts, "An ultralow power athermal silicon modulator," Nature Communications, vol. 5, no. 1, p. 4008, 2014/06/11 2014

    2014

  12. [21]

    Koch, B. R. et al. Integrated silicon photonic laser sources for telecom and datacom. In Optical Fiber Communication Conference, PDP5C–8 (Optica Publishing Group, 2013)

    2013

  13. [22]

    Three -dimensional photonic integration for ultra -low-energy, high - bandwidth interchip data links,

    S. Daudlin et al. , "Three -dimensional photonic integration for ultra -low-energy, high - bandwidth interchip data links," Nature Photonics, 2025/03/21 2025

    2025

  14. [23]

    A 64 Gb/s NRZ O -Band Ring Modulator with 3.2 THz FSR for DWDM Applications,

    C. Xie et al. , "A 64 Gb/s NRZ O -Band Ring Modulator with 3.2 THz FSR for DWDM Applications," in 2024 Optical Fiber Communications Conference and Exhibition (OFC) , 2024, pp. 1-3

    2024

  15. [25]

    Photonics for Die-to-Die Interconnects: Links and Optical I/O Chiplets

    C. Sun, “Photonics for Die-to-Die Interconnects: Links and Optical I/O Chiplets ”, in ISSCC 2024, Forum 1.7

    2024

  16. [26]

    An Error-free 1 Tbps WDM Optical I/O Chiplet and Multi-wavelength Multi- port Laser,

    M. Wade et al., "An Error-free 1 Tbps WDM Optical I/O Chiplet and Multi-wavelength Multi- port Laser," in 2021 Optical Fiber Communications Conference and Exhibition (OFC), 2021, pp. 1-3

    2021

  17. [28]

    Hu, F. et al. 300 -Gbps optical interconnection using neural -network based silicon microring modulator. Communications Engineering 2, 67, doi:10.1038/s44172-023-00115-x (2023)

    2023 doi

  18. [31]

    A 5 × 200 Gbps microring modulator silicon chip empowered by two-segment Z-shape junctions,

    Y . Y uan et al., "A 5 × 200 Gbps microring modulator silicon chip empowered by two-segment Z-shape junctions," Nature Communications, vol. 15, no. 1, p. 918, 2024/01/31 2024

    2024

  19. [32]

    Efficient 330 -Gb/s PAM-8 modulation using silicon microring modulators,

    D. W. U. Chan, X. Wu, C. Lu, A. P. T. Lau, and H. K. Tsang, "Efficient 330 -Gb/s PAM-8 modulation using silicon microring modulators," Opt. Lett., vol. 48, no. 4, pp. 1036 -1039, 2023/02/15 2023

    2023

  20. [33]

    A 240 Gb/s PAM4 Silicon Micro-Ring Optical Modulator,

    M. Sakib et al., "A 240 Gb/s PAM4 Silicon Micro-Ring Optical Modulator," in 2022 Optical Fiber Communications Conference and Exhibition (OFC), 2022, pp. 01-03

    2022

  21. [34]

    Ultra -Wide Free- Spectral-Range Silicon Microring Modulator for High Capacity WDM,

    D. W. U. Chan, X. Wu, Z. Zhang, C. Lu, A. P. T. Lau, and H. K. Tsang, "Ultra -Wide Free- Spectral-Range Silicon Microring Modulator for High Capacity WDM," Journal of Lightwave Technology, vol. 40, no. 24, pp. 7848-7855, 2022

    2022

  22. [36]

    540Gbps IMDD Transmission over 30km SMF using 110GHz Bandwidth InP EML

    Xin Chen, et al., “540Gbps IMDD Transmission over 30km SMF using 110GHz Bandwidth InP EML” Optical Fiber Communication Conference (OFC), Th4B.2, 2025

    2025

  23. [37]

    Berikaa, E. et al. TFLN MZMs and Next-Gen DACs: Enabling Beyond 400 Gbps IMDD O - Band and C -Band Transmission. IEEE Photonics Technology Letters 35, 850 -853, doi:10.1109/LPT.2023.3285881 (2023)

    2023

  24. [38]

    Han, C. et al. Exploring 400 Gbps/λ and beyond with AI-accelerated silicon photonic slow - light technology. Nature Communications 16, 6547, doi:10.1038/s41467-025-61933-5 (2025)

    2025 doi

  25. [39]

    Shen, J. et al. Highly Efficient Slow-Light Mach–Zehnder Modulator Achieving 0.21 V cm Efficiency with Bandwidth Surpassing 110 GHz. Laser & Photonics Reviews 19, 2401092, (2025)

    2025

  26. [40]

    Self-biasing of carrier depletion based silicon microring modulators,

    A. Melikyan, K. Kim, B. Stern, and N. Kaneda, "Self-biasing of carrier depletion based silicon microring modulators," Opt. Express, vol. 28, no. 15, pp. 22540-22548, 2020/07/20 2020

    2020

  27. [41]

    Müller, J. et al. Optical peaking enhancement in high-speed ring modulators. Sci. Rep. 4, 6310 (2014)

    2014

  28. [42]

    & Sheikholeslami, A

    Karimelahi, S. & Sheikholeslami, A. Ring modulator small-signal response analysis based on pole-zero representation. Opt. Express 24, 7585–7599 (2016)

    2016

  29. [43]

    Low V pp, ultralow-energy, compact, high- speed silicon electro-optic modulator,

    P. Dong, S. Liao, D. Feng, H. Liang, D. Zheng, R. Shafiiha, C. C. Kung, W. Qian, G. Li, X. Zheng, A. V . Krishnamoorthy, and M. Asghari, “Low V pp, ultralow-energy, compact, high- speed silicon electro-optic modulator,” Opt. Express 17(25), 22484–22490 (2009)

    2009

  30. [44]

    Ring resonator modulators in silicon for interchip photonic links,

    G. L. et al., “Ring resonator modulators in silicon for interchip photonic links,” IEEE J. Sel. Topics Quantum Electron., vol. 19, no. 6, pp. 95–113, Nov./Dec. 2013

    2013

  31. [45]

    Sub-volt forward-biased silicon microring modulator at 210 Gb/s,

    David W. U. Chan and Hon Ki Tsang, "Sub-volt forward-biased silicon microring modulator at 210 Gb/s," Opt. Lett. 49, 6477-6480 (2024)

    2024

  32. [46]

    8 -λ × 50 Gbps/λ Heterogeneously Integrated Si-Ph DWDM Transmitter,

    C. S. Levy et al., "8 -λ × 50 Gbps/λ Heterogeneously Integrated Si-Ph DWDM Transmitter," IEEE Journal of Solid-State Circuits, vol. 59, no. 3, pp. 690-701, 2024

    2024

  33. [47]

    Universal Chiplet Interconnect Express (UCIe): An Open Industry Standard for Innovations With Chiplets at Package Level,

    D. D. Sharma, G. Pasdast, Z. Qian, and K. Aygun, "Universal Chiplet Interconnect Express (UCIe): An Open Industry Standard for Innovations With Chiplets at Package Level," IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 12, no . 9, pp. 1423-1431, 2022

    2022

  34. [48]

    GlobalFoundries 12 LP—CMC microsystems,

    “GlobalFoundries 12 LP—CMC microsystems,” https://www.cmc.ca/globalfoundries-12-lp/

  35. [49]

    36.6 A 112Gb/s 0.61pJ/b PAM-4 Linear TIA Supporting Extended PD -TIA Reach in 28nm CMOS,

    Y . Zhang et al., "36.6 A 112Gb/s 0.61pJ/b PAM-4 Linear TIA Supporting Extended PD -TIA Reach in 28nm CMOS," in 2025 IEEE International Solid-State Circuits Conference (ISSCC), 2025, vol. 68, pp. 1-3

    2025

  36. [50]

    PCI Express® Base Specification Revision 5.0 Version 1.0, https://picture.iczhiku.com/resource/eetop/SYkDTqhOLhpUTnMx.pdf

  37. [51]

    PCI Express & PAM4: The Pathway to 128GT/s and Challenges of Building Interoperable 64GT/s Capable Systems

    Pegah Alavi, et al., “PCI Express & PAM4: The Pathway to 128GT/s and Challenges of Building Interoperable 64GT/s Capable Systems”, in DesignCon, 2024. Acknowledgements: This work is supported by Zhangjiang Laboratory. Author contributions: The concept of this work was conceive...

    2024

  38. [52]

    4 18 22.9 2670 / 30.4 90 C-band 128 (NRZ) 200 (PAM4) 1.36 Si- MRM

  39. [54]

    12 16 5.7 3700 0.6 27.3 48.6 O-band 200 (PAM4) 1.6 Si- MRM

  40. [55]

    7.5 24 / 5200 0.63 / 50 C-band 330 (PAM8) 1.8 Si- MRM

  41. [56]

    4 19 16.3 4000 0.42 / 60 O-band 240 (PAM4) 1.8 Si- MRM

  42. [57]

    References:

    3 16.5 35.7 1170 1.35 25 >110 C-band 300 (PAM4) 2 *Si-MRM: silicon microring modulator; Si-RT: Silicon micro-racetrack modulator. References:

  43. [58]

    Timurdogan, E. et al. An ultralow power athermal silicon modulator. Nature Communications 5, 4008, (2014)

    2014

  44. [59]

    Rizzo, A. et al. Massively scalable Kerr comb-driven silicon photonic link. Nature Photonics, doi:10.1038/s41566-023-01244-7 (2023)

    2023 doi

  45. [60]

    A 64 Gb/s NRZ O -Band Ring Modulator with 3.2 THz FSR for DWDM Applications,

    C. Xie et al. , "A 64 Gb/s NRZ O -Band Ring Modulator with 3.2 THz FSR for DWDM Applications," in 2024 Optical Fiber Communications Conference and Exhibition (OFC), 2024, pp. 1-3

    2024

  46. [61]

    Photonics for Die -to-Die Interconnects: Links and Optical I/O Chiplets

    C. Sun, “Photonics for Die -to-Die Interconnects: Links and Optical I/O Chiplets ”, in ISSCC 2024, Forum 1.7

    2024

  47. [62]

    A Monolithically Integrated DWDM Si-Photonics Transceiver for Chiplet Optical I/O,

    N. Qi et al., "A Monolithically Integrated DWDM Si-Photonics Transceiver for Chiplet Optical I/O," IEEE Journal of Solid-State Circuits, pp. 1-13, 2025

    2025

  48. [63]

    240 Gb/s optical transmission based on an ultrafast silicon microring modulator,

    Y . Zhang et al., "240 Gb/s optical transmission based on an ultrafast silicon microring modulator," Photon. Res., vol. 10, no. 4, pp. 1127-1133, 2022/04/01 2022

    2022

  49. [64]

    High Bandwidth and Low Driving V oltage Add-Drop Micro-Ring Modulator for Optical Interconnection I/O Chips,

    S. Zhao et al., "High Bandwidth and Low Driving V oltage Add-Drop Micro-Ring Modulator for Optical Interconnection I/O Chips," Journal of Lightwave Technology, pp. 1-9, 2025

    2025

  50. [65]

    A 290 Gbps Silicon Photonic Microring Modulator with 83 -aJ/bit Power Consumption,

    X. Wang et al., "A 290 Gbps Silicon Photonic Microring Modulator with 83 -aJ/bit Power Consumption," in Optical Fiber Communication Conference (OFC) 2025, San Francisco, California, 2025: Optica Publishing Group, p. M3K.5

    2025

  51. [66]

    A 5 × 200 Gbps microring modulator silicon chip empowered by two-segment Z-shape junctions,

    Y . Yuan et al., "A 5 × 200 Gbps microring modulator silicon chip empowered by two-segment Z-shape junctions," Nature Communications, vol. 15, no. 1, p. 918, 2024/01/31 2024

    2024

  52. [67]

    Efficient 330 -Gb/s PAM-8 modulation using silicon microring modulators,

    D. W. U. Chan, X. Wu, C. Lu, A. P . T. Lau, and H. K. Tsang, "Efficient 330 -Gb/s PAM-8 modulation using silicon microring modulators," Opt. Lett., vol. 48, no. 4, pp. 1036 -1039, 2023/02/15 2023

    2023

  53. [68]

    A 240 Gb/s PAM4 Silicon Micro -Ring Optical Modulator,

    M. Sakib et al., "A 240 Gb/s PAM4 Silicon Micro -Ring Optical Modulator," in 2022 Optical Fiber Communications Conference and Exhibition (OFC), 2022, pp. 01-03

    2022

  54. [69]

    Whispering Gallery Mode Enhanced Broadband and High-Speed Silicon Microring Modulator,

    K. Lu, H. Chen, W. Zhou, H. K. Tsang, and Y . Tong, "Whispering Gallery Mode Enhanced Broadband and High-Speed Silicon Microring Modulator," Journal of Lightwave Technology, pp. 1-7, 2025

    2025

  55. [83]

    5 23 13 26300 0.9 15 51 O-band 290 (PAM6) 224 (PAM4) 0.4 Si- MRM

Pith tools

Reviewed August 5, 2026 · model on record in the stance chip above.