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UVLLM: An Automated Universal RTL Verification Framework using LLMs

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arxiv 2411.16238 v1 pith:4ROXCK7U submitted 2024-11-25 cs.AR

Yuchen Hu , Junhao Ye , Ke Xu , Jialin Sun , Shiyue Zhang , Xinyao Jiao , Dingrong Pan , Jie Zhou
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Ning Wang Weiwei Shan Xinwei Fang Xi Wang Nan Guan Zhe Jiang
This is my paper
classification cs.AR
keywords verificationuvllmhardwarellmsassumptionsautomationdesignerror
verification ladder T0 review T1 audit T2 compute T3 formal
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Verifying hardware designs in embedded systems is crucial but often labor-intensive and time-consuming. While existing solutions have improved automation, they frequently rely on unrealistic assumptions. To address these challenges, we introduce a novel framework, UVLLM, which combines Large Language Models (LLMs) with the Universal Verification Methodology (UVM) to relax these assumptions. UVLLM significantly enhances the automation of testing and repairing error-prone Register Transfer Level (RTL) codes, a critical aspect of verification development. Unlike existing methods, UVLLM ensures that all errors are triggered during verification, achieving a syntax error fix rate of 86.99% and a functional error fix rate of 71.92% on our proposed benchmark. These results demonstrate a substantial improvement in verification efficiency. Additionally, our study highlights the current limitations of LLM applications, particularly their reliance on extensive training data. We emphasize the transformative potential of LLMs in hardware design verification and suggest promising directions for future research in AI-driven hardware design methodologies. The Repo. of dataset and code: https://anonymous.4open.science/r/UVLLM/.

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Cited by 10 Pith papers

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score.

  1. UVMarvel: an Automated LLM-aided UVM Machine for Subsystem-level RTL Verification

    cs.AR 2026-05 unverdicted novelty 7.0 of 10

    UVMarvel automatically constructs subsystem-level UVM testbenches for mainstream bus protocols using LLMs, an IR, and supporting libraries, reaching 95.65% average code coverage in 4.5 hours of automated runtime.

  2. Clover: A Neural-Symbolic Agentic Harness with Stochastic Tree-of-Thoughts for Verified RTL Repair

    cs.AR 2026-04 unverdicted novelty 7.0 of 10

    Clover fixes 96.8% of bugs on an RTL-repair benchmark using stochastic tree-of-thoughts and neural-symbolic agents, outperforming traditional and LLM baselines by 94% and 63% respectively with 87.5% pass@1.

  3. ChatSVA: Bridging SVA Generation for Hardware Verification via Task-Specific LLMs

    cs.AR 2026-04 unverdicted novelty 7.0 of 10

    ChatSVA achieves 96.12% functional pass rate and 82.5% coverage in SVA generation on 24 RTL designs, delivering 33 percentage point gains and 11x better coverage than prior state-of-the-art.

  4. LongRTL: Graph-Similarity-Guided LLM-driven Long Context RTL Optimization

    cs.AR 2026-06 unverdicted novelty 6.0 of 10

    LongRTL proposes a three-agent LLM system guided by graph similarity on ASTs to partition, optimize via multi-modal RAG, and reconstruct long RTL designs for functional equivalence.

  5. Understanding Inference-Time Token Allocation and Coverage Limits in Agentic Hardware Verification

    cs.AR 2026-04 unverdicted novelty 6.0 of 10

    Domain-specialized LangGraph agents close hardware coverage faster and with far fewer tokens than a general Codex agent, while a hole taxonomy exposes hard limits of pure LLM stimulus generation.

  6. Spec2Cov: An Agentic Framework for Code Coverage Closure of Digital Hardware Designs

    cs.AR 2026-04 unverdicted novelty 6.0 of 10

    Spec2Cov uses an LLM agent in a feedback loop with a hardware simulator to generate tests from specs, achieving 100% coverage on simple designs and up to 49% on complex ones across 26 benchmarks.

  7. From Concept to Practice: an Automated LLM-aided UVM Machine for RTL Verification

    cs.AR 2025-04 conditional novelty 6.0 of 10

    UVM^2 is an LLM-driven system that generates and refines UVM testbenches for RTL verification, reporting up to substantial time savings and average code/function coverage of 87.44%/89.58% on designs up to 1.6K lines, ...

  8. Understanding Inference-Time Token Allocation and Coverage Limits in Agentic Hardware Verification

    cs.AR 2026-04 unverdicted novelty 5.0 of 10

    Domain-specialized LLM agents for hardware verification close 95-99% coverage using 4-13x fewer tokens and 2-4x faster convergence than general-purpose agents by reallocating tokens toward coverage-directed reasoning.

  9. Spec2Cov: An Agentic Framework for Code Coverage Closure of Digital Hardware Designs

    cs.AR 2026-04 unverdicted novelty 5.0 of 10

    Spec2Cov uses an LLM-simulator feedback loop to generate tests from specs, reaching 100% coverage on simple designs and up to 49% on complex ones across 26 benchmarks.

  10. Automated SVA Generation with LLMs

    cs.AR 2026-04 unverdicted novelty 5.0 of 10

    SVA Generator improves semantic correctness of LLM-generated SystemVerilog Assertions by 22.7 percentage points on average for deeper properties using AST-grounded constraint injection and depth-stratified formal equi...

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