REVIEW 1 cited by
Modeling Noisy Quantum Circuits Using Experimental Characterization
Not yet reviewed by Pith; the record is open.
This paper has not been read by Pith yet. Machine review is queued; the pith claim, tier, and objections will appear here once it completes.
SPECIMEN: schema-true, not a live event
T0 review · schema-true
One-sentence machine reading of the paper's core claim.
pith:XXXXXXXX · record.json · timestamp
read the original abstract
Noisy intermediate-scale quantum (NISQ) devices offer unique platforms to test and evaluate the behavior of non-fault-tolerant quantum computing. However, validating programs on NISQ devices is difficult due to fluctuations in the underlying noise sources and other non-reproducible behaviors that generate computational errors. Efficient and effective methods for modeling NISQ behaviors are necessary to debug these devices and develop programming techniques that mitigate against errors. We present a test-driven approach to characterizing NISQ programs that manages the complexity of noisy circuit modeling by decomposing an application-specific circuit into a series of bootstrapped experiments. By characterizing individual subcircuits, we generate a composite model for the original noisy quantum circuit as well as other related programs. We demonstrate this approach using a family of superconducting transmon devices running applications of GHZ-state preparation and the Bernstein-Vazirani algorithm. We measure the model accuracy using the total variation distance between predicted and experimental results, and we find that the composite model works well across multiple circuit instances. In addition, these characterizations are computationally efficient and offer a trade-off in model complexity that can be tailored to the desired predictive accuracy.
Forward citations
Cited by 1 Pith paper
-
Breaking Memory Bottlenecks in Quantum Control Systems for More Precise Experiments and Higher Throughput Computing
Ant-Q pipelines quantum circuit loading, execution, and readout uplink on FPGA control boards using a DRAM plus BRAM hierarchy, supporting deep randomized benchmarking circuits and reducing classical overhead to near zero.
Discussion (0). Continue with ORCID to comment.