Is RISC-V ready for High Performance Computing? An evaluation of the Sophon SG2044

Nick Brown

REVIEW 3 major objections 6 minor 15 references

Is RISC-V ready for High Performance Computing? An evaluation of the Sophon SG2044

T0 review · 3 major / 6 minor · reviewed 2026-08-05 · deepseek-v4-flash

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Pith's one-line read The Sophon SG2044's memory and vector upgrades let RISC-V scale to 64 cores, outrunning its predecessor by up to 4.91x and closing the HPC gap on compute-bound kernels.

desk verdict First useful NPB data for the SG2044; the multi-core and memory story is credible, but the headline speedups over the SG2042 are compiler-dependent and need a controlled rerun before being used for procurement decisions. read the letter →

arxiv 2508.13840 v1 pith:5H5YNJIV submitted 2025-08-19 cs.DC

Nick Brown This is my paper · ORCID

classification cs.DC

keywords RISC-VHighPerformanceComputingSophonSG2044NASParallelBenchmarksRVVv1.0vectorisationmemorybandwidthSG2042OpenMPscaling

verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper is the first HPC-focused performance study of SOPHGO's Sophon SG2044, a 64-core RISC-V CPU aimed at workstation and server workloads. The author's central claim is that the SG2044's upgraded memory subsystem and RVV v1.0 vector support remove the bottlenecks that limited its predecessor, the SG2042, so the chip is most advantageous at high core counts: across 64 cores it delivers up to 4.91 times the performance of the SG2042, with the memory-latency-bound IS kernel benefiting most. A single C920v2 core beats all other commodity RISC-V cores tested, and on compute-bound EP the SG2044 tracks an Intel Skylake core-for-core while scaling like an AMD EPYC at high thread counts. If correct, this means RISC-V is no longer confined to embedded use: mainline GCC can auto-vectorize code and the memory subsystem can feed 64 cores, making RISC-V a credible contender for at least compute-bound HPC workloads.

What carries the argument

The load-bearing object is the SG2044's memory subsystem redesign plus the RVV v1.0 vector unit in each C920v2 core. The CPU keeps 64 T-Head cores in clusters of four, but replaces the SG2042's 4 memory controllers/channels with 32, moves to DDR5-4266, doubles per-cluster L2 to 2MB, and puts all cores in one NUMA region. This is what lets memory-bandwidth-bound kernels keep scaling past 8 threads; the RVV v1.0 support is what lets a stock compiler (GCC 15.2) generate vector code, which is what makes the single-core compute-bound EP result competitive. The STREAM copy kernel is the direct probe of the memory claim, and the NPB kernels are the workloads that demonstrate the end-to-end effect.

What would settle it

Re-run the 64-core NPB class C IS and MG comparisons and the STREAM copy benchmark on the SG2042 with the same GCC 15.2 used on the SG2044 (or vice versa); if the SG2044's 4.91x IS advantage and threefold bandwidth advantage shrink substantially, the attribution to the SG2044's memory subsystem is wrong.

Watch

Extended reading notes

Core claim

On the paper's own terms, the discovery is that the SG2044 turns RISC-V from a CPU that peaks early into one that keeps scaling: the STREAM copy benchmark shows bandwidth on the SG2042 plateauing after 8 cores while the SG2044 continues rising to over three times the SG2042's 64-core bandwidth. With 32 memory controllers and channels, DDR5-4266, and a single NUMA domain, all 64 T-Head C920v2 cores can be fed, so memory-bound NPB kernels (IS, MG, CG, FT) that stalled on the SG2042 now run 2.2 to 4.91 times faster at full occupancy. The other half is RVV v1.0, which lets unmodified mainline GCC v15.2 auto-vectorize code; on the compute-bound EP kernel the SG2044 matches a Skylake core-for-core

Load-bearing premise

The comparison assumes each platform's chosen compiler is representative: the SG2044 runs GCC 15.2, the SG2042 runs T-Head GCC 8.4, and the x86 and Arm systems run GCC 11.2, 8.4, or 9.2, so if a different compiler changed any machine's score by 20 to 30 percent the reported speedup ratios would shift.

Editorial extensions

If this is right

The SG2044 is the first commodity 64-core RISC-V CPU shown to scale on memory-bound NPB kernels (IS, MG, CG, FT) across all 64 cores, not just compute-bound ones.
Mainline GCC v15.2 can auto-vectorize HPC code targeting RISC-V, so the software stack no longer depends on vendor forks of GCC.
At full CPU occupancy the SG2044 is competitive with an Intel Skylake and an AMD EPYC on compute-bound EP, and comparable to Skylake and ThunderX2 on MG when comparing full CPUs.
At low core counts the gap with x86 and Arm remains significant, so HPC users on the SG2044 should run whole-node to get the benefit.
SOPHGO's claimed roughly threefold memory bandwidth improvement is confirmed by STREAM at 64 cores, aligning with the 4.91x IS improvement.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

Because the SG2044 uses the same C920 core family as the SG2042, most of the multi-core win is attributed to the memory subsystem; a future RISC-V server chip pairing a stronger core with similar memory could close the remaining per-core gap with x86 and Arm.
The CG vectorization slowdown (vectorised binary about three times slower) looks like a compiler autovectorization pathology rather than a hardware limit; it offers a concrete target for tuning GCC and LLVM's RISC-V vector code generation and could become a regression test.
The comparison assumes each platform's chosen compiler is representative; re-running the SG2042 with GCC 15.2, or the x86 and Arm systems with their best compilers, would test whether the reported ratios are hardware or toolchain effects.
The single-NUMA, 32-channel design suggests the SG2044 may behave more predictably than multi-socket x86 nodes for OpenMP because there is no remote NUMA penalty, though the paper does not make this claim.

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Signed reviews

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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Desk Editor's Note

read the letter

Nick Brown has done the first published HPC-style benchmark study of SOPHGO's SG2044. That alone is the main novelty: a 64-core RISC-V server chip with RVV 1.0, previously uncharacterized in the HPC literature. The central qualitative result, that the SG2044's advantage over the SG2042 appears only at high core counts, is well supported by the NPB scaling plots and independently by the STREAM bandwidth curves. The compute-bound EP numbers are genuinely interesting, with the SG2044 tracking the Skylake core-for-core.

The soft spots are real and the stress-test has the right target. The 4.91x IS speedup is GCC 15.2 on the SG2044 against T-Head GCC 8.4 on the SG2042. The paper asserts that 8.4 was consistently best but presents no data from that compiler sweep. Given the paper's own Table 8 shows IS improving by 35% between GCC 12.3.1 and 15.2 on the SG2044, the across-generation comparison can easily shift the headline by tens of percent. The cross-ISA comparisons in Section 5 mix GCC 11.2, 8.4, 9.2, and 15.2, so the relative positions are approximate. There are also no error bars and no raw data. These are measurement-attribution weaknesses, not signs of fabrication: the STREAM scaling and the multi-core curves point consistently in the same direction.

The paper is honest about its own limitations, including the CG vectorisation anomaly, and the citation pattern is fair. It leans on the author's earlier SG2042 work, which is exactly the relevant baseline. The remaining gaps are that this is one chip, one benchmark suite, and one benchmark generation, and the compiler question is not resolved.

Who should read it: anyone considering SG2044 hardware for compute workloads and anyone tracking RISC-V readiness. It deserves a serious referee. My recommendation: send it out, and ask for either the SG2042 compiler-sweep data, a common-toolchain rerun of the headline comparisons, or a carefully hedged abstract that presents the ratios as compiler-dependent. With that fix it becomes a solid reference point.

Referee Report

3 major / 6 minor

Summary. The paper presents the first HPC-oriented performance evaluation of the Sophon SG2044, a 64-core RISC-V processor. Using the NAS Parallel Benchmark suite (OpenMP version, class B/C), it compares the SG2044 against the SG2042, several smaller RISC-V systems, and x86/Arm HPC CPUs (AMD EPYC 7742, Intel Skylake 8170, Marvell ThunderX2). It reports that the SG2044 outperforms the SG2042 by up to 4.91x on 64 cores (IS kernel, Table 4), attributes this to an improved memory subsystem and RVV v1.0 support, and uses STREAM to show that memory bandwidth scales beyond 8 cores on the SG2044 while it plateaus on the SG2042. A final section studies compiler version and vectorisation effects, including a documented anomaly where vectorisation hurts the CG kernel.

Significance. If the results are robust, this is a valuable and timely data point: the SG2044 appears to be the first commodity 64-core RISC-V CPU on which mainline compiler auto-vectorization works and on which memory-bound NPB kernels continue to scale across all cores. The paper's strengths are its direct measurements, use of unmodified benchmark code, the independent STREAM scaling evidence, and the honest reporting of the CG vectorisation anomaly. The evaluation is more thorough than a simple 'look, it boots' paper and will be useful to the HPC and RISC-V communities as an early characterisation of this processor. The central claims are, however, weakened by uncontrolled cross-compiler comparisons and a lack of clock normalization, as detailed below.

major comments (3)

The headline multi-core speedup of the SG2044 over the SG2042 (up to 4.91x for IS, Table 4) is measured with different compilers on the two CPUs: T-Head's fork of GCC v8.4 for the SG2042, GCC v15.2 for the SG2044. The text states that v8.4 was 'consistently the best' among versions tried on the SG2042, but no data for that sweep are shown. This is load-bearing because Section 6 shows that on the SG2044, moving from GCC v12.3.1 to v15.2 alone improves IS by about 35% at 64 cores (2255.72 to 3038.14 Mop/s, Table 8). If a modern compiler similarly improves the SG2042, the reported ratios, and particularly the memory-subsystem attribution, would shrink. Please provide the compiler sweep data for the SG2042 or re-run the SG2042 comparison with a common toolchain; without this, the 4.91x figure is not substantiated.
Clock frequency is not normalized when comparing the SG2044 (2.6 GHz in the test system) with the SG2042 (2.0 GHz). The single-core improvement for the compute-bound EP kernel is 1.30x, which is exactly the frequency ratio (2.6/2.0). The paper attributes EP's benefit to RVV v1.0 and memory performance ('this is potentially due to the C920v2 providing RVV v1.0 along with the memory performance to keep the vector unit fed'), but the data are equally or more consistent with a pure clock-speed effect. Please report per-GHz or otherwise normalized figures for single-core comparisons, or explicitly discuss this confound. The multi-core comparison is less severely affected, but the 'compute-bound' attribution in the conclusions is not supported without normalization.
No error bars or variance information are reported. Section 5 states that 'all results represent the average of five independent runs', but no standard deviations, ranges, or per-run values are given anywhere, and Section 4 does not even state the number of runs. For a benchmark paper whose conclusions depend on differences such as 1.08x (IS single-core) and 2.20x (CG multi-core), the absence of variability information makes it impossible to judge whether these ratios are within run-to-run noise. Please add error bars or at least report the spread for the key SG2044-vs-SG2042 comparisons in Tables 3 and 4.

minor comments (6)

The phrase 'delivering up to 4.91 greater performance' should read '4.91 times greater' or '4.91x'.
Typo: 'Since it's release in 2023' should be 'Since its release in 2023'.
Typo: 'agsinst' should be 'against'.
The entry 'DNR' for the AllWinner D1 FT benchmark is undefined. If it means 'did not run', please state so in the caption or text.
The thread-placement experiment with OMP_PROC_BIND/OMP_PLACES is described only qualitatively ('consistently the best performance was obtained by either leaving these environment variables unset...'). This would be more convincing with a small table or a sentence quantifying the impact.
Reference [10] is titled 'SG2042 Empowering RISC-V in High-Performance Computing' but is cited to support claims about SG2044 promises; please clarify the source or use a more directly relevant reference if available.

Circularity Check

0 steps flagged · score 0.0 of 10

No circularity: benchmark claims rest on independent measurements; prior self-citations are background only.

full rationale

This is an empirical benchmark study rather than a mathematical derivation, so there is no derivation chain whose outputs are equivalent to its inputs by construction. The central claims—that the SG2044 is up to 4.91x faster than the SG2042 at 64 cores and that improved memory plus RVV v1.0 close the HPC gap—are supported by direct measurements reported in Tables 3, 4, and 8 and Figures 1-6. The memory-bandwidth attribution is independently confirmed in the same paper via the STREAM benchmark (Figure 1), not merely taken from a vendor promise or the author's earlier work. Prior self-citations ([2], [3], [4]) are used as background motivation and to characterize the SG2042's known bottlenecks, but the SG2044-vs-SG2042 speedups are newly measured here and do not reduce to those citations. The use of different compiler generations on different platforms (GCC v8.4 on SG2042, GCC v15.2 on SG2044, etc.) is a potential measurement-attribution threat, but it is a correctness/experimental-design concern, not circularity: the SG2044's performance is not defined in terms of the SG2042's compiler choice, and no fitted parameter is renamed as a prediction. No equation in the paper is self-referential, and no load-bearing claim is justified only by a self-citation whose content is itself the target result. The finding is therefore no significant circularity.

Assumptions & free parameters 0 free parameters · 4 assumptions · 0 invented entities

This is an empirical benchmark paper, so there are no fitted mathematical parameters or derived constants. The results rest on representativeness of NPB, comparability of toolchains, correctness of vendor data, and stability of measurements.

assumptions (4)

domain assumption NPB OpenMP class C runs are representative of HPC workloads and are run unmodified under comparable configurations.
Section 2.2 defines NPB as representative; Section 5 uses class C on all systems to compare.
domain assumption Different compiler versions and optimization flags do not dominate the measured hardware differences.
Section 4 uses GCC 8.4 fork for SG2042 and GCC 15.2 for SG2044; Section 5 uses different GCC versions per system, so the paper implicitly assumes hardware rather than toolchain drives results.
domain assumption The SG2044 sample and vendor-provided information (2.6 GHz clock, 32 memory controllers/channels, single NUMA region) are accurate and representative.
Section 2.1 relies on SOPHGO engineers' statement and third-party documentation; no independent verification is provided.
domain assumption Performance differences are stable across runs; the average of five runs without reported variance is treated as sufficient.
Section 5 states results are averages of five runs but no error bars or run-to-run spread are reported.

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Cite this review

Pith. "Pith review of Is RISC-V ready for High Performance Computing? An evaluation of the Sophon SG2044." pith.science (2026). https://pith.science/paper/5H5YNJIV

@misc{pith2026250813840,
  author       = {Pith},
  title        = {Pith review of: Is RISC-V ready for High Performance Computing? An evaluation of the Sophon SG2044},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/5H5YNJIV}},
  note         = {Machine review of arXiv:2508.13840}
}

read the original abstract

The pace of RISC-V adoption continues to grow rapidly, yet for the successes enjoyed in areas such as embedded computing, RISC-V is yet to gain ubiquity in High Performance Computing (HPC). The Sophon SG2044 is SOPHGO's next generation 64-core high performance CPU that has been designed for workstation and server grade workloads. Building upon the SG2042, subsystems that were a bottleneck in the previous generation have been upgraded. In this paper we undertake the first performance study of the SG2044 for HPC. Comparing against the SG2042 and other architectures, we find that the SG2044 is most advantageous when running at higher core counts, delivering up to 4.91 greater performance than the SG2042 over 64-cores. Two of the most important upgrades in the SG2044 are support for RVV v1.0 and an enhanced memory subsystem. This results in the SG2044 significantly closing the performance gap with other architectures, especially for compute-bound workloads.

Figures

Figures reproduced from arXiv: 2508.13840 by the authors.

**Figure 2.** IS benchmark performance (higher is better) paral [PITH_FULL_IMAGE:figures/full_fig_p005_2.png] view at source ↗

**Figure 3.** MG benchmark performance (higher is better) par [PITH_FULL_IMAGE:figures/full_fig_p006_3.png] view at source ↗

Figures from the paper (2 more)

**Figure 5.** Figure 5: CG benchmark performance (higher is better) par [PITH_FULL_IMAGE:figures/full_fig_p006_5.png]

**Figure 6.** Figure 6: FT benchmark performance (higher is better) par [PITH_FULL_IMAGE:figures/full_fig_p007_6.png]

Discussion (0). Continue with ORCID to comment.

Reference graph

Works this paper leans on

15 extracted references · 15 canonical work pages

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bananapi 2024. Banana Pi BPI-F3 SpacemiT K1 RISC-V chip datasheet . Retrieved Aug 9, 2025 from https://docs.banana-pi.org/en/BPI-F3/SpacemiT_K1_datasheet

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Nick Brown and Maurice Jamieson. 2024. Performance characterisation of the 64-core SG2042 RISC-V CPU for HPC. In International Conference on High Perfor- mance Computing. Springer, 354–367

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Patrick Diehl, Panagiotis Syskakis, Gregor Daiß, Steven R Brandt, Alireza Kheirkhahan, Srinivas Yadav Singanaboina, Dominic Marcello, Chris Taylor, John Leidel, and Hartmut Kaiser. 2024. Preparing for HPC on RISC-V: Examining Vectorization and Distributed Performance of an Astrophysics Application with HPX and Kokkos. In SC24-W: Workshops of the Internati...

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