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AutoVCoder: A Systematic Framework for Automated Verilog Code Generation using LLMs

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arxiv 2407.18333 v1 pith:5HPBAFXD submitted 2024-07-21 cs.AR cs.AI

Mingzhe Gao , Jieru Zhao , Zhe Lin , Wenchao Ding , Xiaofeng Hou , Yu Feng , Chao Li , Minyi Guo This is my paper · ORCID
classification cs.ARcs.AI
keywords generationcodecorrectnessllmsautovcoderverilogframeworkfunctional
verification ladder T0 review T1 audit T2 compute T3 formal

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Recently, the use of large language models (LLMs) for software code generation, e.g., C/C++ and Python, has proven a great success. However, LLMs still suffer from low syntactic and functional correctness when it comes to the generation of register-transfer level (RTL) code, such as Verilog. To address this issue, in this paper, we develop AutoVCoder, a systematic open-source framework that significantly improves the LLMs' correctness of generating Verilog code and enhances the quality of its output at the same time. Our framework integrates three novel techniques, including a high-quality hardware dataset generation approach, a two-round LLM fine-tuning method and a domain-specific retrieval-augmented generation (RAG) mechanism. Experimental results demonstrate that AutoVCoder outperforms both industrial and academic LLMs in Verilog code generation. Specifically, AutoVCoder shows a 0.5% and 2.2% improvement in functional correctness on the EvalMachine and EvalHuman benchmarks compared with BetterV, and also achieves a 3.4% increase in syntax correctness and a 3.4% increase in functional correctness on the RTLLM benchmark compared with RTLCoder.

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Cited by 5 Pith papers

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score. Full citation record

  1. HINT: Toward an Executable Hardware-Intent Representation Layer for LLM-Driven RTL Generation

    cs.AR 2026-08 conditional novelty 6.0 of 10

    HINT, an executable hardware-intent representation with explicit architecture commitments and RTL-lowering obligations, improves LLM-generated RTL correctness and area across seven operator cases and three larger designs.

  2. RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs

    cs.LG 2025-07 conditional novelty 6.0 of 10

    RealBench measures LLM Verilog generation on complex open-source IP cores with formal verification, and all tested models score near zero on full system designs.

  3. RTL++: Graph-enhanced LLM for RTL Code Generation

    cs.PL 2025-05 conditional novelty 6.0 of 10

    RTL++ encodes RTL code as textualized CFG/DFG graphs to generate richer instructions for fine-tuning CodeLlama-7B, claiming improved VerilogEval pass@k over comparable open-source models.

  4. MAGE: A Multi-Agent Engine for Automated RTL Code Generation

    cs.AR 2024-12 reject novelty 6.0 of 10

    MAGE, a multi-agent LLM pipeline with high-temperature sampling and state-checkpoint debugging, reports 95.7% Pass@1 on VerilogEval-V2, but the evaluation includes the golden testbench as generation input.

  5. VerilogDB: The Largest, Highest-Quality Dataset with a Preprocessing Framework for LLM-based RTL Generation

    cs.AR 2025-07 conditional novelty 4.0 of 10

    A new pipeline and dataset of 20,392 synthesis-checked Verilog modules for LLM fine-tuning is presented, claimed to be the largest high-quality dataset of its kind.

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