Paper Citation Record · LEDGER

SCE-NTT: A Hardware Accelerator for Number Theoretic Transform Using Superconductor Electronics

As of 20 August 2026, this Paper Citation Record lists 33 of 33 outbound references and 2 inbound Pith citation observations for arXiv:2508.21265.

A citation records a reference. It does not transfer a finding from one paper to another.

pith.paper-citation-record.v1
2508.21265 v1

Coverage vector

measured 33 of 33 reference resolution

Typed states for the displayed outbound observations.

Source: paper_references, paper_reference_links, observed 2026-08-05T14:30:30.389901Z

measured 35 of 35 standing notices

One-hop event checks from named stored sources.

Source: scholarly_work_events, retraction_status_cache, observed 2026-08-19T06:32:44.657259+00:00

measured 2 of 2 inbound itemization

Pith citing papers itemized under the disclosed page cap.

Source: paper_references, paper_reference_links, observed 2026-07-30T13:30:50.758024Z

measured 0 of 1 external citation measurements

A source-named dated measurement, never combined with another source.

Source: arxiv_reference, observed 2026-05-11T07:50:59.930382Z

Reference resolution

33 of 33 outbound references displayed

verified exact2
verified fuzzy29
unresolved2
parse uncertain0
malformed identifier0
metadata mismatch0

External citation measurements

No source-named external measurement is stored.

Outbound references

Observation e388c5d4-ab1e-4f94-8a88-1967732d70e6 · outbound

This paper cites IRDS™ 2023: IRDS Chairman Editorial - IEEE IRDS™.

SCE-NTT: A Hardware Accelerator for Number Theoretic Transform Using Superconductor Electronics IRDS™ 2023: IRDS Chairman Editorial - IEEE IRDS™

Reference 1

Resolution: verified fuzzy; raw_fallback, observed 2026-08-05T14:30:35.622132Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-19T06:32:44.657259+00:00.

Observation cb4bc8b7-93cf-413d-9f7b-2abecc1a4c82 · outbound

This paper cites Energy-efficient single flux quantum technology,.

SCE-NTT: A Hardware Accelerator for Number Theoretic Transform Using Superconductor Electronics Energy-efficient single flux quantum technology,

Reference 2

Resolution: verified fuzzy; raw_fallback, observed 2026-08-05T14:30:35.489329Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-19T06:32:44.657259+00:00.

Observation c2ebe1c1-ce3c-43c2-a311-8d421526c707 · outbound

This paper cites An adiabatic quantum flux parametron as an ultra-low-power logic device,.

SCE-NTT: A Hardware Accelerator for Number Theoretic Transform Using Superconductor Electronics An adiabatic quantum flux parametron as an ultra-low-power logic device,

Reference 3

Resolution: verified fuzzy; raw_fallback, observed 2026-08-05T14:30:35.191250Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-19T06:32:44.657259+00:00.

Observation 29e977ea-d4a7-401c-83ff-fc0364689785 · outbound

This paper cites Coldflux superconducting eda and tcad tools project: Overview and progress,.

SCE-NTT: A Hardware Accelerator for Number Theoretic Transform Using Superconductor Electronics Coldflux superconducting eda and tcad tools project: Overview and progress,

Reference 4

Resolution: verified fuzzy; raw_fallback, observed 2026-08-05T14:30:34.881158Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-19T06:32:44.657259+00:00.

Observation 4e9ed7e4-9746-4fbd-9c5e-18bc049a3c29 · outbound

This paper cites Results from the coldflux superconductor integrated circuit design tool project,.

SCE-NTT: A Hardware Accelerator for Number Theoretic Transform Using Superconductor Electronics Results from the coldflux superconductor integrated circuit design tool project,

Reference 5

Resolution: verified fuzzy; raw_fallback, observed 2026-08-05T14:30:34.716504Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-19T06:32:44.657259+00:00.

Observation eb791b3d-8069-4077-92e2-c650f8a663c2 · outbound

This paper cites Design and Implementation of a Pipelined Bit-Serial SFQ Microprocessor, CORE1β,.

SCE-NTT: A Hardware Accelerator for Number Theoretic Transform Using Superconductor Electronics Design and Implementation of a Pipelined Bit-Serial SFQ Microprocessor, CORE1β,

Reference 6

Resolution: verified fuzzy; raw_fallback, observed 2026-08-05T14:30:34.578681Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-19T06:32:44.657259+00:00.

Observation 0d23e115-ffdd-4601-a8ef-79a7c910f838 · outbound

This paper cites Mana: A monolithic adiabatic integration architecture microprocessor using 1.4-zj/op unshunted superconductor josephson junction devices,.

SCE-NTT: A Hardware Accelerator for Number Theoretic Transform Using Superconductor Electronics Mana: A monolithic adiabatic integration architecture microprocessor using 1.4-zj/op unshunted superconductor josephson junction devices,

Reference 7

Resolution: verified fuzzy; raw_fallback, observed 2026-08-05T14:30:34.432513Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-19T06:32:44.657259+00:00.

Observation 1808d4dd-2919-4665-9efa-03fa9c61ec31 · outbound

This paper cites Fully homomorphic encryption using ideal lattices,.

SCE-NTT: A Hardware Accelerator for Number Theoretic Transform Using Superconductor Electronics Fully homomorphic encryption using ideal lattices,

Reference 8

Resolution: unresolved; no resolver link, observed 2026-08-05T14:30:27.482154Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation f29cdebb-d303-4646-95d0-4ef3557e4249 · outbound

This paper cites Polynomial-time algorithms for prime factorization and discrete logarithms on a quantum computer,.

SCE-NTT: A Hardware Accelerator for Number Theoretic Transform Using Superconductor Electronics Polynomial-time algorithms for prime factorization and discrete logarithms on a quantum computer,

Reference 9

Resolution: unresolved; no resolver link, observed 2026-08-05T14:30:27.589652Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 2034b738-1b2f-48fb-9628-8f544ad454c2 · outbound

This paper cites Fully homomorphic encryption over the integers,.

SCE-NTT: A Hardware Accelerator for Number Theoretic Transform Using Superconductor Electronics Fully homomorphic encryption over the integers,

Reference 10

Resolution: verified fuzzy; raw_fallback, observed 2026-08-05T14:30:34.278752Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-19T06:32:44.657259+00:00.

Observation c327af31-1076-46c9-8af5-ba6e76b01267 · outbound

This paper cites Faster fully homomorphic encryption: Bootstrapping in less than 0.1 seconds,.

SCE-NTT: A Hardware Accelerator for Number Theoretic Transform Using Superconductor Electronics Faster fully homomorphic encryption: Bootstrapping in less than 0.1 seconds,

Reference 16

Resolution: verified fuzzy; raw_fallback, observed 2026-08-05T14:30:33.425762Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-19T06:32:44.657259+00:00.

Observation dc116b1e-c519-417e-a49d-21be38a80ead · outbound

This paper cites Fhew: bootstrapping homomorphic en- cryption in less than a second,.

SCE-NTT: A Hardware Accelerator for Number Theoretic Transform Using Superconductor Electronics Fhew: bootstrapping homomorphic en- cryption in less than a second,

Reference 17

Resolution: verified fuzzy; raw_fallback, observed 2026-08-05T14:30:33.833985Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-19T06:32:44.657259+00:00.

Observation 7e6ae607-55fd-41cd-86f9-9c76c6ebb219 · outbound

This paper cites (leveled) fully homo- morphic encryption without bootstrapping,.

SCE-NTT: A Hardware Accelerator for Number Theoretic Transform Using Superconductor Electronics (leveled) fully homo- morphic encryption without bootstrapping,

Reference 18

Resolution: verified fuzzy; raw_fallback, observed 2026-08-05T14:30:34.083670Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-19T06:32:44.657259+00:00.

Observation ae5e9e08-34a8-405b-8fb2-8fffe3c66a37 · outbound

This paper cites Somewhat practical fully homomorphic encryption,.

SCE-NTT: A Hardware Accelerator for Number Theoretic Transform Using Superconductor Electronics Somewhat practical fully homomorphic encryption,

Reference 19

Resolution: verified fuzzy; raw_fallback, observed 2026-08-05T14:30:33.951928Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-19T06:32:44.657259+00:00.

Observation f36dd942-b45c-4df9-b988-86084a5d872c · outbound

This paper cites Homomorphic encryption for arithmetic of approximate numbers,.

SCE-NTT: A Hardware Accelerator for Number Theoretic Transform Using Superconductor Electronics Homomorphic encryption for arithmetic of approximate numbers,

Reference 20

Resolution: verified fuzzy; raw_fallback, observed 2026-08-05T14:30:33.682959Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-19T06:32:44.657259+00:00.

Observation c8ea2fb4-3e20-41c7-90bc-b1786157f189 · outbound

This paper cites A high-performance, conflict- free memory-access architecture for modular polynomial multiplication,.

SCE-NTT: A Hardware Accelerator for Number Theoretic Transform Using Superconductor Electronics A high-performance, conflict- free memory-access architecture for modular polynomial multiplication,

Reference 21

Resolution: verified fuzzy; raw_fallback, observed 2026-08-05T14:30:33.293007Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-19T06:32:44.657259+00:00.

Observation 4396345e-0166-42f6-8aed-86ad735b76fb · outbound

This paper cites Reconfigurable multi- core array architecture and mapping method for rns-based homomophic encryption,.

SCE-NTT: A Hardware Accelerator for Number Theoretic Transform Using Superconductor Electronics Reconfigurable multi- core array architecture and mapping method for rns-based homomophic encryption,

Reference 22

Resolution: verified fuzzy; raw_fallback, observed 2026-08-05T14:30:33.159541Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-19T06:32:44.657259+00:00.

Observation 0680a4ac-ca5b-4f61-bc9a-eb0a54f5cfd6 · outbound

This paper cites Medha: Microcoded Hardware Accelerator for computing on Encrypted Data.

SCE-NTT: A Hardware Accelerator for Number Theoretic Transform Using Superconductor Electronics Medha: Microcoded Hardware Accelerator for computing on Encrypted Data

Reference 23

Resolution: verified exact; local_arxiv, observed 2026-08-05T14:30:30.774025Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-19T06:32:44.657259+00:00.

Observation 44d9369f-a34a-4af2-9fca-9ad88b7bf0a3 · outbound

This paper cites coxhe: A software- hardware co-design framework for fpga acceleration of homomorphic computation,.

SCE-NTT: A Hardware Accelerator for Number Theoretic Transform Using Superconductor Electronics coxhe: A software- hardware co-design framework for fpga acceleration of homomorphic computation,

Reference 24

Resolution: verified fuzzy; raw_fallback, observed 2026-08-05T14:30:32.965839Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-19T06:32:44.657259+00:00.

Observation 5c81570a-cba8-4fe7-8a08-12f4bbefec2b · outbound

This paper cites On ideal lattices and learn- ing with errors over rings,.

SCE-NTT: A Hardware Accelerator for Number Theoretic Transform Using Superconductor Electronics On ideal lattices and learn- ing with errors over rings,

Reference 25

Resolution: verified fuzzy; raw_fallback, observed 2026-08-05T14:30:32.799960Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-19T06:32:44.657259+00:00.

Observation f3f39937-2957-49b2-bb64-4c6894e27006 · outbound

This paper cites Fully homomorphic encryption from ring-lwe and security for key dependent messages,.

SCE-NTT: A Hardware Accelerator for Number Theoretic Transform Using Superconductor Electronics Fully homomorphic encryption from ring-lwe and security for key dependent messages,

Reference 26

Resolution: verified fuzzy; raw_fallback, observed 2026-08-05T14:30:32.428172Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-19T06:32:44.657259+00:00.

Observation bce2a7fb-9e02-42c9-aea5-0f2928ac4066 · outbound

This paper cites Fpga-based accelerators of fully pipelined modular multipliers for homomorphic encryption,.

SCE-NTT: A Hardware Accelerator for Number Theoretic Transform Using Superconductor Electronics Fpga-based accelerators of fully pipelined modular multipliers for homomorphic encryption,

Reference 27

Resolution: verified fuzzy; raw_fallback, observed 2026-08-05T14:30:32.250842Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-19T06:32:44.657259+00:00.

Observation eb302d9a-d045-4ddd-b7b4-d96c314fe583 · outbound

This paper cites A high-performance low-power barrett modular multiplier for cryptosystems,.

SCE-NTT: A Hardware Accelerator for Number Theoretic Transform Using Superconductor Electronics A high-performance low-power barrett modular multiplier for cryptosystems,

Reference 28

Resolution: verified fuzzy; raw_fallback, observed 2026-08-05T14:30:32.074555Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-19T06:32:44.657259+00:00.

Observation 66114b52-b51a-46ee-9e27-e7f91007d35a · outbound

This paper cites An iterative montgomery modular multiplication algorithm with low area-time product,.

SCE-NTT: A Hardware Accelerator for Number Theoretic Transform Using Superconductor Electronics An iterative montgomery modular multiplication algorithm with low area-time product,

Reference 29

Resolution: verified fuzzy; raw_fallback, observed 2026-08-05T14:30:31.911933Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-19T06:32:44.657259+00:00.

Observation 5307555f-33e6-4b9c-b333-741e08222200 · outbound

This paper cites Challenges and unexplored frontiers in electronic design automation for superconducting digital logic,.

SCE-NTT: A Hardware Accelerator for Number Theoretic Transform Using Superconductor Electronics Challenges and unexplored frontiers in electronic design automation for superconducting digital logic,

Reference 30

Resolution: verified fuzzy; raw_fallback, observed 2026-08-05T14:30:31.769033Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-19T06:32:44.657259+00:00.

Observation b3c62834-9bd7-4c8e-a749-e0685fe9fafc · outbound

This paper cites Fabrication Process and Properties of Fully- Planarized Deep-Submicron Nb/Al–AlO x/Nb Josephson Junctions for VLSI Circuits,.

SCE-NTT: A Hardware Accelerator for Number Theoretic Transform Using Superconductor Electronics Fabrication Process and Properties of Fully- Planarized Deep-Submicron Nb/Al–AlO x/Nb Josephson Junctions for VLSI Circuits,

Reference 31

Resolution: verified fuzzy; raw_fallback, observed 2026-08-05T14:30:31.637395Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-19T06:32:44.657259+00:00.

Observation 4541c209-36bd-448c-894f-017f715d926d · outbound

This paper cites Multi-phase clocking for multi- threaded gate-level-pipelined superconductive logic,.

SCE-NTT: A Hardware Accelerator for Number Theoretic Transform Using Superconductor Electronics Multi-phase clocking for multi- threaded gate-level-pipelined superconductive logic,

Reference 32

Resolution: verified fuzzy; raw_fallback, observed 2026-08-05T14:30:31.455409Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-19T06:32:44.657259+00:00.

Observation 55e1d802-8d74-44f1-9ac4-2fc7050ef53e · outbound

This paper cites An efficient and scalable clocking assignment algorithm for multi-threaded multi-phase single flux quantum circuits,.

SCE-NTT: A Hardware Accelerator for Number Theoretic Transform Using Superconductor Electronics An efficient and scalable clocking assignment algorithm for multi-threaded multi-phase single flux quantum circuits,

Reference 33

Resolution: verified fuzzy; raw_fallback, observed 2026-08-05T14:30:31.311412Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-19T06:32:44.657259+00:00.

Observation 83ac8939-d566-495a-b854-d0ae952a3469 · outbound

This paper cites Multi-cell characterization: Developing robust cells and abstraction for rapid single flux quantum (rsfq) logic,.

SCE-NTT: A Hardware Accelerator for Number Theoretic Transform Using Superconductor Electronics Multi-cell characterization: Developing robust cells and abstraction for rapid single flux quantum (rsfq) logic,

Reference 34

Resolution: verified fuzzy; raw_fallback, observed 2026-08-05T14:30:31.069917Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-19T06:32:44.657259+00:00.

Observation c316bed2-eec3-41b5-ab73-18bf07b3d7fe · outbound

This paper cites A full rns variant of approximate homomorphic encryption,.

SCE-NTT: A Hardware Accelerator for Number Theoretic Transform Using Superconductor Electronics A full rns variant of approximate homomorphic encryption,

Reference 35

Resolution: verified fuzzy; raw_fallback, observed 2026-08-05T14:30:33.539819Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-19T06:32:44.657259+00:00.

Observation e407782c-0e82-4612-9605-e5999cd94142 · outbound

This paper cites Heax: An architecture for computing on encrypted data,.

SCE-NTT: A Hardware Accelerator for Number Theoretic Transform Using Superconductor Electronics Heax: An architecture for computing on encrypted data,

Reference 36

Resolution: verified fuzzy; raw_fallback, observed 2026-08-05T14:30:30.923144Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-19T06:32:44.657259+00:00.

Observation fa80776b-6795-4343-a12d-f1f2957588db · outbound

This paper cites TREBUCHET: Fully Homomorphic Encryption Accelerator for Deep Computation.

SCE-NTT: A Hardware Accelerator for Number Theoretic Transform Using Superconductor Electronics TREBUCHET: Fully Homomorphic Encryption Accelerator for Deep Computation

Reference 37

Resolution: verified exact; local_arxiv, observed 2026-08-05T14:30:30.555741Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-19T06:32:44.657259+00:00.

Observation 64d7f36a-6aab-43d7-95df-f511abbc3a48 · outbound

This paper cites Springer, 2010, pp.

SCE-NTT: A Hardware Accelerator for Number Theoretic Transform Using Superconductor Electronics Springer, 2010, pp

Reference 2010

Resolution: verified fuzzy; raw_fallback, observed 2026-08-05T14:30:32.605982Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-19T06:32:44.657259+00:00.

Pith citing papers

Observation 4b5b996f-bfc9-49e7-898f-4a0fe0ad13d8 · inbound

qPRO-AQFP: Post-Routing Optimization of AQFP Circuits with Delay Line Clocking cites this paper.

qPRO-AQFP: Post-Routing Optimization of AQFP Circuits with Delay Line Clocking SCE-NTT: A Hardware Accelerator for Number Theoretic Transform Using Superconductor Electronics

Reference 6

Resolution: verified exact; arxiv_id, observed 2026-05-11T07:50:59.934840Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-19T06:32:44.657259+00:00.

Observation ab531316-afe5-4704-be22-195a04517205 · inbound

Bridging AQFP Technology Legalization and Physical Design: Layout-Aware Buffer and Splitter Insertion via Width--Depth Product Minimization cites this paper.

Bridging AQFP Technology Legalization and Physical Design: Layout-Aware Buffer and Splitter Insertion via Width--Depth Product Minimization SCE-NTT: A Hardware Accelerator for Number Theoretic Transform Using Superconductor Electronics

Reference 8

Resolution: unresolved; no resolver link, observed 2026-07-30T13:30:50.758024Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.