Paper Citation Record · LEDGER

VerilogEval: Evaluating Large Language Models for Verilog Code Generation

As of 8 August 2026, this Paper Citation Record lists 0 of 0 outbound references and 15 inbound Pith citation observations for arXiv:2309.07544.

A citation records a reference. It does not transfer a finding from one paper to another.

pith.paper-citation-record.v1
2309.07544 v2

Coverage vector

measured 0 of 0 reference resolution

Typed states for the displayed outbound observations.

Source: paper_references, paper_reference_links

measured 15 of 15 standing notices

One-hop event checks from named stored sources.

Source: scholarly_work_events, retraction_status_cache, observed 2026-08-07T06:34:17.273281+00:00

measured 15 of 15 inbound itemization

Pith citing papers itemized under the disclosed page cap.

Source: paper_references, paper_reference_links, observed 2026-08-07T10:45:07.070822Z

measured 1 of 1 external citation measurements

A source-named dated measurement, never combined with another source.

Source: arxiv_reference, observed 2026-08-05T02:28:24.338817Z

Reference resolution

0 of 0 outbound references displayed

verified exact0
verified fuzzy0
unresolved0
parse uncertain0
malformed identifier0
metadata mismatch0

External citation measurements

16
arxiv_reference, observed 2026-08-05T02:28:24.338817Z

Outbound references

No outbound reference observations are available for this paper version.

Pith citing papers

Observation da3d5ac3-c594-4904-8f3c-4f9c62f5a3f5 · inbound

hdl2v: A Code Translation Dataset for Enhanced LLM Verilog Generation cites this paper.

hdl2v: A Code Translation Dataset for Enhanced LLM Verilog Generation VerilogEval: Evaluating Large Language Models for Verilog Code Generation

Reference 20

Resolution: unresolved; no resolver link, observed 2026-08-07T10:45:07.070822Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation b89db61c-a286-4337-9599-cdc713bc6500 · inbound

VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code cites this paper.

VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code VerilogEval: Evaluating Large Language Models for Verilog Code Generation

Reference 49

Resolution: unresolved; no resolver link, observed 2026-08-07T05:43:45.594753Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 7444a3c0-2d95-422e-8536-a27aff96fcef · inbound

Spec2RTL-Agent: Automated Hardware Code Generation from Complex Specifications Using LLM Agent Systems cites this paper.

Spec2RTL-Agent: Automated Hardware Code Generation from Complex Specifications Using LLM Agent Systems VerilogEval: Evaluating Large Language Models for Verilog Code Generation

Reference 5

Resolution: unresolved; no resolver link, observed 2026-08-07T00:31:00.458485Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 93c00a0d-56fa-4890-a8d4-0e80bcf81c61 · inbound

Iceberg: Enhancing HLS Modeling with Synthetic Data cites this paper.

Iceberg: Enhancing HLS Modeling with Synthetic Data VerilogEval: Evaluating Large Language Models for Verilog Code Generation

Reference 3

Resolution: unresolved; no resolver link, observed 2026-08-06T17:51:02.593071Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 5ec78f87-40c2-408d-9fb4-24fbcba1a705 · inbound

VerilogDB: The Largest, Highest-Quality Dataset with a Preprocessing Framework for LLM-based RTL Generation cites this paper.

VerilogDB: The Largest, Highest-Quality Dataset with a Preprocessing Framework for LLM-based RTL Generation VerilogEval: Evaluating Large Language Models for Verilog Code Generation

Reference 21

Resolution: unresolved; no resolver link, observed 2026-08-06T18:54:03.834957Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 316eca86-dff6-4a51-9b75-050c15e72025 · inbound

Report for NSF Workshop on AI for Electronic Design Automation cites this paper.

Report for NSF Workshop on AI for Electronic Design Automation VerilogEval: Evaluating Large Language Models for Verilog Code Generation

Reference 47

Resolution: verified exact; arxiv_id, observed 2026-05-16T12:37:53.112506Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation f3196897-ce6e-4e89-b5d6-bb63a217a2ab · inbound

Dr. RTL: Autonomous Agentic RTL Optimization through Tool-Grounded Self-Improvement cites this paper.

Dr. RTL: Autonomous Agentic RTL Optimization through Tool-Grounded Self-Improvement VerilogEval: Evaluating Large Language Models for Verilog Code Generation

Reference 20

Resolution: verified exact; arxiv_id, observed 2026-05-10T10:49:56.176778Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 60eddfe4-5d7c-4cf5-9c7c-8ce5193266c1 · inbound

ChipLingo: A Systematic Training Framework for Large Language Models in EDA cites this paper.

ChipLingo: A Systematic Training Framework for Large Language Models in EDA VerilogEval: Evaluating Large Language Models for Verilog Code Generation

Reference 9

Resolution: verified exact; arxiv_id, observed 2026-05-12T09:41:27.221550Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 11c2f4ac-8e93-4b49-bae2-cc32dfd90908 · inbound

Alpha-RTL: Test-Time Training for RTL Hardware Optimization cites this paper.

Alpha-RTL: Test-Time Training for RTL Hardware Optimization VerilogEval: Evaluating Large Language Models for Verilog Code Generation

Reference 2

Resolution: verified exact; arxiv_id, observed 2026-07-02T07:06:44.164135Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 77c7a08d-deb1-4751-bc70-01518cd97f62 · inbound

OpenRTLSet: A Fully Open-Source Dataset for Large Language Model-based Verilog Module Design cites this paper.

OpenRTLSet: A Fully Open-Source Dataset for Large Language Model-based Verilog Module Design VerilogEval: Evaluating Large Language Models for Verilog Code Generation

Reference 36

Resolution: verified exact; arxiv_id, observed 2026-07-03T04:37:37.415159Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation c327e771-2feb-45d6-ae0b-c9a8e14123b4 · inbound

PCB-QA: Evaluating LLMs over the First Printed Circuit Board Design Question-Answer Dataset cites this paper.

PCB-QA: Evaluating LLMs over the First Printed Circuit Board Design Question-Answer Dataset VerilogEval: Evaluating Large Language Models for Verilog Code Generation

Reference 25

Resolution: verified exact; arxiv_id, observed 2026-06-27T08:20:44.917633Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 7ce6bdda-eb4a-4bb3-b26c-2d12951e45af · inbound

Agentic Hardware Design as Repository-Level Code Evolution cites this paper.

Agentic Hardware Design as Repository-Level Code Evolution VerilogEval: Evaluating Large Language Models for Verilog Code Generation

Reference 7

Resolution: metadata mismatch; arxiv_id, observed 2026-07-01T18:45:58.289303Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 60969956-7511-4124-8465-1829f3a0415f · inbound

ArchEval: Measuring AI Agents as Computer Architects cites this paper.

ArchEval: Measuring AI Agents as Computer Architects VerilogEval: Evaluating Large Language Models for Verilog Code Generation

Reference 28

Resolution: unresolved; no resolver link, observed 2026-07-12T01:16:50.927415Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation fadea7a6-434b-4fc5-bd31-c33dcbceeec9 · inbound

WaveformQA: Benchmarking LLM Temporal Reasoning on Digital Waveforms cites this paper.

WaveformQA: Benchmarking LLM Temporal Reasoning on Digital Waveforms VerilogEval: Evaluating Large Language Models for Verilog Code Generation

Reference 22

Resolution: unresolved; no resolver link, observed 2026-08-01T09:49:36.505128Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 1a1f72c5-229d-4644-906a-c1ef3c6b6839 · inbound

Open-Source LLM-Driven Formal Verification: A Multi-Agent Pipeline for RTL Repair cites this paper.

Open-Source LLM-Driven Formal Verification: A Multi-Agent Pipeline for RTL Repair VerilogEval: Evaluating Large Language Models for Verilog Code Generation

Reference 7

Resolution: unresolved; no resolver link, observed 2026-08-03T01:29:16.231691Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.