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arxiv: 2606.30553 · v2 · pith:7P4GGESRnew · submitted 2026-06-29 · 💻 cs.AR · cs.DC

COSM: A Cooperative Scheduling Framework for Concurrent PIM and CPU Execution on Mobile Devices

Yilong Zhao , Fangxin Liu , Onur Mutlu , Mingyu Gao , Jian Liu , Haibing Guan , Li Jiang This is my paper

Pith reviewed 2026-06-30 03:05 UTC · model grok-4.3

classification 💻 cs.AR cs.DC
keywords processing-in-memorymobile devicesscheduling frameworkconcurrent executionLLM inferenceDRAM accessbank conflictsthroughput optimization
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The pith

COSM enables concurrent PIM and CPU execution on mobile devices by scheduling PIM tasks into CPU idle periods.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper presents COSM to allow processing-in-memory and CPU tasks to share DRAM on phones without major interference during LLM runs. Bank conflicts and bus congestion normally reduce the gains from PIM when both access memory at once. COSM introduces a control interface that issues many PIM commands without stopping CPU accesses and a scheduler that inserts those commands into gaps in the CPU sequence. This approach hides PIM latency and overlaps its work with data movement. Readers would care because on-device AI requires both privacy and speed yet faces tight memory constraints on existing hardware.

Core claim

The central claim is that a low-interference PIM control interface together with an idleness-aware scheduling method can integrate PIM commands into CPU access sequences on mobile platforms, enabling concurrent execution that improves PIM throughput by up to 2.8x while limiting CPU performance loss to under 2% during tests with LLMs and mobile workloads.

What carries the argument

The idleness-aware scheduling method that places PIM commands into available idle time windows within the CPU access sequence, supported by a low-interference PIM control interface that generates the maximum number of PIM commands without disrupting CPU memory accesses.

If this is right

  • PIM execution latency becomes hidden from the CPU view.
  • PIM work overlaps with ongoing data transfer operations.
  • The approach requires no hardware modifications to existing mobile DRAM.
  • The gains apply across LLMs paired with both mobile applications and compute kernels.
  • Throughput improves while CPU performance remains nearly unchanged.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The same idle-window insertion idea could extend to other memory-bound tasks on edge devices beyond language models.
  • Software scheduling alone might reduce the need for dedicated PIM hardware in memory-constrained systems.
  • Validation on varied DRAM bank organizations would test how well idleness detection holds across device models.

Load-bearing premise

That the low-interference interface and idleness-aware scheduling can reliably avoid or mitigate bank conflicts and bus congestion in real mobile hardware without creating new bottlenecks.

What would settle it

A measurement on physical mobile hardware showing that concurrent LLM and app execution still produces measurable bus congestion or CPU slowdown above 2% even when the COSM scheduler is active.

Figures

Figures reproduced from arXiv: 2606.30553 by Fangxin Liu, Haibing Guan, Jian Liu, Li Jiang, Mingyu Gao, Onur Mutlu, Yilong Zhao.

Figure 1
Figure 1. Figure 1: Internal/external DRAM bandwidth utilization of CPU and PIM work [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: (a) CPU workload performance under injected read latency. (b) PIM [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: (a) An example of FR-FCFS scheduling for a CPU-only workload and [PITH_FULL_IMAGE:figures/full_fig_p004_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: COSM’s memory controller architecture and memory interface [PITH_FULL_IMAGE:figures/full_fig_p005_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: Timing diagram of PIM unit, memory bus, Command Arbiter, and [PITH_FULL_IMAGE:figures/full_fig_p006_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: The data, command, and address path of (a) [PITH_FULL_IMAGE:figures/full_fig_p006_6.png] view at source ↗
Figure 7
Figure 7. Figure 7: (a) Conventional software-controlled three-stage sequential scheduling. [PITH_FULL_IMAGE:figures/full_fig_p008_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: Overall PIM & CPU performance of COSM and baselines for concurrent CPU and PIM execution. [PITH_FULL_IMAGE:figures/full_fig_p010_8.png] view at source ↗
Figure 9
Figure 9. Figure 9: Normalized CPU and PIM workload performance under fixed-length and preemptable PIM execution command. Cases where CPU performance degrades [PITH_FULL_IMAGE:figures/full_fig_p011_9.png] view at source ↗
Figure 10
Figure 10. Figure 10: Impact of CPU-mediated data transfers on CPU performance under different scheduling strategies. We test on the attention layers of the benchmarks. [PITH_FULL_IMAGE:figures/full_fig_p011_10.png] view at source ↗
Figure 11
Figure 11. Figure 11: (a) PIM performance and (b) Internal bandwidth usage during concur [PITH_FULL_IMAGE:figures/full_fig_p012_11.png] view at source ↗
Figure 12
Figure 12. Figure 12: PIM workload energy consumption per token (including PIM unit computation, PIM bank access, and CPU-mediated data transfer) of COSM and baselines [PITH_FULL_IMAGE:figures/full_fig_p012_12.png] view at source ↗
Figure 13
Figure 13. Figure 13: Sensitivity analysis on (a) nP T L (b) rank count per channel (c) KV cache size (d) scaled tRP (n×, relative to [PITH_FULL_IMAGE:figures/full_fig_p013_13.png] view at source ↗
read the original abstract

The development of on-device large language models (LLMs) is driven by the need for privacy and fast response times. Energy-intensive data transfer on mobile devices makes Processing-in-Memory (PIM) an effective solution. Due to stringent DRAM cost constraints, limited physical footprint on circuit boards, and the interaction between applications and LLMs, it is imperative for the CPU and PIM to operate concurrently within a shared memory space. However, challenges such as bank conflicts and bus congestion can arise, potentially diminishing the performance and energy benefits of PIM. To address this challenge, we introduce COSM, a cooperative scheduling framework designed to facilitate the concurrent operation of PIM and CPU tasks on mobile platforms. Our key innovations include: 1) a low-interference PIM control interface that generates the maximum number of PIM commands without disrupting CPU memory accesses; 2) an idleness-aware scheduling method that integrates PIM commands into available idle time windows within the CPU's access sequence. COSM not only hides PIM execution latency from the CPU, but also overlaps PIM execution with data transfer. Experiments on concurrent execution of LLMs and mobile workloads, including mobile applications and compute-intensive kernels, demonstrate that COSM improves PIM throughput by up to 2.8x compared to the baseline scheduling method with less than 2.0% CPU performance loss.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 0 minor

Summary. The paper proposes COSM, a cooperative scheduling framework for concurrent PIM and CPU execution on mobile devices to support on-device LLMs. It introduces two key innovations: (1) a low-interference PIM control interface that generates the maximum number of PIM commands without disrupting CPU memory accesses, and (2) an idleness-aware scheduling method that integrates PIM commands into idle time windows in the CPU's access sequence. The framework is claimed to hide PIM latency from the CPU and overlap PIM execution with data transfer. Experiments on concurrent LLMs and mobile workloads (applications and compute-intensive kernels) report up to 2.8x PIM throughput improvement over a baseline scheduling method with less than 2.0% CPU performance loss.

Significance. If the central claims hold under realistic evaluation on unmodified mobile hardware, the work would be significant for enabling practical PIM deployment in mobile SoCs. It directly addresses energy costs of data movement for on-device LLMs by allowing concurrent PIM/CPU operation in a shared memory space without requiring hardware modifications, which is a key constraint for mobile platforms.

major comments (2)
  1. [Abstract / Proposed mechanism] The central feasibility claim—that the low-interference PIM control interface and idleness-aware scheduler can safely interleave PIM commands with CPU traffic on unmodified commodity LPDDR memory controllers without new contention, bank conflicts, or bus congestion—lacks a concrete mechanism. The abstract states these are 'software innovations' but provides no description of how PIM commands are issued, recognized, or routed separately while preserving CPU access ordering (e.g., via existing command queues or without controller extensions). This is load-bearing for the no-hardware-change assertion and the reported 2.8x throughput gain.
  2. [Experiments / Evaluation] The experimental results (2.8x PIM throughput, <2% CPU loss) cannot be assessed for validity because the abstract supplies no methodology details: no description of the simulation or hardware platform, baseline scheduling method, workload specifics (LLM models, mobile apps, kernels), error bars, or whether the evaluation models real unmodified controllers versus an idealized PIM-capable controller. This directly impacts whether the gains demonstrate feasibility on actual mobile hardware.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the detailed and constructive review. The comments highlight areas where the abstract could better convey the paper's contributions. The full manuscript already contains the requested technical details in dedicated sections, but we are happy to revise the abstract and add cross-references to improve clarity. Point-by-point responses follow.

read point-by-point responses

  1. Referee: [Abstract / Proposed mechanism] The central feasibility claim—that the low-interference PIM control interface and idleness-aware scheduler can safely interleave PIM commands with CPU traffic on unmodified commodity LPDDR memory controllers without new contention, bank conflicts, or bus congestion—lacks a concrete mechanism. The abstract states these are 'software innovations' but provides no description of how PIM commands are issued, recognized, or routed separately while preserving CPU access ordering (e.g., via existing command queues or without controller extensions). This is load-bearing for the no-hardware-change assertion and the reported 2.8x throughput gain.

    Authors: Section 3.2 of the full manuscript describes the low-interference interface: PIM commands are generated in software by mapping to standard LPDDR command encodings and inserted into the memory controller's existing command queue during detected idle windows (via performance counter monitoring of bank and bus utilization). No controller extensions are used; ordering is preserved because PIM commands only occupy slots that the controller would otherwise leave empty, avoiding new bank conflicts or congestion. The idleness-aware scheduler (Section 4) explicitly tracks CPU access sequences to find these windows. We agree the abstract is too terse on this point and will expand it with a one-sentence mechanism summary plus a pointer to Section 3. revision: yes

  2. Referee: [Experiments / Evaluation] The experimental results (2.8x PIM throughput, <2% CPU loss) cannot be assessed for validity because the abstract supplies no methodology details: no description of the simulation or hardware platform, baseline scheduling method, workload specifics (LLM models, mobile apps, kernels), error bars, or whether the evaluation models real unmodified controllers versus an idealized PIM-capable controller. This directly impacts whether the gains demonstrate feasibility on actual mobile hardware.

    Authors: Section 5 of the manuscript details the evaluation: a cycle-accurate simulator modeling unmodified LPDDR5 controllers (no PIM extensions), baseline as a simple round-robin PIM/CPU interleaver, workloads including Llama-7B/13B inference, mobile apps (Chrome, YouTube), and kernels (GEMM, convolution), with results averaged over 10 runs and error bars shown. All experiments use the unmodified-controller model. We will add a concise methodology paragraph to the abstract and ensure the evaluation section is explicitly referenced there. revision: yes

Circularity Check

0 steps flagged

No circularity; empirical systems proposal with no derivation chain

full rationale

The paper presents a scheduling framework (COSM) with two proposed mechanisms: a low-interference PIM control interface and an idleness-aware scheduler. Performance claims (up to 2.8x PIM throughput, <2% CPU loss) rest on experimental measurements of concurrent LLM and mobile workloads. No equations, mathematical derivations, fitted parameters renamed as predictions, or self-citation load-bearing steps appear in the abstract or described structure. The work is self-contained against external benchmarks via simulation or hardware experiments; no reduction of outputs to inputs by construction exists.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 0 invented entities

No free parameters, axioms, or invented entities are identifiable from the abstract; the work is a systems scheduling proposal rather than a theoretical derivation.

pith-pipeline@v0.9.1-grok · 5787 in / 1105 out tokens · 55879 ms · 2026-06-30T03:05:01.588544+00:00 · methodology

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