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arxiv: 2606.09326 · v1 · pith:7Z656IDXnew · submitted 2026-06-08 · 🧮 math.OC

Generalized Cancellation of Capacitor Parasitic Inductance Using a Lattice Network and Its Application to Common-Mode Noise Reduction

Katsuya Nomura , Shuhei Chizuwa , Takashi Masuzawa This is my paper

Pith reviewed 2026-06-27 15:42 UTC · model grok-4.3

classification 🧮 math.OC
keywords parasitic inductance cancellationlattice networkZ-matrix transformationcommon-mode noise reductioncapacitor parasiticsvertically asymmetric latticecommon-mode choke
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The pith

Lattice network cancels capacitor parasitic inductance without vertical symmetry requirement.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper establishes a generalized technique for cancelling parasitic inductance in capacitors through a lattice network. Z-matrix equivalent transformation demonstrates that the standard vertically symmetric inductance condition is only sufficient and can be relaxed to allow vertical asymmetry. This enables cancellation by adjusting only a single inductance. The technique extends to common-mode noise reduction when paired with a common-mode choke, with both ideas confirmed through experiments.

Core claim

The Z-matrix-based equivalent transformation shows that the conventional vertically symmetric inductance condition is only a sufficient condition and can be relaxed; a vertically asymmetric lattice network then enables the parasitic inductance of capacitors to be cancelled by adjusting only one inductance, with the method extended to common-mode noise reduction using a common-mode choke.

What carries the argument

Z-matrix-based equivalent transformation applied to the lattice network, which relaxes the symmetry condition for inductance cancellation.

If this is right

  • Parasitic inductance cancellation becomes possible with adjustment of only one inductance instead of requiring matched pairs.
  • The same lattice approach combines with a common-mode choke to reduce common-mode noise.
  • Experimental results confirm both the generalized cancellation and the noise-reduction application.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • Circuit designers working at high frequencies could adopt the asymmetric lattice to simplify layout and reduce component count.
  • The relaxation may apply to other passive networks where symmetry was previously assumed necessary for cancellation effects.
  • Testing the method across wider frequency ranges or with lossy components would show where the ideal Z-matrix model deviates.

Load-bearing premise

The Z-matrix equivalent transformation remains accurate when real component parasitics, losses, and frequency-dependent effects are present.

What would settle it

Build the proposed vertically asymmetric lattice network with a capacitor and measure its impedance at the target frequency; if the parasitic inductance is not cancelled after setting the single adjustable inductance to the calculated value, the claim fails.

Figures

Figures reproduced from arXiv: 2606.09326 by Katsuya Nomura, Shuhei Chizuwa, Takashi Masuzawa.

Figure 1
Figure 1. Figure 1: (a) Lattice network and (b) T-equivalent circuit. [PITH_FULL_IMAGE:figures/full_fig_p001_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: ESL cancellation circuit. 𝐿ଶ௔ 𝐿ଶ௕ 𝐿ଵ௔ 𝐿ଵ௕ 𝐿ଶ௔ 𝐿ଶ௔ 𝐿ଶ௔ 𝐿ଶ௕ 𝐶 𝐶 𝐶 𝐶 [PITH_FULL_IMAGE:figures/full_fig_p002_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: ESL cancellation circuit for CM noise reduction. [PITH_FULL_IMAGE:figures/full_fig_p002_3.png] view at source ↗
Figure 5
Figure 5. Figure 5: Circuit diagram of the ESL cancellation circuit. [PITH_FULL_IMAGE:figures/full_fig_p003_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: Conventional cancellation circuit: (a) without and (b) with additional [PITH_FULL_IMAGE:figures/full_fig_p003_6.png] view at source ↗
Figure 7
Figure 7. Figure 7: Proposed cancellation circuit: (a) loop for [PITH_FULL_IMAGE:figures/full_fig_p003_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: shows the measured S21 results. The dashed curves represent simulated results of [PITH_FULL_IMAGE:figures/full_fig_p003_8.png] view at source ↗
Figure 10
Figure 10. Figure 10: S21 of the CM verification circuits: (a) normal circuit and (b) proposed circuit. [2] T. H. Hubing, J. L. Drewniak, T. P. Van Doren, and D. M. Hockanson, “Power bus decoupling on multilayer printed circuit boards,” IEEE Transactions on Electromagnetic Compatibility, vol. 37, no. 2, pp. 155– 166, 1995. [3] H. Wang and F. Blaabjerg, “Reliability of capacitors for dc-link applica￾tions in power electronic co… view at source ↗
read the original abstract

This letter presents a generalized technique for cancelling the parasitic inductance of capacitors using a lattice network. The Z-matrix-based equivalent transformation shows that the conventional vertically symmetric inductance condition is only a sufficient condition and can be relaxed. A vertically asymmetric lattice network is then proposed, enabling the parasitic inductance of capacitors to be cancelled by adjusting only one inductance. The method is further extended to common-mode noise reduction using a common-mode choke, and both concepts are experimentally verified.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

1 major / 1 minor

Summary. This letter proposes a generalized technique for cancelling the parasitic inductance of capacitors via a lattice network. Using Z-matrix equivalent transformation, it shows that the conventional vertically symmetric inductance condition is only sufficient and can be relaxed, allowing a vertically asymmetric lattice network that cancels the parasitic inductance by adjusting only one inductance value. The approach is extended to common-mode noise reduction by combining the lattice with a common-mode choke, and both the basic cancellation and the CM application are experimentally verified.

Significance. If the Z-matrix transformation and its extension hold under realistic parasitics and port conditions, the result provides a more flexible design method for EMI filters that reduces the number of tunable components. The experimental verification is a positive element, though the load-bearing step is the validity of the two-port Z-matrix equivalence when the lattice is placed in series with a coupled common-mode choke.

major comments (1)
  1. [extension to common-mode choke] The Z-matrix equivalence is derived under a two-port lumped-element model for the lattice network. When the vertically asymmetric lattice is placed in series with a common-mode choke (which introduces mutual coupling and effectively a multi-port configuration), the transformation no longer maps directly unless the choke's mutual inductance is shown to preserve the null condition. The manuscript should provide the combined impedance expression or re-derived cancellation condition for the full network (see the extension section following the lattice proposal).
minor comments (1)
  1. The abstract states experimental verification but does not specify the frequency range, component values, or how closely the measured CM impedance null matches the predicted Z-matrix null; adding these quantitative details would strengthen the claims.

Simulated Author's Rebuttal

1 responses · 0 unresolved

We thank the referee for the constructive feedback on our manuscript. We address the single major comment below regarding the extension to the common-mode choke, agreeing that an explicit combined expression would improve clarity.

read point-by-point responses

  1. Referee: [extension to common-mode choke] The Z-matrix equivalence is derived under a two-port lumped-element model for the lattice network. When the vertically asymmetric lattice is placed in series with a common-mode choke (which introduces mutual coupling and effectively a multi-port configuration), the transformation no longer maps directly unless the choke's mutual inductance is shown to preserve the null condition. The manuscript should provide the combined impedance expression or re-derived cancellation condition for the full network (see the extension section following the lattice proposal).

    Authors: We agree that the initial Z-matrix derivation applies to the lattice network in isolation. In the extension, the common-mode choke is incorporated by modeling the full series combination as an effective two-port network under common-mode excitation, where the choke's self- and mutual inductances appear symmetrically. The lattice's negative inductance term continues to null the capacitor parasitic inductance because the mutual coupling does not alter the differential cancellation path derived from the Z-matrix transformation. Nevertheless, to address the concern directly, we will add the combined impedance expression and re-derived null condition in the revised manuscript. The existing experimental results remain valid as empirical confirmation of the overall behavior. revision: yes

Circularity Check

0 steps flagged

No circularity: Z-matrix transformation is an independent algebraic derivation

full rationale

The central claim rests on applying the standard Z-matrix equivalent transformation to a lattice network model to demonstrate that vertical symmetry is sufficient but not necessary. This is a direct matrix equivalence on the two-port network parameters and does not reduce to any fitted parameter, self-citation, or redefinition of the target result. The subsequent proposal of an asymmetric lattice and its extension to a common-mode choke are presented as applications of that algebraic result, with experimental verification cited separately. No load-bearing step in the described derivation chain collapses to an input by construction.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 0 invented entities

No full text available; cannot enumerate free parameters, axioms, or invented entities.

pith-pipeline@v0.9.1-grok · 5607 in / 1008 out tokens · 17201 ms · 2026-06-27T15:42:09.563398+00:00 · methodology

discussion (0)

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Reference graph

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