A Novel Synchronous Reference Frame Frequency-Locked Loop

Alex Q. Huang; Qinran Hu; Xiangjun Quan; Xiaobo Dou; Zaijun Wu

REVIEW 2 major objections 6 minor 9 references

A Novel Synchronous Reference Frame Frequency-Locked Loop

T0 review · 2 major / 6 minor · reviewed 2026-08-14 · deepseek-v4-flash

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Pith's one-line read This paper claims that feeding the dq-frame phase error through the loop filter $G(s)=ds/(V(s+k))$ makes the frequency estimate a first-order system, so gain $d$ can be raised without degrading damping.

desk verdict A genuinely new FLL architecture with a clean small-signal design story, held back by a hidden linearization assumption and a few skipped algebraic steps. read the letter →

arxiv 1908.08669 v3 pith:A7LOSMXO submitted 2019-08-23 eess.SY cs.SY

Xiangjun Quan , Qinran Hu , Alex Q. Huang , Xiaobo Dou , Zaijun Wu This is my paper · ORCID

classification eess.SYcs.SY

keywords frequency-lockedloopsynchronousreferenceframedqphaseerrorfilterfirst-orderfrequencyestimationgridsynchronizationinvertercontrol

verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

Grid-connected inverters need to estimate the grid frequency and phase quickly and cleanly. This letter proposes doing frequency-locked-loop estimation in the synchronous dq reference frame rather than the stationary $\alpha\beta$ frame, where small-signal modeling is harder. The key claim is that by feeding the dq-frame phase error $u_q$ through the loop filter $G(s)=d s/(V(s+k))$, the frequency-estimate transfer function becomes a first-order low-pass filter $\Delta\hat{\omega}/\Delta\omega = d/(s+d)$. That lets the frequency-estimation gain $d$ be increased to speed up response without pushing the loop into overshoot, which the conventional FLL cannot do. A sympathetic reader would care because grid synchronization is a basic building block of inverter control, and the paper offers a parameter-tuning rule that is simpler than the second-order models used for existing FLLs.

What carries the argument

The load-bearing object is the small-signal block diagram of the frequency-estimation loop in the dq frame (Fig. 2). The auxiliary complex variable $x_a = \mathrm{conj}(\hat{\mathbf{u}}_{dq})\mathbf{u}_{dq}$ is a complex low-pass filter whose imaginary part $x_{aI}$ carries the frequency error, while the q-axis voltage $u_q$ carries the phase error. Feeding $u_q$ through $G(s)=d s/(V(s+k))$ adds a term that cancels the prefilter pole at $-k$, turning the open-loop gain into $d/s$ and the closed-loop frequency estimate into a first-order low-pass filter with pole at $-d$. The same algebraic relation allows this filter to be realized without an extra filter block, by scaling the estimate error $\hat{u}_q-u_q$ by $d/V$ and integrating.

What would settle it

Apply a 20-degree phase step with $d$ set to several times $k$ and compare the measured frequency estimate to the first-order prediction $\Delta\hat{\omega}/\Delta\omega=d/(s+d)$; overshoot or a settling time that does not scale as $1/d$ would show the small-signal derivation misses the transient.

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Extended reading notes

Core claim

The paper's central discovery is that a frequency-locked loop implemented in the synchronous dq frame can use both frequency error (from $x_{aI}$, the imaginary part of a conjugate auxiliary variable) and phase error (from $u_q$) at the same time. Selecting the extra loop filter $G(s)=d s/(V(s+k))$ cancels the prefilter pole and converts the frequency-estimation closed loop into the first-order transfer function $\Delta\hat{\omega}/\Delta\omega = d/(s+d)$. The phase-corrected estimate $\hat{\omega}_b$ has poles at $-k$ and $-d$, so both characteristic roots are real for any positive $d$ and $k$. Consequently, unlike the conventional FLL whose damping ratio falls as the frequency gain rises, the SRF-FLL can raise $d$ to speed up tracking while keeping overdamped behavior; with the same prefilter $k$ it also has stronger high-frequency attenuation. The paper verifies this with bench experiments on frequency steps, phase steps, and amplitude sags.

Load-bearing premise

The derivation assumes the phase error stays close to zero and the frequency error is much smaller than the prefilter gain $k$; if a large transient violates that, the first-order transfer function is not guaranteed.

Editorial extensions

If this is right

With the same prefilter gain $k$, the proposed SRF-FLL can choose a larger frequency-estimation gain $d$, making the frequency response faster without the overshoot that appears in the conventional FLL at large $d$.
The frequency estimate $\hat{\omega}$ is a first-order system, so its settling time is set directly by $d$; this gives a simpler tuning rule than the second-order model used for conventional FLLs.
The phase-corrected estimate $\hat{\omega}_b$ has two real poles ($-k$ and $-d$), meaning overdamped response for all positive $k,d$, and is recommended as the final frequency output because it handles phase-step transients well.
The extra loop filter $G(s)$ is an additional design degree of freedom; the paper notes that choosing a PI controller in that path would drive $u_q$ to zero and produce a hybrid PLL-FLL behavior, which it leaves for future study.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

The paper's verification is limited to the fundamental positive-sequence component; harmonic and unbalanced-grid operation is delegated to additional prefilters, so the claimed improvement is demonstrated only for clean fundamental-voltage conditions.
The pole-zero cancellation in $G(s)$ assumes exact knowledge of $V$ and $k$; voltage sags or parameter drift would leave residual dynamics that the paper does not quantify.
The dq-frame construction suggests a family of loop filters $G(s)$: a PI choice would blend PLL and FLL behavior, while resonant choices could target specific harmonics without adding integrators to the main frequency loop.

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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Desk Editor's Note

read the letter

The paper does something real: it moves the FLL into the dq frame and uses the q-axis voltage as an explicit phase-error path. The baseline equivalence between SRF-FLL0 and the conventional FLL is a clean restatement, and the improved loop with G(s) is a genuine new architecture. The first-order frequency-loop result, eq. (18), is a useful design simplification: it makes the frequency-estimate gain d directly settable without touching the damping. That is worth having, and the Bode plots and step responses back it up over the tested range.

The main soft spot is the one the stress-test flags: eq. (18) is derived under the linearizations θe≈0 and ωe<

The second issue is presentation. The step from the open-loop gain (15) to the selection of G(s) in (16)-(17) is shown in a compressed way; a reader has to guess at the algebra. The same goes for the transition from the generic G(s) to the concrete first-order result. This is a minor fix.

The experimental section is visual and single-platform, which is typical for a letter, but I'd like at least one quantitative comparison against the derived transfer functions. Also, the harmonic-rejection discussion is thin; the claim of better filtering is only checked on the fundamental sequence.

Who gets value from this? Researchers working on grid synchronization or inverter control in a power-electronics group. The novel dq-frame phase-error path is the kind of idea that will spawn follow-ups. The math is mostly sound and the citation pattern is fine; the main thing missing is proof that the design behaves as advertised outside the small-signal neighborhood.

I would send this to peer review. It's a solid original contribution with a fixable gap, not a paper that should be desk-rejected.

Referee Report

2 major / 6 minor

Summary. The paper proposes a synchronous-reference-frame frequency-locked loop (SRF-FLL). It first defines SRF-FLL0, a dq-frame structure whose small-signal frequency-estimation transfer function is shown to be identical to that of the conventional αβ-frame FLL when the frequency gain is set to D=kd/V². It then augments SRF-FLL0 with a phase-error path G(s) and selects G(s)=d s/[V(s+k)], which collapses the open-loop gain to d/s. The resulting frequency estimate satisfies Δω̂/Δω = d/(s+d), i.e., a first-order response, and the alternative estimate ω̂_b has denominator (s+k)(s+d), giving real roots. The paper gives tuning guidelines, Bode plots, and experimental comparisons for frequency and phase steps, concluding that the proposed SRF-FLL has better filtering and transient performance than the conventional FLL with the same prefilter parameter k.

Significance. If the small-signal result holds over the intended operating range, the contribution is useful: it introduces an extra design degree of freedom for FLLs, gives a simple realization of G(s) through Eq. (20), and provides a clear explanation of why increasing the frequency-estimate gain does not degrade damping in the linearized model. The derivation is self-contained and the transfer functions are internally consistent; the equivalence of SRF-FLL0 with the conventional FLL is a clean analytic result. The experimental comparison against the conventional FLL under the same k supports the claimed improvement for the tested operating points.

major comments (2)

[§III.A, Eqs. (17)–(18), Fig. 5] The first-order frequency-estimate result and the guideline that 'd can be increased without deteriorating damping' are derived from a small-signal model built on the assumptions θe≈0 and ωe<<k, stated before Eq. (8) and before Eq. (14). The experimental validation uses +5 Hz frequency steps and 20° phase steps with k=120π, so initially ωe/k≈0.083 and sinθe/θe≈0.98; these tests stay within the linearization but do not probe its boundary. Because Table I and the conclusion state the claim unconditionally, the manuscript should either provide a nonlinear stability and performance check (for example, simulations with ωe/k approaching unity and larger phase steps) or explicitly restrict the claim to the small-signal regime.
[§III.A, Eq. (16), Fig. 3] The cancellation that produces the open-loop gain d/s in Eq. (17) requires exact knowledge of the grid-voltage amplitude V inside G(s)=d s/[V(s+k)], but the manuscript does not say how V is obtained or updated in the implementation. If the actual amplitude differs from the value used in G(s), the open-loop gain becomes d/s · [k+(V_act/V_nom)s]/(s+k), so the frequency estimate is no longer exactly first order and the damping-independence property is lost. The amplitude-sag test in Fig. 8(a) should be accompanied by a statement of how V is handled or by a sensitivity analysis.

minor comments (6)

[Abstract] The abstract contains typographical errors such as 'propose s' and 'acquir e'; the manuscript should be proofread.
[§II.B, Eq. (14)] Equation (14) is typeset ambiguously; the intended relation ω̂ = D x_aI/s + G(s) u_q should be written with explicit parentheses so that the two signal paths are clear.
[§IV.B] The sentence 'The selection of k has no inference for the comparison results' should read 'no influence'.
[Figs. 8–9] The axes of Figs. 8 and 9 lack clear numerical scales for the estimated quantities; annotating settling times or overshoot values would make the claimed improvements quantitative.
[§IV.B] The manuscript should state the discretization method and sampling frequency used on the TMS320F28379D testbed, since the experimental results are obtained digitally.
[References] Reference [6] is cited as 'vol. PP, no. 99, pp. 1–1'; please update it to the final publication data.

Circularity Check

0 steps flagged · score 0.0 of 10

No circularity found; the SRF-FLL derivation is self-contained synthesis, not a reduction to its inputs.

full rationale

The paper's derivation chain is self-contained. It begins with the conventional FLL transfer function (1), attributed to the external reference [9], and constructs the SRF-FLL0 by transforming the ROGI into the dq frame. With the conventional gain choice D = kd/V^2 in Eq. (9), the closed-loop transfer function (10) is shown by direct algebra to reproduce Eq. (1), which is a verification of equivalence rather than an assumed premise. The improved SRF-FLL then adds a phase-error path through G(s). Equation (15) gives the open-loop gain, and Eq. (16) is an explicit design choice, G(s) = d s / (V(s+k)). Substituting this choice into (15) collapses the open-loop gain to d/s in Eq. (17), and the closed-loop transfer function becomes d/(s+d) in Eq. (18). This is controller synthesis: the claimed first-order behavior is the designed consequence of the chosen G(s), not an input that is later relabeled as a prediction. The small-signal assumptions theta_e approximately 0 and omega_e much less than k are stated before Eqs. (8) and (14); they limit the validity of the linearized model during large transients, but this is a correctness or robustness limitation, not a circular step. The only self-citation, reference [6], is cited as an example of ROGI-based FLLs and as an option for multiple prefilters; it is peripheral and not load-bearing for the new result. The experimental comparisons in Figs. 5-7 are consistency checks of the derived transfer functions and parameter sweeps, not fitted predictions. No step in the paper reduces by definition to its own input.

Assumptions & free parameters 3 free parameters · 4 assumptions · 0 invented entities

The design uses two tunable gains (k and d) plus a conventional normalization D=k d/V². No physical entities are invented. The main assumptions are small-signal linearization (θ_e≈0, ω_e<<k) and a balanced fundamental input; these are standard for grid-synchronization letters and are stated in the text.

free parameters (3)

k = k=120π and 60π in experiments and Bode plots
Prefilter gain that sets the bandwidth of the complex LPF in eq (2); chosen by the designer as a trade-off between filtering and settling time.
d = d=2k, k, 0.5k, 0.25k tested; d=k recommended
Normalized frequency-estimate gain; sets the first-order bandwidth in eq (18) and the damping of the conventional FLL.
D = D = k d / V²
Frequency-estimate integrator gain selected in eq (9), a conventional choice from the cited literature, so that SRF-FLL0 matches the conventional FLL transfer function.

assumptions (4)

domain assumption The frequency error is much smaller than the prefilter gain during transients (ω_e << k).
Used to approximate the auxiliary-variable dynamics in eqs (6) and (8) and to build the small-signal model. Stated in Section II.A before eq (8).
domain assumption The phase error is small (θ_e ≈ 0) for the small-signal model.
Stated in Section II.B before eq (14); required for the linearized block diagram in Fig. 2 and for u_q ≈ V θ_e.
domain assumption The input is a balanced fundamental positive-sequence voltage.
Used in eq (3); harmonic and imbalance rejection is deferred to multiple prefilters as noted in Section IV.B.
standard math The transfer function of the conventional FLL reported in [9] is correct.
Used in eq (1) as the benchmark to establish the equivalence of SRF-FLL0.

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Cite this review

Pith. "Pith review of A Novel Synchronous Reference Frame Frequency-Locked Loop." pith.science (2026). https://pith.science/paper/A7LOSMXO

@misc{pith2026190808669,
  author       = {Pith},
  title        = {Pith review of: A Novel Synchronous Reference Frame Frequency-Locked Loop},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/A7LOSMXO}},
  note         = {Machine review of arXiv:1908.08669}
}

read the original abstract

This letter proposes a new design of frequency-locked loop (FLL) which is based on synchronous (dq) reference frame instead of stationary ({\alpha}\b{eta}) reference frame. First, a synchronous reference frame FLL (briefly called SRF-FLL0) equivalent to the conventional FLL is proposed. Then the SRF-FLL0 is improved by utilizing the phase error to acquire a better performance. The small-signal modeling and parameter tuning of the improved synchronous reference frame FLL (SRF-FLL) are presented. Finally, the theoretical analysis and experiment results verify the superiority and effectiveness of proposed SRF-FLL.

Discussion (0). Continue with ORCID to comment.

Reference graph

Works this paper leans on

9 extracted references · 9 canonical work pages

[1]

T hree-phase PLLs: A review of recent advances,

S. Golestan, J. M. Guerrero, and J. C. Vasquez, “T hree-phase PLLs: A review of recent advances,” IEEE Trans. Power Electron., vol. 32, no. 3, pp. 1894–1907, Mar. 2017

work page 1907
[2]

A Study on Three -Phase FLLs,

S. Golestan, J. M. Guerrero, J. C. Vasq uez, A. M. Abusorrah and Y. Al-Turki, "A Study on Three -Phase FLLs," in IEEE Transactions on Power Electronics, vol. 34, no. 1, pp. 213-224, Jan. 2019

work page 2019
[3]

Re-investigation of generalized integrator based filters from a first-order-system perspective,

Z. Xin, R . Zhao, P . Mattavelli, P. C. Loh, and F. Blaabjerg, “Re-investigation of generalized integrator based filters from a first-order-system perspective,” IEEE A ccess, vol. 4, pp. 7131 –7144, 2016

work page 2016
[4]

Multireso nant frequency -locked loop for grid synchronization of power converte rs under distorted grid con ditions,

P. Rodr´ ıguez, A. Luna, I. Candela, R. Mujal, R. Teodorescu, an d F. Blaabjerg, “Multireso nant frequency -locked loop for grid synchronization of power converte rs under distorted grid con ditions,” IEEE Trans. Ind. Electron., vol. 58, no. 1, pp. 127–138, Jan. 2011

work page 2011
[5]

Adaptive vectorial filter for grid synchronization of power converters under unbal anced and/or distorted grid conditions,

S. Vazquez, J. A. Sanchez, M. R. Reyes, J. I. Leon, J. M . Carrasc o, “Adaptive vectorial filter for grid synchronization of power converters under unbal anced and/or distorted grid conditions,” IEEE Trans. Ind. Electron., vol. 61, no. 3, pp. 1355–1367, Mar. 2014

work page 2014
[6]

Complex-coefficient complex -variable-filter for grid synchronization based on linear quadratic regulation,

X. Quan, X. Dou, Z. Wu, M. Hu, and A. Q. Huang, “Complex-coefficient complex -variable-filter for grid synchronization based on linear quadratic regulation,” IEEE Trans. Ind. Informat., vol. PP, no. 99, pp. 1–1, 2017

work page 2017
[7]

Multiple-complex coefficient-filter-based phase-locked loop and synchronization technique for three-phase grid-interfaced converters in distributed utility networks,

X. Guo, W. Wu, and Z. Chen, “Multiple-complex coefficient-filter-based phase-locked loop and synchronization technique for three-phase grid-interfaced converters in distributed utility networks,” IEEE Trans. Ind. Electron., vol. 58, no. 4, pp. 1194–1204, Apr. 2011

work page 2011
[8]

Frequency adaptive discrete filter for gr id synchronization under distorted voltages,

S. G. Jorge, C. A . Busada, and J. A. Solsona, “Frequency adaptive discrete filter for gr id synchronization under distorted voltages,” IEEE Trans. Power Electron., vol. 27, no. 8, pp. 3584–3594, Aug. 2012

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[9]

High -Order Frequency-Locked Loops: A Critical Analysis,

S. Golestan, J. M. Guerrero an d J. C. Vasquez, "High -Order Frequency-Locked Loops: A Critical Analysis," in IEEE Transactions on Power Electronics, vol. 32, no. 5, pp. 3285-3291, May 2017

2017

Pith tools

Reviewed August 14, 2026 · model on record in the stance chip above.

[1] [1]

T hree-phase PLLs: A review of recent advances,

S. Golestan, J. M. Guerrero, and J. C. Vasquez, “T hree-phase PLLs: A review of recent advances,” IEEE Trans. Power Electron., vol. 32, no. 3, pp. 1894–1907, Mar. 2017

work page 1907

[2] [2]

A Study on Three -Phase FLLs,

S. Golestan, J. M. Guerrero, J. C. Vasq uez, A. M. Abusorrah and Y. Al-Turki, "A Study on Three -Phase FLLs," in IEEE Transactions on Power Electronics, vol. 34, no. 1, pp. 213-224, Jan. 2019

work page 2019

[3] [3]

Re-investigation of generalized integrator based filters from a first-order-system perspective,

Z. Xin, R . Zhao, P . Mattavelli, P. C. Loh, and F. Blaabjerg, “Re-investigation of generalized integrator based filters from a first-order-system perspective,” IEEE A ccess, vol. 4, pp. 7131 –7144, 2016

work page 2016

[4] [4]

Multireso nant frequency -locked loop for grid synchronization of power converte rs under distorted grid con ditions,

P. Rodr´ ıguez, A. Luna, I. Candela, R. Mujal, R. Teodorescu, an d F. Blaabjerg, “Multireso nant frequency -locked loop for grid synchronization of power converte rs under distorted grid con ditions,” IEEE Trans. Ind. Electron., vol. 58, no. 1, pp. 127–138, Jan. 2011

work page 2011

[5] [5]

Adaptive vectorial filter for grid synchronization of power converters under unbal anced and/or distorted grid conditions,

S. Vazquez, J. A. Sanchez, M. R. Reyes, J. I. Leon, J. M . Carrasc o, “Adaptive vectorial filter for grid synchronization of power converters under unbal anced and/or distorted grid conditions,” IEEE Trans. Ind. Electron., vol. 61, no. 3, pp. 1355–1367, Mar. 2014

work page 2014

[6] [6]

Complex-coefficient complex -variable-filter for grid synchronization based on linear quadratic regulation,

X. Quan, X. Dou, Z. Wu, M. Hu, and A. Q. Huang, “Complex-coefficient complex -variable-filter for grid synchronization based on linear quadratic regulation,” IEEE Trans. Ind. Informat., vol. PP, no. 99, pp. 1–1, 2017

work page 2017

[7] [7]

Multiple-complex coefficient-filter-based phase-locked loop and synchronization technique for three-phase grid-interfaced converters in distributed utility networks,

X. Guo, W. Wu, and Z. Chen, “Multiple-complex coefficient-filter-based phase-locked loop and synchronization technique for three-phase grid-interfaced converters in distributed utility networks,” IEEE Trans. Ind. Electron., vol. 58, no. 4, pp. 1194–1204, Apr. 2011

work page 2011

[8] [8]

Frequency adaptive discrete filter for gr id synchronization under distorted voltages,

S. G. Jorge, C. A . Busada, and J. A. Solsona, “Frequency adaptive discrete filter for gr id synchronization under distorted voltages,” IEEE Trans. Power Electron., vol. 27, no. 8, pp. 3584–3594, Aug. 2012

work page 2012