Toward Lifelong-Sustainable Electronic-Photonic AI Systems via Extreme Efficiency, Reconfigurability, and Robustness

Chetan Choppali Sudarshan; Hongjian Zhou; Jiaqi Gu; Vidya Chhabria; Ziang Yin

REVIEW 4 major objections 5 minor 44 references

Toward Lifelong-Sustainable Electronic-Photonic AI Systems via Extreme Efficiency, Reconfigurability, and Robustness

T0 review · 4 major / 5 minor · reviewed 2026-08-04 · deepseek-v4-flash

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Pith's one-line read Electronic-photonic AI chips can beat conventional accelerators on both carbon per task and performance per unit carbon.

desk verdict Useful sustainability framework for EPIC AI hardware, but the central carbon comparison is undercut by using raw TOPS instead of SLA-compliant throughput and hand-assigned lifetimes. read the letter →

arxiv 2509.07396 v1 pith:AVCD74CW submitted 2025-09-09 physics.optics cs.AIcs.ET

Ziang Yin , Hongjian Zhou , Chetan Choppali Sudarshan , Vidya Chhabria , Jiaqi Gu This is my paper

classification physics.opticscs.AIcs.ET

keywords electronic-photonicintegratedcircuitscarbonfootprintAIacceleratorsreconfigurablephotoniccomputingcross-layerco-designdesignautomationcarbon-awaremetricssustainable

verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

Photonic AI accelerators have usually been discussed as speed and energy winners; this paper argues they also win on carbon when the metric is carbon per completed task rather than total footprint. It splits carbon into embodied and operational parts, amortizes the embodied part over the hardware's useful life, and compares devices by carbon per task and throughput per unit carbon. Using case studies of co-designed photonic systems, it claims that cross-layer optimization shrinks die area and power, that reconfigurability extends functional lifetime and amortizes embodied carbon over more tasks, and that automated photonic layout generates compact, routable chips in minutes. The central empirical result is that electronic-photonic designs occupy the upper-right region of the carbon-performance curve, beating electronic baselines on both footprint per task and throughput per carbon. If right, this reframes AI sustainability: the best carbon strategy is not only energy efficiency but designing hardware that is compact, adaptable, and long-lived.

What carries the argument

The load-bearing object is the carbon-per-task metric CFP_task = C_emb/N_life + CI_use × P_active/Θ and its companion ratio Perf/CFP. This metric is what makes different chips comparable: it converts embodied carbon into a per-inference cost by dividing by the lifetime number of tasks, and adds the per-task operating carbon. Because the lifetime term appears in the denominator, the metric rewards hardware that is reconfigurable enough to stay useful as workloads change; and because it is normalized, it lets the authors plot all devices on a single carbon-performance curve. The metric is the argument: whoever controls the lifetime controls the comparison.

What would settle it

Take a fixed-function photonic accelerator with the published power and TOPS numbers and compute, via Eq. 5, how many years of continuous operation it would need to match the per-task carbon of the reconfigurable CHORD system at its assumed 5-year life; if that crossover is below one year for a realistic workload, the amortization argument for reconfigurability falls apart. The same calculation can be run on the table's numbers without any new hardware.

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Extended reading notes

Core claim

The central claim is that, measured per delivered task, electronic-photonic AI systems can be both cheaper in carbon and higher-performing per unit carbon than state-of-the-art electronic accelerators. The authors arrive at this by writing total carbon as embodied plus operational, then normalizing embodied carbon by the lifetime number of tasks and operational carbon by throughput and grid carbon intensity, producing a per-task carbon number and a performance-per-carbon ratio. They apply the framework to published accelerators using stated lifetimes and show that reconfigurable photonic designs occupy the upper-right corner of the curve, while a co-optimized design moves markedly up-right f

Load-bearing premise

The load-bearing premise is that the deployment lifetimes in Table II are realistic—5 to 7 years for electronic chips, 5 years for reconfigurable photonic systems, and 0.2 years for fixed-function CHORD—because those lifetimes set the amortization of embodied carbon in Eq. 5; if a fixed-function system is used for even a year, or a reconfigurable system is not actually retrained across tasks, the claimed carbon advantage changes or disappears.

Editorial extensions

If this is right

Hardware selection should be based on lifetime carbon per task, not peak power or raw total carbon, which penalizes efficient chips that are used only briefly.
Reconfigurable photonic accelerators become a sustainability instrument: retraining a fabricated chip for a new model avoids the embodied carbon of fabricating a replacement.
Automated photonic layout tools that shrink die area and metal layers are a direct lever on embodied carbon, so design automation belongs in the carbon budget.
For AI hardware generally, the dominant carbon terms imply that extending device life and enabling multi-workload reuse may outperform further energy-efficiency gains.
The same two-metric comparison can be applied during early design to choose among device, circuit, and architecture options by their predicted lifetime carbon impact.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

Extending the metric to include the carbon cost of retraining and recalibration would test whether reconfigurability remains a net win once updates are charged.
The same two-metric comparison could be applied to digital in-memory accelerators to check whether the photonic advantage is structural or an artifact of the chosen electronic baselines.
A controlled study comparing embodied carbon of an automated layout versus a manual layout for the same circuit would turn the automation argument into a testable number.
The paper's logic implies an optimization objective—maximize lifetime tasks per unit embodied carbon—that could be used as a search criterion in future accelerator design.

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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Desk Editor's Note

read the letter

Here's my take. This is a perspective/roadmap piece on sustainability of electronic-photonic AI hardware. The genuinely useful part is the carbon-normalized comparison framework: separating embodied vs operational carbon and computing CFP per task and performance-per-carbon for a broad set of accelerators. That framework is a legitimate, clear extension of ECO-CHIP's accounting, and it gives the community a common yardstick for comparing EIC vs EPIC sustainability. The EPDA results (Apollo/LiDAR) are also well presented and are real contributions from prior papers.

The weak spot is the quantitative evidence behind the central chart. Fig. 8 uses raw TOPS as the performance metric, but Eq. 5 defines CFP per task using throughput at an SLA point. TOPS is not task throughput: it ignores accuracy differences. Table I shows CHORD's accuracy is substantially below a digital CNN on CIFAR-10 and CIFAR-100. If you normalize by correct inferences per second instead of TOPS, the 'upper-right' position of EPICs may shrink significantly. This affects every EPIC row, so it is more fundamental than the lifetime assumptions.

The lifetime choices are also post hoc, especially the 0.2-year lifetime for fixed-function CHORD. That number drives the amortization of embodied carbon in Eq. 5 and makes reconfigurability look much better. The paper states these are assumptions, but no sensitivity analysis is given. A fixed-function system might be used for a few years, and a reconfigurable system might not actually be retrained across tasks in practice, so the advantage is not as robust as claimed.

What about novelty? The paper is mostly a re-packaging of the authors' prior results, with the carbon metrics being simple normalizations. That's okay for a perspective, but it means the paper is not a new experimental or theoretical result. The real value is the synthesis and the call for sustainability-aware design automation.

Overall, the paper is well written and the framework is useful, but the central claim needs more validation. A serious referee should ask for a sensitivity analysis over lifetimes, a clear definition of throughput in the carbon metrics, and ideally an accuracy-aware performance comparison. I'd send it to peer review rather than desk reject, but with expectation of major revision.

Who is this for? Researchers working on photonic AI hardware, design automation, or sustainable computing. It's a good discussion piece. I'd probably bring it to a reading group if the group cares about hardware sustainability metrics. I wouldn't depend on the quantitative claims in my own work until the inputs are validated, but the metric definitions are worth citing.

Recommendation: engage with the work, but treat Fig. 8 as a hypothesis, not a demonstrated result. Peer review should encourage revision rather than rejection.

Referee Report

4 major / 5 minor

Summary. The paper is a perspective/vision article arguing that electronic-photonic integrated circuits (EPICs) can deliver 'lifelong-sustainable' AI hardware through three pillars—extreme efficiency, reconfigurability, and robustness—amplified by electronic-photonic design automation (EPDA). It reviews several recent photonic accelerator case studies (SCATTER, LightningTransformer, TeMPO, CHORD) and two PIC layout tools (Apollo, LiDAR). The quantitative core is a carbon-aware performance analysis (Sec. IV) that separates embodied and operational carbon, defines CFP per task and performance per carbon, and uses Fig. 8 to claim that EPIC designs consistently occupy the upper-right region of the carbon–performance tradeoff, i.e., reduced carbon per task and higher performance per unit carbon. The paper also reports concrete EPDA benchmark results in Table III.

Significance. If the quantitative claim were supported, the paper would make an important contribution to the emerging literature on sustainable AI hardware: it would quantify, through a standardized carbon model, that reconfigurable and robust photonic systems can outperform conventional electronics on a carbon-normalized basis. The paper's strengths are its broad synthesis of recent work, the concrete and reproducible-looking EPDA benchmark numbers in Table III, and its clear articulation of carbon-aware metrics. However, the central Fig. 8 conclusion is currently not adequately supported: the performance metric used in the carbon comparison is raw TOPS rather than SLA task throughput, and the amortization lifetimes that drive the reconfigurability conclusion are hand-assigned. These issues affect the main claim, not just presentation.

major comments (4)

[Sec. IV-C, Eq. (5), Fig. 8] Eq. (5) defines Θ as throughput at an SLA operating point (tasks/s), but Fig. 8 uses raw TOPS as the performance metric in TOPS/CFP. Raw TOPS ignores accuracy. Table I shows this is not a minor discrepancy: CHORD achieves only 0.618 accuracy on CIFAR-10 versus 0.763 for a digital CNN, 0.382 versus 0.435 on CIFAR-100, and post-fabrication adaptation degrades to 0.2513. If raw TOPS is substituted for Θ, the claimed 'upper-right' region measures peak arithmetic throughput per carbon, not completed tasks per carbon. The central sustainability conclusion requires redoing the comparison with task-level throughput at matched accuracy, or at least applying an explicit accuracy correction to the EPIC rows.
[Sec. IV-B, Table II, Eq. (5)] The amortization term C_emb/N_life is directly controlled by hand-assigned lifetimes. CHORD without reconfigurability is assigned a 0.2-year lifetime, while CHORD with reconfigurability is assigned 5 years; this makes the reconfigurability benefit an input rather than an output of the analysis. No empirical basis or sensitivity study is provided for the 0.2-year value. A fixed-function system used for even one year would substantially change the plotted advantage. Moreover, Eq. (5) defines N_life as a 'lifetime number of tasks,' while Table II lists lifetimes in years, so the units in the embodied term are inconsistent. The authors should report a lifetime sensitivity sweep and use a consistent task-count or years-with-throughput formulation.
[Sec. IV, Table II] The EPIC area, power, and TOPS values in Table II come from the authors' own architecture simulations, with no uncertainty bounds or comparison to fabricated silicon. The carbon model treats these simulated values with the same apparent precision as the commercial H100/TPU and fabricated EIC entries. This makes the 'consistently occupy upper-right' claim in Fig. 8 depend on unvalidated inputs. The authors should state clearly which values are simulated, provide uncertainty ranges if possible, and soften the claim accordingly.
[Sec. IV-C, Fig. 8] The figure caption defines only the y-axis (TOPS/CFP); the x-axis is not defined in the text, and the phrase 'upper-right region' is not self-evidently consistent with 'reduced carbon footprint per task.' If the x-axis is total CFP, upper-right would imply high CFP, which contradicts the stated conclusion; if it is an inverse metric, the axes should be labeled explicitly. The paper should clarify the axes and explain why upper-right corresponds to the most sustainable designs.

minor comments (5)

[Eq. (4)] The expression P_active = workload ops / (TOPS/W) is dimensionally awkward (ops divided by TOPS/W gives W, but the notation should be made explicit). Suggest rewriting in terms of operations per second and energy per operation.
[Table I and Sec. II-B] In Table I, 'A 2-layer digital CNN (C32K3) ×2' is unclear; please expand the notation and state whether it is the same task for all rows. Also, the post-fab adaptation rows should specify how many epochs or training steps were used.
[Sec. VI / References] Reference [35] duplicates reference [22] (both cite CHORD at DAC 2025). Please consolidate.
[Sec. II-C] The sentence 'ELight introduces a framework that introduces Write-aware training' contains a redundant 'introduces'; please rephrase.
[Fig. 8] The axis labels and units should be added directly to the figure; currently the caption only identifies the y-axis, and the x-axis label is missing from the text extraction.

Circularity Check

1 steps flagged · score 6.0 of 10

Reconfigurability benefit in the carbon model reduces to the chosen lifetime input (0.2 vs 5 years), not to measured behavior.

fitted input called prediction [Table II and Sec. IV-C (Eq. 5 and CHORD discussion)]
"Lifetimes are chosen to reflect typical deployment horizons used in prior carbon-aware hardware analyses and industry practice: we assign 5 years to convolution-only ASICs ... and 7 years to Transformer-capable accelerators ... [Table II:] CHORD w/o Reconfig. ... Lifetime (Years) 0.2; CHORD w/ Opt. ... Lifetime (Years) 5 ... [Sec. IV-C:] Its longer functional lifetime can amortize embodied carbon across many more tasks and application generations, driving its CFP_task lower."

Eq. (5) defines CFP_task = C_emb/N_life + CI_use*P_active/Theta, so N_life directly divides the embodied term. Table II assigns CHORD w/o Reconfig. 0.2 years and CHORD w/ Opt. 5 years, a 25x difference. The paper's conclusion that reconfigurable CHORD has lower CFP_task because of its 'longer functional lifetime' is an arithmetic restatement of the chosen N_life values, not an empirical result. With a comparable fixed-function lifetime the advantage would shrink or vanish. Thus the 'prediction' reduces to the input lifetime.

full rationale

The main circular reduction is the CHORD reconfigurability comparison: the sustainability benefit is obtained by assigning 0.2 years to the non-reconfigurable version and 5 years to the reconfigurable version, then reading the resulting CFP_task difference back as a demonstrated advantage. Other elements are not circular: the device area/power/TOPS data are taken from published designs (several by the authors, but used as external data sources and reported with citations), the Apollo/LiDAR results are benchmarked against DREAMPlace and a manual flow, and the ECO-CHIP carbon model is an adopted framework rather than a conclusion derived from itself. The use of TOPS in Fig. 8 while Eq. (5) is defined with SLA task throughput is a metric-normalization concern that affects the strength of the task-level claim, but it is not itself an input-equal-output reduction, so it does not add to the circularity score. Overall: partial circularity in the central reconfigurability claim, with the rest of the paper self-contained against external data.

Assumptions & free parameters 4 free parameters · 4 assumptions · 0 invented entities

The central comparison in Fig. 8 is determined by hand-assigned lifetimes and simulation-only TOPS numbers, with the carbon model itself cited from the authors' related work.

free parameters (4)

Deployment lifetime N_life = 5 yr (conv. ASICs), 7 yr (Transformer-capable), 0.2 yr (CHORD w/o Reconfig), 5 yr (CHORD w/ Reconfig)
Chosen per device in Table II; divides embodied carbon in Eq. 5 and dominates CFP_task.
Grid carbon intensity CI_use = not stated
Required by Eq. 4 and 5 but never given; presumably inherited from ECO-CHIP.
EPIC TOPS values = e.g., CHORD 20,976.64 TOPS; SCATTER 40.96 TOPS
Imported from the authors' simulation papers; not measured hardware.
PIC power for CHORD = 0 W
Diffractive optics assumed to consume zero electrical power in Table II.

assumptions (4)

domain assumption ECO-CHIP carbon accounting model (Eqs 1-4) is valid for EPICs
Adopted in Sec. IV-A from citation [3] without re-derivation.
domain assumption Published performance numbers for prior designs are accurate
TOPS, TOPS/W, area and power figures are taken from the authors' prior papers in Table II.
ad hoc to paper Fixed-function diffractive systems become obsolete in 0.2 years
Assigned in Table II; no evidence cited, and it directly yields the reconfigurability benefit.
domain assumption TOPS is a fair cross-architecture performance metric
Used throughout Sec. IV-C and Fig. 8 without workload-specific SLA details.

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Cite this review

Pith. "Pith review of Toward Lifelong-Sustainable Electronic-Photonic AI Systems via Extreme Efficiency, Reconfigurability, and Robustness." pith.science (2026). https://pith.science/paper/AVCD74CW

@misc{pith2026250907396,
  author       = {Pith},
  title        = {Pith review of: Toward Lifelong-Sustainable Electronic-Photonic AI Systems via Extreme Efficiency, Reconfigurability, and Robustness},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/AVCD74CW}},
  note         = {Machine review of arXiv:2509.07396}
}

read the original abstract

The relentless growth of large-scale artificial intelligence (AI) has created unprecedented demand for computational power, straining the energy, bandwidth, and scaling limits of conventional electronic platforms. Electronic-photonic integrated circuits (EPICs) have emerged as a compelling platform for next-generation AI systems, offering inherent advantages in ultra-high bandwidth, low latency, and energy efficiency for computing and interconnection. Beyond performance, EPICs also hold unique promises for sustainability. Fabricated in relaxed process nodes with fewer metal layers and lower defect densities, photonic devices naturally reduce embodied carbon footprint (CFP) compared to advanced digital electronic integrated circuits, while delivering orders-of-magnitude higher computing performance and interconnect bandwidth. To further advance the sustainability of photonic AI systems, we explore how electronic-photonic design automation (EPDA) and cross-layer co-design methodologies can amplify these inherent benefits. We present how advanced EPDA tools enable more compact layout generation, reducing both chip area and metal layer usage. We will also demonstrate how cross-layer device-circuit-architecture co-design unlocks new sustainability gains for photonic hardware: ultra-compact photonic circuit designs that minimize chip area cost, reconfigurable hardware topology that adapts to evolving AI workloads, and intelligent resilience mechanisms that prolong lifetime by tolerating variations and faults. By uniting intrinsic photonic efficiency with EPDA- and co-design-driven gains in area efficiency, reconfigurability, and robustness, we outline a vision for lifelong-sustainable electronic-photonic AI systems. This perspective highlights how EPIC AI systems can simultaneously meet the performance demands of modern AI and the urgent imperative for sustainable computing.

Figures

Figures reproduced from arXiv: 2509.07396 by the authors.

**Figure 3.** Efficiency and density Pareto front comparison of differ [PITH_FULL_IMAGE:figures/full_fig_p003_3.png] view at source ↗

**Figure 4.** LighteningTransformer [20] with dynamic tensor cores for versatile AI inference acceleration. hardware achieves a better Pareto frontier in energy efficiency and compute density compared to SoTA electronic accelerators. B. Toward Sustainable EPIC via Extreme Versatility and Reconfigurability Beyond area/energy efficiency, long-term sustainability also depends on reconfigurability and versatility. AI workloads evolv… view at source ↗

Figures from the paper (3 more)

**Figure 6.** Figure 6: Customized PTC design SCATTER [19] with thermalaware, area-efficient circuit design and dynamic signal redistribution/gating enables compact layout without crosstalk issue. hardware substrate itself, enabling fabricated substrates to be repurposed across entirely dif…

**Figure 7.** Figure 7: Compared to VLSI placer DREAMPlace [39], Apollo [40] places the same photonic circuits in a ∼40% smaller die with even larger whitespace left for packaging usage, further improving the PIC sustainability. Apollo is a GPU-accelerated, waveguide-routing-informed analytic…

**Figure 8.** Figure 8: Carbon-performance tradeoff across devices. The y [PITH_FULL_IMAGE:figures/full_fig_p007_8.png]

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Works this paper leans on

44 extracted references · 42 canonical work pages

[1]

Tackling AI’s Climate Change Problem,

N. Sundberg, “Tackling AI’s Climate Change Problem,” 2023, https://sloanreview.mit.edu/article/tackling-ais-climate-change-problem/ (last accessed: Sep 2024)

work page 2023
[2]

The real climate and transformative impact of ICT: A critique of estimates, trends, and regulations,

C. Freitag, M. Berners-Leeet al., “The real climate and transformative impact of ICT: A critique of estimates, trends, and regulations,”Patterns, vol. 2, no. 9, p. 100340, 2021

work page 2021
[3]

ECO-CHIP: Estimation of Carbon Footprint of Chiplet-based Architectures for Sustainable VLSI,

C.C. Sudarshan, N. Matkaret al., “ECO-CHIP: Estimation of Carbon Footprint of Chiplet-based Architectures for Sustainable VLSI,” inPro- ceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2024

work page 2024
[4]

DTCO including sustainability: Power-performance-area-cost-environmental score (PPACE) analysis for logic technologies,

M. Garcia Bardon, P. Wuytenset al., “DTCO including sustainability: Power-performance-area-cost-environmental score (PPACE) analysis for logic technologies,” inProceedings of the IEEE International Electron Devices Meeting, 2020, pp. 41.4.1–41.4.4

work page 2020
[5]

ACT: Designing sustainable computer systems with an architectural carbon modeling tool,

U. Gupta, M. Elgamalet al., “ACT: Designing sustainable computer systems with an architectural carbon modeling tool,” inProceedings of the ACM International Symposium on Computer Architecture, 2022, p. 784–799

work page 2022
[6]

Deep learning with coherent nanophotonic circuits,

Y . Shen, N.C. Harriset al., “Deep learning with coherent nanophotonic circuits,”Nature Photonics, 2017

work page 2017
[7]

Inference in artificial intelligence with deep optics and photonics,

G. Wetzstein, A. Ozcanet al., “Inference in artificial intelligence with deep optics and photonics,”Nature, 2020

work page 2020
[8]

Photonics for Artificial Intelligence and Neuromorphic Computing,

B.J. Shastri, A.N. Taitet al., “Photonics for Artificial Intelligence and Neuromorphic Computing,”Nature Photonics, 2021

work page 2021

Show all 44 references

[9]

11 TOPS photonic convolutional accelerator for optical neural networks,

X. Xu, M. Tanet al., “11 TOPS photonic convolutional accelerator for optical neural networks,”Nature, 2021

2021
[10]

Parallel convolutional processing using an integrated photonic tensor core,

J. Feldmann, N. Youngbloodet al., “Parallel convolutional processing using an integrated photonic tensor core,”Nature, 2021

2021
[11]

Hardware-efficient photonic tensor core: acceler- ating deep neural networks with structured compression,

S. Ning, H. Zhuet al., “Hardware-efficient photonic tensor core: acceler- ating deep neural networks with structured compression,”Optica, vol. 12, no. 7, pp. 1079–1089, 2025

2025
[12]

Photonic-electronic integrated circuits for high-performance computing and ai accelerators,

S. Ning, H. Zhuet al., “Photonic-electronic integrated circuits for high-performance computing and ai accelerators,”Journal of Lightwave Technology, vol. 42, no. 22, pp. 7834–7859, 2024

2024
[13]

Analog optical computer for ai inference and combinatorial optimization,

K.P. Kalinin, J. Gladrowet al., “Analog optical computer for ai inference and combinatorial optimization,”Nature, Sep. 2025, open access

2025
[14]

An integrated large-scale photonic accelerator with ultralow latency,

S. Hua, E. Divitaet al., “An integrated large-scale photonic accelerator with ultralow latency,”Nature, vol. 640, pp. 361–367, Apr. 2025

2025
[15]

Universal photonic artificial intelligence acceleration,

S.R. Ahmed, R. Baghdadiet al., “Universal photonic artificial intelligence acceleration,”Nature, vol. 640, pp. 368–374, Apr. 2025

2025
[16]

TPU v4: An Optically Reconfigurable Supercomputer for Machine Learning with Hardware Support for Em- beddings,

N.P. Jouppi, G. Kurianet al., “TPU v4: An Optically Reconfigurable Supercomputer for Machine Learning with Hardware Support for Em- beddings,”arXiv preprint arXiv:2304.01433, 2023, tPUv4

2023 arXiv
[17]

Chapter 18 - optical interconnection networks for high-performance systems,

Q. Cheng, M. Glicket al., “Chapter 18 - optical interconnection networks for high-performance systems,” inOptical Fiber Telecommunications VII, A.E. Willner, Ed. Academic Press, 2020, pp. 785–825

2020
[18]

Photonics for sustainable computing,

F. Fayza, S.P. Raoet al., “Photonics for sustainable computing,”arXiv preprint arXiv:2401.05121, 2024

2024 arXiv
[19]

SCATTER: Algorithm-Circuit Co-Sparse Pho- tonic Accelerator with Thermal-Tolerant, Power-Efficient In-situ Light Redistribution,

Z. Yin, N. Gangiet al., “SCATTER: Algorithm-Circuit Co-Sparse Pho- tonic Accelerator with Thermal-Tolerant, Power-Efficient In-situ Light Redistribution,” inProc. ICCAD, 2024

2024
[20]

Lightening-transformer: A dynamically-operated photonic tensor core for energy-efficient transformer accelerator,

H. Zhu, J. Guet al., “Lightening-transformer: A dynamically-operated photonic tensor core for energy-efficient transformer accelerator,” in Proc. HPCA, 2024

2024
[21]

TeMPO: Efficient Time-Multiplexed Dy- namic Photonic Tensor Core for Edge AI with Compact Slow-Light Electro-Optic Modulator,

M. Zhang ∗, D. Yin ∗ et al., “TeMPO: Efficient Time-Multiplexed Dy- namic Photonic Tensor Core for Edge AI with Compact Slow-Light Electro-Optic Modulator,”Journal of Applied Physics (JAP), Jun. 2024

2024
[22]

CHORD: Composable Hybrid Optical Re- configurable Diffractive Framework For Optical Neural Network,

Z. Yin, Y . Yaoet al., “CHORD: Composable Hybrid Optical Re- configurable Diffractive Framework For Optical Neural Network,” in Proc. DAC. San Francisco, CA, USA: ACM/IEEE, Jun. 2025, pp. 1–6

2025
[23]

Fourier-space diffractive deep neural network,

T. Yan, J. Wuet al., “Fourier-space diffractive deep neural network,” Phys. Rev. Lett., vol. 123, p. 023901, Jul 2019

2019
[24]

Spatially varying nanophotonic neural networks,

K. Wei, X. Liet al., “Spatially varying nanophotonic neural networks,” Sci. Adv., 2023

2023
[25]

Dynamically reconfigurable all-optical neural network based on a hybrid graphene metasurface array,

J. Peng, L. Fanget al., “Dynamically reconfigurable all-optical neural network based on a hybrid graphene metasurface array,”Opt. Continuum, vol. 3, no. 5, pp. 704–713, May 2024

2024
[26]

Diffractive deep neural networks at visible wavelengths,

H. Chen, J. Fenget al., “Diffractive deep neural networks at visible wavelengths,”Engineering, vol. 7, no. 10, pp. 1483–1491, 2021

2021
[27]

All-optical machine learning using diffractive deep neural networks,

X. Lin, Y . Rivensonet al., “All-optical machine learning using diffractive deep neural networks,”Science, vol. 361, no. 6406, pp. 1004–1008, 2018

2018
[28]

Optical transformers,

M.G. Anderson, S.Y . Maet al., “Optical transformers,” 2023. [Online]. Available: https://arxiv.org/abs/2302.10360

2023 arXiv
[29]

Eyeriss: An energy-efficient reconfigurable accelerator for deep convolutional neural networks,

Y . Chen, T. Krishnaet al., “Eyeriss: An energy-efficient reconfigurable accelerator for deep convolutional neural networks,”IEEE Journal of Solid-State Circuits, vol. 52, no. 1, pp. 127–138, 2017

2017
[30]

Eyeriss v2: A flexible accelerator for emerging deep neural networks on mobile devices,

Y . Chen, J.S. Emeret al., “Eyeriss v2: A flexible accelerator for emerging deep neural networks on mobile devices,”IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), 2019

2019
[31]

A 28nm physics computing unit supporting emerging physics-informed neural network and finite element method for real-time scientific computing on edge devices,

Y .H. Ju, G. Xuet al., “A 28nm physics computing unit supporting emerging physics-informed neural network and finite element method for real-time scientific computing on edge devices,” inISSCC Digest of Technical Papers, 2024, pp. 366–368

2024
[32]

Trancim: Full-digital bitline-transpose cim- based sparse transformer accelerator with pipeline/parallel reconfigurable modes,

F. Tu, Z. Wuet al., “Trancim: Full-digital bitline-transpose cim- based sparse transformer accelerator with pipeline/parallel reconfigurable modes,”IEEE Journal of Solid-State Circuits, vol. 58, no. 6, pp. 1798– 1809, 2023

2023
[33]

Nvidia h100 tensor core gpu ar- chitecture,

NVIDIA Corporation, “Nvidia h100 tensor core gpu ar- chitecture,” NVIDIA, Tech. Rep., 2022. [Online]. Avail- able: https://www.advancedclustering.com/wp-content/uploads/2022/03/ gtc22-whitepaper-hopper.pdf

2022
[34]

Nvidia h100 pcie gpu — product brief,

NVIDIA Corporation, “Nvidia h100 pcie gpu — product brief,” 2022, power modes and board specs for PCIe variant. [Online]. Available: https://www.nvidia.com/content/dam/en-zz/Solutions/gtcs22/ data-center/h100/PB-11133-001_v01.pdf

2022
[35]

CHORD: Composable Hybrid Optical Re- configurable Diffractive Framework For Optical Neural Network,

Z. Yin, Y . Yaoet al., “CHORD: Composable Hybrid Optical Re- configurable Diffractive Framework For Optical Neural Network,” in Proc. DAC, Jun. 2025

2025
[36]

L2ight: Enabling On-Chip Learning for Opti- cal Neural Networks via Efficient in-situ Subspace Optimization,

J. Gu, H. Zhuet al., “L2ight: Enabling On-Chip Learning for Opti- cal Neural Networks via Efficient in-situ Subspace Optimization,” in Proc. NeurIPS, 2021

2021
[37]

Doctor: Dynamic on-chip temporal variation remediation toward self-corrected photonic tensor accelerators,

H. Lu, S. Banerjeeet al., “Doctor: Dynamic on-chip temporal variation remediation toward self-corrected photonic tensor accelerators,”IEEE Journal of Lightwave Technology, 2024

2024
[38]

ELight: Towards Efficient and Aging-Resilient Photonic In-Memory Neurocomputing,

H. Zhu, J. Guet al., “ELight: Towards Efficient and Aging-Resilient Photonic In-Memory Neurocomputing,”IEEE TCAD, 2022

2022
[39]

DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement,

Y . Lin, S. Dharet al., “DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement,”IEEE TCAD, 2020

2020
[40]

Apollo: Automated routing-informed placement for large-scale photonic integrated circuits,

H. Zhou, H. Yanget al., “Apollo: Automated routing-informed placement for large-scale photonic integrated circuits,” inProc. ICCAD, 2025

2025
[41]

LiDAR: Automated Curvy Waveguide Detailed Routing for Large-Scale Photonic Integrated Circuits,

H. Zhou, K. Zhuet al., “LiDAR: Automated Curvy Waveguide Detailed Routing for Large-Scale Photonic Integrated Circuits,” inProceedings of the 2025 International Symposium on Physical Design, 2025, pp. 64–72

2025
[42]

LiDAR 2.0: Hierarchical Curvy Waveguide Detailed Routing for Large-Scale Photonic Integrated Circuits,

H. Zhou, H. Yanget al., “LiDAR 2.0: Hierarchical Curvy Waveguide Detailed Routing for Large-Scale Photonic Integrated Circuits,”arXiv preprint arXiv:2505.17239, 2025

2025
[43]

Beyond the surface: The necessity for detailed metrics in corporate sustainability reports,

C.C. Sudarshan, A. Aroraet al., “Beyond the surface: The necessity for detailed metrics in corporate sustainability reports,” in2024 IEEE 15th International Green and Sustainable Computing Conference (IGSC), 2024, pp. 145–150

2024
[44]

Adept: Automatic differentiable design of photonic tensor cores,

J. Gu, H. Zhuet al., “Adept: Automatic differentiable design of photonic tensor cores,” inProc. DAC, 2022

2022

Pith tools

Reviewed August 4, 2026 · model on record in the stance chip above.

[1] [1]

Tackling AI’s Climate Change Problem,

N. Sundberg, “Tackling AI’s Climate Change Problem,” 2023, https://sloanreview.mit.edu/article/tackling-ais-climate-change-problem/ (last accessed: Sep 2024)

work page 2023

[2] [2]

The real climate and transformative impact of ICT: A critique of estimates, trends, and regulations,

C. Freitag, M. Berners-Leeet al., “The real climate and transformative impact of ICT: A critique of estimates, trends, and regulations,”Patterns, vol. 2, no. 9, p. 100340, 2021

work page 2021

[3] [3]

ECO-CHIP: Estimation of Carbon Footprint of Chiplet-based Architectures for Sustainable VLSI,

C.C. Sudarshan, N. Matkaret al., “ECO-CHIP: Estimation of Carbon Footprint of Chiplet-based Architectures for Sustainable VLSI,” inPro- ceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2024

work page 2024

[4] [4]

DTCO including sustainability: Power-performance-area-cost-environmental score (PPACE) analysis for logic technologies,

M. Garcia Bardon, P. Wuytenset al., “DTCO including sustainability: Power-performance-area-cost-environmental score (PPACE) analysis for logic technologies,” inProceedings of the IEEE International Electron Devices Meeting, 2020, pp. 41.4.1–41.4.4

work page 2020

[5] [5]

ACT: Designing sustainable computer systems with an architectural carbon modeling tool,

U. Gupta, M. Elgamalet al., “ACT: Designing sustainable computer systems with an architectural carbon modeling tool,” inProceedings of the ACM International Symposium on Computer Architecture, 2022, p. 784–799

work page 2022

[6] [6]

Deep learning with coherent nanophotonic circuits,

Y . Shen, N.C. Harriset al., “Deep learning with coherent nanophotonic circuits,”Nature Photonics, 2017

work page 2017

[7] [7]

Inference in artificial intelligence with deep optics and photonics,

G. Wetzstein, A. Ozcanet al., “Inference in artificial intelligence with deep optics and photonics,”Nature, 2020

work page 2020

[8] [8]

Photonics for Artificial Intelligence and Neuromorphic Computing,

B.J. Shastri, A.N. Taitet al., “Photonics for Artificial Intelligence and Neuromorphic Computing,”Nature Photonics, 2021

work page 2021