Identification and mitigation of memory block timing issue in ITk ABCStar during ASIC production
Pith reviewed 2026-05-22 01:44 UTC · model grok-4.3
The pith
Raising the ABCStar core voltage from 1.20 V to 1.25 V fixes a timing issue in reused memory blocks and achieves over 80% yields even on the worst wafers.
A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.
Core claim
The root cause of low wafer yields was a timing issue in the logic synthesized to control previously silicon-proven memory blocks re-used in the ABCStar. Raising the core operating voltage from 1.20V to 1.25V sufficiently speeds up the transistors to resolve the timing issue. Extensive testing including the effects of temperature and radiation over the lifetime of the ITk detector validated that even the worst performing wafers would have yields over 80% with the 1.25V core voltage, and neither the modified process nor redesign would be required.
What carries the argument
The timing violation in the synthesized control logic for re-used memory blocks; raising the operating voltage provides the speed margin needed to meet timing requirements.
If this is right
- Production can proceed with existing wafers at the higher voltage without scrapping them.
- Yields remain high even under the full range of expected operating temperatures and radiation doses.
- An increase in the clock duty cycle provides additional timing reliability margin.
- The ITk detector module production using ABCStar ASICs is now underway.
Where Pith is reading between the lines
- Voltage tuning after fabrication may serve as a general strategy for fixing subtle timing problems in radiation-hard ASICs that reuse memory IP.
- This experience suggests that design verification for future detector electronics should include more aggressive timing corner analysis at nominal voltages.
- Similar issues could arise in other LHC upgrade ASICs, making early identification of reused block timing sensitivities important.
Load-bearing premise
That a small 0.05 V increase in core voltage will give the transistors enough extra speed to fix the specific timing violation in the memory control logic without causing other problems like higher power consumption or shorter lifetime in the full range of detector conditions.
What would settle it
A test showing that even at 1.25 V the worst wafers still have yields under 80% or fail under combined high temperature and radiation exposure would show the voltage increase does not fully solve the timing issue.
read the original abstract
The ABCStar is a mixed-signal front-end readout ASIC for the strips sensor portion of the ATLAS ITk detector being developed as part of the High-Luminosity LHC upgrade. In pre-production testing, a subtle design flaw was uncovered in the ABCStar that was reducing wafer yields in some manufactured lots from the expected 90% to as low as 2%. The root cause was determined to be a timing issue in the logic synthesized to control previously silicon proven memory blocks re-used for this ASIC. The solutions proposed included manufacturing process changes by the wafer foundry, changes to the operating parameters for the ABCStar in the detector, and the possibility that a redesign might be required. The two mitigation efforts were undertaken in parallel, with the process modification route a less desirable solution since already manufactured wafers would need to be scrapped in favour of the new ones. Based on a knowledge of the existing process, and testing done on the worst performing wafers, it was proposed that raising the core operating voltage of the ABCStar from 1.20V to 1.25V could address the timing issue by sufficiently speeding up its transistors. An extensive testing program that included the effects of temperature and radiation expected over the lifetime of the ITk detector was conducted to validate that approach. Those tests and studies proved that even the worst performing wafers would have yields over 80% with the 1.25V core voltage, and neither the modified process nor redesign would be required for ensuring reliable operation of the ITk. Based on testing, a further timing mitigation was implemented to provide an additional margin of reliability by increasing the duty cycle of the clock to the ABCStar. Testing of all ABCStar wafers has been completed and the production of the detector modules using these ASICs is now well underway as a result of the efforts detailed herein.
Editorial analysis
A structured set of objections, weighed in public.
Referee Report
Summary. The manuscript reports the discovery of a timing violation in the synthesized control logic for re-used memory blocks in the ABCStar ASIC for the ATLAS ITk strips detector. This issue reduced wafer yields from expected ~90% to as low as 2% in some lots. The authors identify the root cause through testing, propose raising the core voltage from 1.20 V to 1.25 V to increase transistor speed, and validate this via an extensive program covering temperature and radiation conditions expected over the ITk lifetime. They report that this yields >80% even for worst-case wafers, supplemented by a clock duty-cycle adjustment, enabling full wafer testing and module production without foundry process changes or redesign.
Significance. If the empirical results hold, this has clear significance for the timely completion of the ITk detector, as it salvages existing wafers and avoids delays or costs from redesign or scrapping. The work merits credit for the systematic root-cause analysis tied to the memory-control logic and for the practical validation under relevant environmental stresses, which directly informs reliable long-term operation in a high-radiation environment.
major comments (1)
- Testing and Validation section: The central claim that the 1.25 V core voltage produces yields over 80% for worst-performing wafers under temperature and radiation rests on the described testing program; however, the manuscript provides no tabulated yield data, error bars, sample sizes, or detailed test protocols, which undermines independent verification of the quantitative improvement and the conclusion that redesign is unnecessary.
minor comments (1)
- Abstract and Introduction: The description of the timing issue in the re-used memory blocks is clear, but a brief reference to the specific memory block type or prior silicon-proven usage would aid readers unfamiliar with the ABCStar design history.
Simulated Author's Rebuttal
We thank the referee for the constructive review and the recommendation of minor revision. The single major comment is addressed point-by-point below.
read point-by-point responses
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Referee: Testing and Validation section: The central claim that the 1.25 V core voltage produces yields over 80% for worst-performing wafers under temperature and radiation rests on the described testing program; however, the manuscript provides no tabulated yield data, error bars, sample sizes, or detailed test protocols, which undermines independent verification of the quantitative improvement and the conclusion that redesign is unnecessary.
Authors: We agree that the absence of tabulated yield data, error bars, sample sizes, and explicit test-protocol details limits independent verification. The original manuscript summarized the outcomes of the extensive testing campaign on worst-case wafers, but did not present the underlying quantitative results. In the revised version we will expand the Testing and Validation section with a new table that reports wafer-level yields at 1.20 V versus 1.25 V, including the number of wafers and dies tested, observed yield ranges, and a concise description of the temperature and radiation test protocols. These additions will directly support the claim that yields exceed 80 % under the relevant conditions and that redesign is unnecessary. revision: yes
Circularity Check
No significant circularity; empirical validation only
full rationale
The manuscript is an engineering report on ASIC production yield recovery. It identifies a timing violation in synthesized memory-control logic through testing, then validates a 0.05 V core-voltage increase plus clock-duty-cycle adjustment via direct measurements on worst-case wafers under temperature and radiation. No equations, fitted parameters, predictions, or derivation chains appear. The central claim rests on experimental outcomes and prior process knowledge rather than any self-referential reduction or self-citation load-bearing step. The argument is therefore self-contained against external benchmarks.
Axiom & Free-Parameter Ledger
axioms (1)
- domain assumption The timing issue originates in the logic synthesized to control the previously proven memory blocks.
Reference graph
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discussion (0)
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