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Culsans: An Efficient Snoop-based Coherency Unit for the CVA6 Open Source RISC-V application processor
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Symmetric Multi-Processing (SMP) based on cache coherency is crucial for high-end embedded systems like automotive applications. RISC-V is gaining traction, and open-source hardware (OSH) platforms offer solutions to issues such as IP costs and vendor dependency. Existing multi-core cache-coherent RISC-V platforms are complex and not efficient for small embedded core clusters. We propose an open-source SystemVerilog implementation of a lightweight snoop-based cache-coherent cluster of Linux-capable CVA6 cores. Our design uses the MOESI protocol via the Arm's AMBA ACE protocol. Evaluated with Splash-3 benchmarks, our solution shows up to 32.87% faster performance in a dual-core setup and an average improvement of 15.8% over OpenPiton. Synthesized using GF 22nm FDSOI technology, the Cache Coherency Unit occupies only 1.6% of the system area.
Forward citations
Cited by 2 Pith papers
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A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs
A centralized EVU-APMU hardware architecture collects and processes performance counter data on a dedicated side processor, demonstrated on a RISC-V SoC for memory regulation and function-level profiling.
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The Open-Source BlackParrot-BedRock Cache Coherence System
A race-free cache coherence protocol called BedRock and three coherence directory implementations in the BlackParrot multicore show that programmable and hybrid coherence engines can match fixed-function performance w...
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