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arxiv: 1906.09395 · v1 · pith:BHTZBS5Wnew · submitted 2019-06-22 · 📡 eess.SP · cs.AR· eess.IV

Adaptive Precision CNN Accelerator Using Radix-X Parallel Connected Memristor Crossbars

Jaeheum Lee , Jason K. Eshraghian , Kyoungrok Cho , Kamran Eshraghian This is my paper

Pith reviewed 2026-05-25 18:31 UTC · model grok-4.3

classification 📡 eess.SP cs.AReess.IV
keywords memristor crossbarCNN acceleratoradaptive precisionradix-Xweight mappingnegative weightsCIFAR-10area reduction
0
0 comments X

The pith

Radix-X memristor crossbars represent negative weights in single columns and vary memristor counts per crosspoint to cut CNN accelerator area while raising accuracy.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper develops an adaptive precision method for memristor crossbar arrays in CNN accelerators by varying the number of memristors at each crosspoint. It introduces a weight mapping algorithm that represents negative weights using a single column line instead of duplicating columns. Through simulation and experimental results, the radix-5 version achieves 90.5 percent accuracy on CIFAR-10, improving 4.5 percent over binarized neural networks, and reduces crossbar area by 46 percent. This matters because it tackles area and power issues in edge devices that rely on in-memory matrix multiplications for deep learning.

Core claim

The radix-X Convolutional Neural Network Crossbar Array efficiently represents negative weights using a single column line rather than doubling the number of additional columns, while varying the number of memristors at each crosspoint for adaptive precision, leading to a validation accuracy of 90.5% on the CIFAR-10 dataset with 46% less area than conventional arrays.

What carries the argument

The radix-X CNN crossbar array with a weight mapping algorithm that supports signed weights in single columns and adaptive precision via multiple memristors per crosspoint.

If this is right

  • Negative weights no longer require duplicate column wires, reducing area.
  • Adaptive precision improves accuracy over fixed low-precision methods like binarized networks.
  • The approach maintains efficiency in parallel matrix-vector multiplications for CNN layers.
  • Experimental verification shows the area savings and accuracy gains on standard datasets.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • If scaled to larger networks, this could lower the hardware footprint for real-time image classification on edge devices.
  • Similar mapping techniques might apply to other neural network types beyond CNNs.
  • Combining this with existing in-memory computing optimizations could further cut power consumption in AI hardware.

Load-bearing premise

Varying the number of memristors per crosspoint and the weight mapping algorithm can be implemented in physical hardware without introducing resistive losses or fabrication variability that degrade accuracy beyond simulation results.

What would settle it

Measuring the inference accuracy of a fabricated radix-5 memristor crossbar array on the CIFAR-10 dataset and comparing it to the reported 90.5% simulation accuracy.

Figures

Figures reproduced from arXiv: 1906.09395 by Jaeheum Lee, Jason K. Eshraghian, Kamran Eshraghian, Kyoungrok Cho.

Figure 1
Figure 1. Figure 1: Memristor characterization (a) physical representation depicting TiO [PITH_FULL_IMAGE:figures/full_fig_p003_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: Generalized CNN model with parameters labeled including number [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 6
Figure 6. Figure 6: The process of training radix-X CNN models. The gradients of the cost [PITH_FULL_IMAGE:figures/full_fig_p005_6.png] view at source ↗
Figure 7
Figure 7. Figure 7: Parallel-connected crosspoint for X=5. Each intersection of the cross [PITH_FULL_IMAGE:figures/full_fig_p005_7.png] view at source ↗
Figure 5
Figure 5. Figure 5: Conversion plot of (a) weights and (b) activations. [PITH_FULL_IMAGE:figures/full_fig_p005_5.png] view at source ↗
Figure 8
Figure 8. Figure 8: Parallel-connected memristor crosspoint structure (a) Symbolic [PITH_FULL_IMAGE:figures/full_fig_p006_8.png] view at source ↗
Figure 10
Figure 10. Figure 10: A simple example showing the issues that occur when linearly [PITH_FULL_IMAGE:figures/full_fig_p007_10.png] view at source ↗
Figure 11
Figure 11. Figure 11: The structure of the proposed circuit is able to represent negative [PITH_FULL_IMAGE:figures/full_fig_p008_11.png] view at source ↗
Figure 10
Figure 10. Figure 10: The relationship between a neural network input Xn and the input voltage Vn in the circuit is given as, Vn = Xn S , (18) where S is the scaling factor of Vn. Substituting (18) and (1)into (17) obtains: Vcol = R ∗ Xn i=0 wr−5,i ∗ Xi Rm ∗ S  =  R Rm ∗ S  ∗ Y ∵ (1), (17). (19) This verifies that the output voltage of our radix-X CNN accelerator is simply scaled by ( Rm∗S R ), and concludes that we [PITH… view at source ↗
Figure 14
Figure 14. Figure 14: (a) Simulation of the proposed architecture where [PITH_FULL_IMAGE:figures/full_fig_p009_14.png] view at source ↗
Figure 15
Figure 15. Figure 15: Al/TiO2/TiOx/Al memristor device imaged using a focus ion beam (FIB) analyzer [PITH_FULL_IMAGE:figures/full_fig_p009_15.png] view at source ↗
Figure 16
Figure 16. Figure 16: 2D convolution performed on 100 28 × 28 images from the MNIST dataset with a Sobel filter in radix-5 on the crossbar array in [PITH_FULL_IMAGE:figures/full_fig_p010_16.png] view at source ↗
Figure 17
Figure 17. Figure 17: A scaled-up inspection of hardware-based 2D convolution. (a) Before [PITH_FULL_IMAGE:figures/full_fig_p010_17.png] view at source ↗
read the original abstract

Neural processor development is reducing our reliance on remote server access to process deep learning operations in an increasingly edge-driven world. By employing in-memory processing, parallelization techniques, and algorithm-hardware co-design, memristor crossbar arrays are known to efficiently compute large scale matrix-vector multiplications. However, state-of-the-art implementations of negative weights require duplicative column wires, and high precision weights using single-bit memristors further distributes computations. These constraints dramatically increase chip area and resistive losses, which lead to increased power consumption and reduced accuracy. In this paper, we develop an adaptive precision method by varying the number of memristors at each crosspoint. We also present a weight mapping algorithm designed for implementation on our crossbar array. This novel algorithm-hardware solution is described as the radix-X Convolutional Neural Network Crossbar Array, and demonstrate how to efficiently represent negative weights using a single column line, rather than double the number of additional columns. Using both simulation and experimental results, we verify that our radix-5 CNN array achieves a validation accuracy of 90.5% on the CIFAR-10 dataset, a 4.5% improvement over binarized neural networks whilst simultaneously reducing crossbar area by 46% over conventional arrays by removing the need for duplicate columns to represent signed weights.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 1 minor

Summary. The paper presents an adaptive precision method for memristor crossbar arrays in CNN accelerators by varying the number of memristors at each crosspoint and a radix-X weight mapping algorithm that allows negative weights to be represented in a single column rather than requiring duplicate columns. Using simulation and experimental results, it claims a radix-5 CNN array achieves 90.5% validation accuracy on CIFAR-10 (4.5% better than binarized NNs) while reducing crossbar area by 46%.

Significance. If the hardware realization of the variable memristor counts and single-column signed weight mapping proves feasible without significant resistive losses or variability, this work could advance efficient in-memory computing for edge AI by addressing key limitations in area and precision in memristor-based accelerators. The combination of simulation and experimental results is a positive aspect.

major comments (2)
  1. [Abstract] Abstract: The abstract states that both simulation and experimental results support the 90.5% accuracy and 46% area claim, yet provides no error bars, baseline implementation details, data exclusion criteria, or quantitative comparison tables; this leaves the central performance numbers with limited verifiability.
  2. [Abstract] Abstract: The radix-X mapping for single-column negative weights and adaptive precision via multiple memristors per crosspoint are central to the area reduction and accuracy claims, but the manuscript does not demonstrate that these can be implemented in physical hardware without unaccounted resistive losses, fabrication variability, or accuracy degradation.
minor comments (1)
  1. The abstract could benefit from a brief mention of the specific datasets or network architectures used beyond CIFAR-10.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the detailed review and constructive comments. We address each major comment point-by-point below, clarifying the manuscript content and indicating where revisions will be made.

read point-by-point responses

  1. Referee: [Abstract] Abstract: The abstract states that both simulation and experimental results support the 90.5% accuracy and 46% area claim, yet provides no error bars, baseline implementation details, data exclusion criteria, or quantitative comparison tables; this leaves the central performance numbers with limited verifiability.

    Authors: We agree that the abstract's brevity limits inclusion of error bars, detailed baselines, or tables. The full manuscript provides these in Sections 4 (simulation setup with CIFAR-10 baselines against binarized NNs) and 5 (experimental results including variability measurements). No data exclusion criteria apply as all simulation runs and fabricated device measurements are reported. We will revise the abstract to reference the key baselines and direct readers to the quantitative tables in the main text. revision: partial

  2. Referee: [Abstract] Abstract: The radix-X mapping for single-column negative weights and adaptive precision via multiple memristors per crosspoint are central to the area reduction and accuracy claims, but the manuscript does not demonstrate that these can be implemented in physical hardware without unaccounted resistive losses, fabrication variability, or accuracy degradation.

    Authors: The manuscript's experimental section reports measurements from fabricated memristor crossbar prototypes implementing the radix-X mapping and variable memristor counts. These include direct characterization of resistive losses and device variability, with the observed accuracy of 90.5% on CIFAR-10 already incorporating those effects. The 46% area reduction is derived from the single-column signed-weight representation validated in hardware. While a full end-to-end chip with the exact radix-5 configuration at scale is beyond the current prototype scope, the presented hardware results directly address feasibility. revision: no

Circularity Check

0 steps flagged

No circularity in derivation chain

full rationale

The paper reports empirical results from simulations and limited experiments on the radix-X CNN accelerator, including 90.5% CIFAR-10 accuracy and 46% area reduction. No equations, derivations, or load-bearing steps are shown that reduce these outcomes to quantities defined by fitted parameters chosen within the same work, self-citations, or ansatzes smuggled via prior author work. The claims rest on measured/simulated outcomes rather than tautological predictions or self-referential mappings, making the derivation self-contained against external benchmarks.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 0 invented entities

Abstract-only review provides no explicit free parameters, axioms, or invented entities; the design implicitly assumes standard memristor device models and crossbar fabrication feasibility without detailing any fitted constants or new postulated components.

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Forward citations

Cited by 1 Pith paper

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score.

  1. Reconfigurable multiplier architecture based on memristor-cmos with higher flexibility

    cs.AR 2019-07 unverdicted novelty 4.0

    A memristor-CMOS reconfigurable multiplier is introduced to enable flexible bit-width operations with reduced area via SPICE simulations on 180-nm CMOS.

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