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Optimizing Superconducting Three-Qubit Gates for Surface-Code Error Correction

T0 review · 3 major / 6 minor · reviewed 2026-08-07 · deepseek-v4-flash

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Pith's one-line read The paper claims that a 35 ns CZZ gate, designed for superconducting transmons and optimized to suppress Pauli errors that break surface-code fault tolerance, raises the rotated surface-code error threshold to roughly 1.2% and reduces…

desk verdict Protocol-level claim holds up; the optimized-gate threshold numbers are plausible but rest on a noise channel that excludes decoherence and is rescaled far beyond the simulated point. read the letter →

arxiv 2506.09028 v1 pith:BTXDKNY7 submitted 2025-06-10 quant-ph

Stephan Tasler , Josias Old , Lukas Heunisch , Verena Feulner , Timo Eckstein , Markus Müller , Michael J. Hartmann This is my paper
classification quant-ph
keywords CZZgatesurfacecodestabilizerreadoutsuperconductingtransmonPaulierrormodeloptimalcontrolquantumcorrectionthreshold
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper sets out to show that surface-code stabilizer readout can be made faster and more error-resilient by replacing the usual sequence of two-qubit CZ gates with a single three-qubit CZZ gate that maps the parity of two data qubits onto a measurement qubit. The authors design this gate for superconducting transmon hardware, arriving at a 35 ns version with a simulated gate fidelity of 99.96%, and they optimize the flux control pulses not simply for maximal fidelity but for suppression of the specific Pauli errors that are most likely to defeat the surface code. Under their circuit-level noise model, the rotated surface code's physical error threshold rises from about 0.66% to about 1.2%, and logical error rates fall by up to an order of magnitude in the experimentally relevant error range; the unrotated surface code also sees a threshold gain while remaining strictly fault tolerant. If the gate and the assumed error channel hold up in hardware, this would be a concrete route to better quantum error correction without changing the chip architecture.

What carries the argument

The load-bearing object is the CZZ parity-mapping gate: the unitary is diagonal with a -1 phase on computational states where the two outer qubits have odd parity, which is realized by simultaneously activating equal ZZ couplings between the center (measurement) qubit and each outer (data) qubit. The implementation uses two frequency-tunable couplers between three fixed-frequency transmons, with flux pulses shaped as flattop Gaussians; the pulse parameters are the optimizable degrees of freedom. The optimization's second key ingredient is the cost function of Eq. (7), which combines a leakage penalty, a term balancing all Pauli coefficients, and a weighted sum of selected Pauli channels; the weights are set by the marginal harmfulness of each Pauli term computed from the graph of conspiring two-fault combinations. The Pauli channel itself is extracted from the simulated process matrix using the closest-channel projection and the Pauli twirling approximation, and then rescaled so that the identity coefficient determines the physical error rate p.

What would settle it

Measure the 35 ns CZZ gate's process matrix on the proposed transmon-coupler circuit over a range of physical error rates and compare the measured Pauli weights to the rescaled model; if the relative probabilities of fault-tolerance-breaking errors such as IYI and XYX grow faster than the model predicts, the threshold gain shown in the paper will not be reached.

Watch

Extended reading notes

Core claim

The central claim is that a CZZ gate — a controlled-Z operation on a measurement qubit whose control is the parity of two data qubits — can be implemented as two simultaneous ZZ interactions between the center qubit and two outer transmons, tuned by flux pulses on two tunable couplers in a fixed-frequency transmon circuit. The paper derives the circuit Hamiltonian by canonical quantization, simulates the full five-mode dynamics, extracts the closest Pauli error channel via the normalized Frobenius inner product, and applies a Pauli twirling approximation to obtain symmetric Pauli weights. The pulse optimization uses a three-term cost function that penalizes leakage, keeps the total Pauli error balanced, and suppresses selected Pauli errors with weights derived from an explicit graph of 'conspiring' two-fault combinations in a distance-5 rotated surface code. The result is a 35 ns gate with a simulated unitary error of 3.6e-4 (fidelity 99.96%) and an estimated decoherence error of about 7e-4, whose effective Pauli channel suppresses the odd X/Y-content errors that dominate the fault-tolerance-breaking marginals. When this channel is rescaled to a physical error rate p and used in Z- and X-memory experiments, the rotated surface-code threshold increases from roughly 0.66% (CZ protocol) to about 0.83% (CZZ with uniform depolarizing noise) and to about 1.17% with the optimized effective channel; for the unrotated code the optimized-channel threshold is about 1.08%. The same simulations show logical error rates reduced by up to an order of magnitude at higher code distances in the experimentally relevant regime, and the unrotated code retains a strictly fault-tolerant readout schedule.

Load-bearing premise

The performance claims depend on the simulated Pauli error channel keeping its shape when rescaled to much larger error rates, and on the omitted experimental error sources not changing which errors dominate.

Editorial extensions

If this is right

  • Stabilizer readout for both Z and X plaquettes can be compressed from four rounds of two-qubit gates to two rounds of CZZ gates per Pauli type, shortening each syndrome-measurement cycle.
  • The rotated surface-code threshold under circuit-level noise rises from about 0.66% with CZ readout to about 1.2% with the optimized CZZ effective channel, and the unrotated code reaches about 1.1%.
  • At physical error rates between 0.1% and 1%, logical error rates at higher code distances drop by up to an order of magnitude compared with CZ readout.
  • Fewer physical qubits are needed to reach a fixed logical error target; for example, at p=0.3% with no idling noise, reaching p_L=1e-6 requires 1057 qubits with CZZ versus 1457 with CZ.
  • The unrotated surface code can use CZZ readout without sacrificing strict fault tolerance, so multi-qubit gates are not inherently incompatible with distance-preserving circuits.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • If the channel-shape assumption is violated in hardware — for example, if leakage or correlated errors grow with pulse power — the threshold gain could shrink; measuring the process matrix at several error rates would reveal this directly.
  • The same weighted-cost recipe could be applied to two-qubit CZ readout or to other platforms with tunable multi-qubit interactions, replacing the surface-code harmfulness marginals with the appropriate decoder-relevant error weights.
  • The appendix's ordering results suggest that for the rotated code, a schedule that puts all CZZ gates orthogonal to one logical operator makes one memory basis fault tolerant, which may offer a cheap way to protect one logical axis before optimized channels are available.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 6 minor

Summary. This manuscript designs and optimizes a three-qubit CZZ parity-mapping gate for superconducting transmon circuits, intended to parallelize surface-code stabilizer readout. The authors quantize a five-node circuit (three fixed-frequency transmons and two tunable couplers, Eq. 3), optimize flux pulses with a cost function (Eq. 7) that penalizes leakage, total Pauli error, and Pauli terms identified as harmful by a decoder-based fault analysis (Sec. V.A, Eq. 8), and extract an effective Pauli channel via the Pauli twirling approximation (Sec. IV.A). They report a 35 ns gate with unitary error 3.646e-4 (F = 99.96%) and a separately estimated decoherence error 6.9975e-4 (Table I). Using stim and pymatching, they benchmark memory experiments for rotated and unrotated surface codes (Fig. 8), report thresholds of about 1.2% (rotated) and 1.1% (unrotated) with the effective Pauli channel versus about 0.66% for standard CZ readout (Fig. 10), claim up to an order-of-magnitude logical-error reduction in the experimentally relevant regime (Fig. 9), and a 27-37% reduction in required physical qubits (Fig. 11). For the unrotated code, strictly fault-tolerant readout schedules are asserted on the basis of the companion paper Ref. [40].

Significance. The paper is a complete, well-executed pipeline from microscopic circuit quantization to QEC threshold extraction, and the core proposal is concrete and falsifiable: specific circuit parameters (Tables II-III), a 35 ns gate, and a Pauli channel engineered to suppress the high-degree harmful terms identified in the fault graph (Fig. 7). The work uses standard public tools (QuTiP, stim, pymatching, pyfssa) and reports quantitative estimates with uncertainties. If the claims hold, the methodology of harmfulness-aware gate optimization is transferable beyond this platform and could inform noise-bias engineering for other gates. The authors deserve credit for explicitly disclosing in Sec. V.C that the QEC numbers are an upper bound because experimental errors are incomplete. The significance is, however, tempered by two issues: the benchmark channel omits the decoherence error that is the larger of the two reported error contributions at the operating point, and the headline claims as stated in the abstract are not accompanied by the caveats that appear in the body.

major comments (3)
  1. [Sec. IV.A, V.C; Figs. 8-11] The QEC benchmarks use an effective Pauli channel extracted from the closed-system unitary U_sim (Eq. 3), which excludes the paper's own decoherence estimate eps_dec ~ 7.0e-4 at 35 ns from Eq. (5) and Table I. At the simulated operating point (eps_gate + eps_dec ~ 1.06e-3), about two-thirds of the physical gate error is therefore absent from the channel that produces Figs. 8-11. In addition, Sec. IV.A rescales all Pauli coefficients so that 1 - w_III = p, and the headline threshold p ~ 1.17e-2 (Fig. 10a) is evaluated at a physical error rate roughly 11 times the simulated total error, under the assumption that the optimized channel shape (including the suppression of high-degree terms in Fig. 7) is invariant under the rescaling and under the addition of decoherence. The 'upper bound' caveat is stated once in Sec. V.C, but the abstract presents the ~1.2% threshold and the order-of-magnitude improvement as properties of the proposed implementation. I ask the authors to (i) include an operating-point QEC evaluation in which the gate channel incorporates the decoherence contribution (e.g., a T1/T2-dressed channel), and (ii) either test the robustness of the channel shape across the p-range of Figs. 8-10 or explicitly rephrase the abstract claims as conditional on the simulated unitary channel.
  2. [Abstract; Sec. IV and Table I] The headline fidelity F = 99.96% is 1 - eps_gate, excluding the decoherence error eps_dec of Eq. (5) that is listed in Table I; including both contributions gives a total error of about 1.06e-3, i.e., F ~ 99.89%. Because the 35 ns gate time was chosen so that eps_gate and eps_dec are of the same order, quoting only the unitary error in the abstract is misleading and should be qualified, e.g., by stating the fidelity before the separately estimated decoherence contribution. Relatedly, the claimed 'nearly 50%' threshold increase is in tension with the reported numbers: Fig. 10a gives 0.658% -> 1.167%, an increase of about 77%, while the decomposition in Appendix C.7 is +25% (uniform CZZ versus CZ) plus a further 30-40% (effective channel versus uniform). The abstract, the introduction (~1.1%), and Sec. V.C (~1.2%) also disagree on the rotated-code threshold value; these numbers should be harmonized.
  3. [Sec. V.A-V.C; Eqs. (7)-(8)] The harmfulness weights gamma_K in the cost function (Eq. 7) are derived from the authors' own decoder-based fault analysis (Eq. 8, Sec. V.A: distance-5 rotated code, 5 rounds, p = 0.001, uniform depolarizing channel), and the optimized gate is then evaluated with the same stim/pymatching decoder and the same single-parameter noise-model family (Figs. 8-10). The reported logical-error improvement could therefore partly reflect tuning to the specific failure modes of this decoder and schedule rather than an intrinsic property of the suppressed Pauli structure. This is not an internal inconsistency, but it is a correctness risk for the central claim. A concrete test would be to benchmark the optimized channel with a different decoder (e.g., BP-OSD or a tensor-network decoder) or to recompute the harmfulness weights at another distance or number of rounds and verify that the optimized channel remains beneficial; the authors' demonstration of improvement across d = 3...13 partially mitigates this concern.
minor comments (6)
  1. [Sec. V.B] The same weightings eta = [1, 10, 0.1] are stated for both the 35 ns and the 50 ns pulses; if this is intentional, please explain what distinguishes the two optimizations (e.g., a fixed-duration constraint), and otherwise correct the sentence.
  2. [Fig. 13] The y-axis is labeled 'frequency in GHz' with values from 0.25 to 2.00, but the idle coupler frequencies are 7.50 and 7.44 GHz (Appendix B) and the caption says the couplers are tuned close to the ancilla at 5.31 GHz; the plotted quantity appears to be the detuning from the ancilla frequency, and the axis should be relabeled accordingly.
  3. [Sec. IV.A] The statement that the asymmetric Pauli coefficients correspond to leakage out of the computational subspace is imprecise: the Pauli twirling approximation also discards the coherent (non-Pauli) error inside the computational subspace, and the sentence should be rephrased.
  4. [Abstract; Figs. 8b and 10b] The unrotated-code claim in the abstract ('strictly fault-tolerant readout schedules can be found') is imported from the unpublished companion Ref. [40]; since Figs. 8b and 10b depend on this property, the manuscript should state this dependence explicitly at the point of the claim.
  5. [App. C.5] Decoding is performed on a detector error model in which the disjoint CZZ error mechanisms are approximated as independent (stim flag 'approximate disjoint errors=True'); for the strongly non-uniform optimized channel, the authors should state the expected size of this approximation or justify it quantitatively.
  6. [Reproducibility] The paper relies on QuTiP, stim, pymatching, and pyfssa but provides no data or code availability statement; a statement (or a repository) would materially aid reproducibility of the reported numbers.

Circularity Check

1 steps flagged · score 4.0 of 10

Load-bearing self-citation supports the unrotated-code fault-tolerance claim; rotated-code results are independent simulations, so overall circularity is partial.

  1. self citation load bearing [Section V, first paragraph (citation of Ref. [40]); abstract: 'We also show that for the unrotated surface code, strictly fault-tolerant readout schedules can be found.']
    "In Ref. [40] some of us have shown that – contrary to the folklore that multi-qubit gates are incompatible with strictly fault-tolerant circuit designs – the unrotated surface code can retain its fault-tolerance when employing a syndrome readout protocol based on 3-qubit CZZ gates."

    The abstract's unrotated-code claim is not derived in this paper; it is imported from Ref. [40], an unpublished companion paper by the same authors (Old, Tasler, Hartmann, Muller, 'to appear (2025)'). The strict fault-tolerance property is load-bearing for the unrotated-code performance claims: it is used to justify the p_L proportional to p^(t+1) scaling and the threshold comparison in Figs. 8b and 10b. Because Ref. [40] is not machine-checked, not externally published, and authored by the present paper's own authors, the unrotated fault-tolerance result reduces to a self-citation chain rather than to an independently verified external fact. The paper's own simulations corroborate the scaling behavior, but the strict-FT property itself is asserted via the citation, not proven here.

full rationale

The central rotated-surface-code results (threshold increase to about 1.2% and up to one order of magnitude logical-error suppression) are obtained from stim/pymatching memory experiments using the effective Pauli channel extracted from the microscopic gate simulation; this is a genuine, discriminative simulation benchmark rather than a renamed input. The optimization weights gamma_K of Eq. 8 are indeed derived from the same QEC framework that later benchmarks the gate, so the design loop is self-referential in the sense that the optimizer is aimed at the same simulator's failure statistics. I do not count this as circularity by construction, however, because the final evaluation (full memory experiments, multiple code distances, idling noise, decoding) is not the same function as the cost function; the improvement is a nontrivial outcome of the simulation, even if not maximally independent of the optimization objective. The paper's caveat that the results are an upper bound because the error model omits some experimental errors, and the separate issue that the headline F=99.96% excludes the paper's own decoherence estimate epsilon_dec, are correctness and robustness concerns, not circularity. Likewise, rescaling the Pauli channel from its simulated operating point to arbitrary p is a modeling extrapolation rather than a self-referential reduction. The one step that satisfies the 'quote-and-reduce' test is the load-bearing self-citation of Ref. [40] for the unrotated strict-fault-tolerance claim, which raises the score to 4 while the rotated-code claims retain independent content.

Assumptions & free parameters 7 free parameters · 8 assumptions · 0 invented entities

The central claims rest on the microscopic simulation chain: circuit quantization (App. A), optimal control pulses (App. B), PTA-based Pauli channel extraction (Sec. IV.A), and stim/pymatching QEC simulations (App. C). Beyond standard QEC methodology, the paper's specific outputs depend on hand-chosen cost weights eta, the simulation-derived harmfulness weights gamma_K, the assumed 50 microsecond coherence time, the SI1000-style noise ratios, and the untested assumption that the Pauli channel shape is invariant under rescaling to p about 1.2%. The unrotated fault-tolerance claim is imported from the unpublished companion work [40]. No new physical entities are introduced.

free parameters (7)
  • Cost-function weights eta = [eta1, eta2, eta3] = [1, 10, 0.1]
    Hand-chosen weights in Eq. (7); both the 35 ns and 50 ns gates report the same weights, and the optimized gate and its Pauli channel depend directly on them. No sensitivity analysis is given.
  • Harmfulness weights gamma_K (63 Pauli marginals) = shown only in Fig. 7 (p=0.001, d=5, 5 rounds)
    Derived from the authors' own conspiracy-graph simulation (Eq. 8) and used as cost weights in Eq. (7). They are the pivot connecting the optimization to the QEC code; neither tabulated values nor code are released.
  • Transmon coherence time tau = 50 microseconds
    Assumed coherence time used in epsilon_dec = 1 - exp(-t_gate/tau) (Eq. 5); the total gate error, and hence the rescaled Pauli channel, scales with tau.
  • Noise model ratios p_reset, p_measure, p_idle = 2p, 5p, 0.1p
    SI1000-inspired circuit-level noise parameters (App. C.3); all QEC results depend on these ratios.
  • Circuit element values (capacitances and qubit frequencies) = Tables II and III
    Chosen symmetrically within literature ranges for experimental feasibility; the ZZ couplings and gate speed depend on them.
  • Resource-extrapolation fit parameters c0, c1, c2 = not reported
    Parameters of the fit p_L(n) = c0 (p/c1)^(c2 sqrt(n)) in Eq. (9), used for the qubit-count comparison in Fig. 11. The fit is labeled as a fit.
  • Optimized pulse amplitudes, durations, ramp times = not reported numerically (Fig. 13 only)
    Nelder-Mead optimized parameters of the flattop-Gaussian pulse ansatz (App. B); the gate and its Pauli channel are the direct output of this optimization.
assumptions (8)
  • domain assumption Canonical circuit quantization with the transmon approximation and a truncated bosonic Hilbert space faithfully models the proposed hardware.
    The Hamiltonian in Eq. (3) is derived in App. A and propagated with QuTiP to produce U_sim; the truncation levels are not stated, and every gate-level number in the paper comes from this model.
  • domain assumption The Pauli twirling approximation plus renormalization of diagonal coefficients yields the gate's effective noise channel.
    Sec. IV.A neglects asymmetric Pauli coefficients as 'leakage' and normalizes the rest; remaining leakage is assumed to be converted into Pauli errors by reset protocols.
  • domain assumption The effective Pauli channel shape is invariant under rescaling from the simulated operating point to any physical error rate p.
    Sec. IV.A rescales all Pauli coefficients so that 1 - w_III = p; Fig. 10 evaluates the channel at p up to about 1.2%, roughly 12 times the simulated total gate error of about 1.06e-3.
  • domain assumption CZZ and CZ gates are assigned equal per-location error probability p in the QEC comparison.
    App. C.3 sets p_H = p_CZ = p_CZZ = p, although the 35 ns CZZ carries a larger simulated decoherence error than a faster CZ gate would at the same coherence time.
  • domain assumption Harmfulness marginals computed at d=5, 5 rounds, p=1e-3 with pymatching generalize to all distances and error rates.
    Sec. V.A fixes one operating point (rotated code, d=5, 5 rounds, uniform depolarizing, p=0.001); the evaluation in Figs. 8-11 spans d=3 to 13 and p from 1e-4 to 1e-2 with the same decoder.
  • ad hoc to paper The unrotated CZZ readout schedule is strictly fault-tolerant, per companion Ref [40].
    Sec. V: 'In Ref. [40] some of us have shown...' the unrotated schedule retains fault-tolerance and a higher threshold; the reference is unpublished ('to appear') with overlapping authorship, so the claim cannot be checked from this manuscript.
  • domain assumption The flattop-Gaussian pulse ansatz spans the relevant reachable gate set.
    App. B restricts each coupler pulse to a flattop Gaussian with three optimizable parameters; optimality and the reported gate error are relative to this ansatz.
  • standard math Minimum-weight perfect matching on an approximately independent detector error model is adequate for the logical error conclusions.
    App. C.5 uses pymatching with approximate_disjoint_errors=True; the harmfulness ranking (Sec. V.A) and the logical error rates depend on decoder strength.

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Pith. "Pith review of Optimizing Superconducting Three-Qubit Gates for Surface-Code Error Correction." pith.science (2026). https://pith.science/paper/BTXDKNY7

@misc{pith2026250609028,
  author       = {Pith},
  title        = {Pith review of: Optimizing Superconducting Three-Qubit Gates for Surface-Code Error Correction},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/BTXDKNY7}},
  note         = {Machine review of arXiv:2506.09028}
}
abstract

Quantum error correction (QEC) is one of the crucial building blocks for developing quantum computers that have significant potential for reaching a quantum advantage in applications. Prominent candidates for QEC are stabilizer codes for which periodic readout of stabilizer operators is typically implemented via successive two-qubit entangling gates, and is repeated many times during a computation. To improve QEC performance, it is thus beneficial to make the stabilizer readout faster and less prone to fault-tolerance-breaking errors. Here we design a 3-qubit CZZ gate for superconducting transmon qubits that maps the parity of two data qubits onto one measurement qubit in a single step. We find that the gate can be executed in a duration of $35\,$ns with a fidelity of F$=99.96 \, \%$. To optimize the gate, we use an error model obtained from the microscopic gate simulation to systematically suppress Pauli errors that are particularly harmful to the QEC protocol. Using this error model, we investigate the implementation of this 3-qubit gate in a surface code syndrome readout schedule. We find that for the rotated surface code, the implementation of CZZ gates increases the error threshold by nearly 50\% to $\approx 1.2\,\%$ and decreases the logical error rate, in the experimental relevant regime, by up to one order of magnitude, compared to the standard CZ readout protocol. We also show that for the unrotated surface code, strictly fault-tolerant readout schedules can be found. This opens a new perspective for below-threshold surface-code error correction, where it can be advantageous to use multi-qubit gates instead of two-qubit gates to obtain a better QEC performance.

Figures

Figures reproduced from arXiv: 2506.09028 by the authors.

Figure 1
Figure 1. FIG. 1. Schematic illustration of the unrotated (a) (rotated [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 3
Figure 3. FIG. 3. The CZZ gate can be used to measure the [PITH_FULL_IMAGE:figures/full_fig_p003_3.png] view at source ↗
Figure 4
Figure 4. FIG. 4. The parallel CZ gate is implemented on a supercon [PITH_FULL_IMAGE:figures/full_fig_p004_4.png] view at source ↗
Figures from the paper (14 more)
Figure 5
Figure 5. Figure 5: FIG. 5. The simulated channel [PITH_FULL_IMAGE:figures/full_fig_p005_5.png]
Figure 6
Figure 6. Figure 6: FIG. 6. Graph [PITH_FULL_IMAGE:figures/full_fig_p007_6.png]
Figure 7
Figure 7. Figure 7: FIG. 7. Effective Pauli channels are displayed by the orange bars for the 35 ns gate and the green bars for the 50 ns gate. The [PITH_FULL_IMAGE:figures/full_fig_p009_7.png]
Figure 8
Figure 8. Figure 8: FIG. 8. Results for rotated (a) and unrotated (b) surface codes: We show the logical error rates of uniform depolarizing [PITH_FULL_IMAGE:figures/full_fig_p010_8.png]
Figure 9
Figure 9. Figure 9: FIG. 9. Logical error rates for CZZ circuits for the uniform gate noise model and the 35 ns [PITH_FULL_IMAGE:figures/full_fig_p010_9.png]
Figure 10
Figure 10. Figure 10: FIG. 10. Threshold plots. a) Rotated surface codes show an increase in threshold from [PITH_FULL_IMAGE:figures/full_fig_p011_10.png]
Figure 11
Figure 11. Figure 11: FIG. 11. Number of physical qubits required to reach a target logical error rate, including auxiliary qubits, i.e. [PITH_FULL_IMAGE:figures/full_fig_p011_11.png]
Figure 12
Figure 12. Figure 12: FIG. 12. Circuit diagram of the parity check circuit. The active nodes are depicted by the red dots. [PITH_FULL_IMAGE:figures/full_fig_p013_12.png]
Figure 13
Figure 13. Figure 13: FIG. 13. The two tunable couplers are strongly tuned close to the ancilla qubit frequency, this results in a large [PITH_FULL_IMAGE:figures/full_fig_p016_13.png]
Figure 14
Figure 14. Figure 14: FIG. 14. a) Orderings 21 [PITH_FULL_IMAGE:figures/full_fig_p017_14.png]
Figure 15
Figure 15. Figure 15: FIG. 15. One round of stabilizer measurements of distance 3 surface codes in the a) rotated and b) unrotated implementation [PITH_FULL_IMAGE:figures/full_fig_p017_15.png]
Figure 16
Figure 16. Figure 16: FIG. 16. Simulation workflow using [PITH_FULL_IMAGE:figures/full_fig_p019_16.png]
Figure 17
Figure 17. Figure 17: FIG. 17. Logical error rates of the 50 ns gate compared to the the 35 ns gate and CZ circuit with uniform noise in Fig. 17. a) [PITH_FULL_IMAGE:figures/full_fig_p019_17.png]
Figure 18
Figure 18. Figure 18: FIG. 18. Threshold plots and finite size scaling analysis for circuits shown in the main text. a) - d) Rotated surface codes show [PITH_FULL_IMAGE:figures/full_fig_p020_18.png]

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Forward citations

Cited by 2 Pith papers

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Pith tools

Reviewed August 7, 2026 · model on record in the stance chip above.