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REVIEW 3 major objections 5 minor 34 references

ABC-FHE : A Resource-Efficient Accelerator Enabling Bootstrappable Parameters for Client-Side Fully Homomorphic Encryption

T0 review · 3 major / 5 minor · reviewed 2026-08-07 · deepseek-v4-flash

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Pith's one-line read ABC-FHE claims a client-side FHE accelerator that supports bootstrappable parameters, reaching up to 1112x speedup over CPU for encode/encrypt and 963x for decode/decrypt.

desk verdict A plausible client-side FHE accelerator with a real architecture contribution, but the headline speedups over prior work rest on a shaky linear-scaling assumption that likely overstates the gap. read the letter →

arxiv 2506.08461 v1 pith:BVSYRPYR submitted 2025-06-10 cs.AR cs.CRcs.ET

Sungwoong Yune , Hyojeong Lee , Adiwena Putra , Hyunjun Cho , Cuong Duong Manh , Jaeho Jeon , Joo-Young Kim This is my paper · ORCID
classification cs.ARcs.CRcs.ET
keywords fullyhomomorphicencryptionCKKSclient-sideacceleratorNTT/FFTstreamingarchitecturebootstrappingMontgomerymultiplicationtwiddlefactorgeneration
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

ABC-FHE is a chip design whose goal is to remove the client-side bottleneck in fully homomorphic encryption (FHE), specifically the encode/encrypt and decode/decrypt steps of the CKKS scheme at large polynomial degrees (up to $2^{16}$) that support bootstrapping. Prior client-side accelerators were limited to smaller parameters and hit DRAM bandwidth walls when scaled up. The paper claims that a streaming architecture with a reconfigurable Fourier engine and on-chip generation of random values and twiddle factors can handle bootstrappable parameters while remaining small enough for client devices, reporting 28.638 mm$^2$ die area and 5.654 W power in 28nm technology. Against a CPU it reports speedups of up to 1112x for encoding and encryption and 963x for decoding and decryption; against the prior state-of-the-art client accelerator, up to 214x and 82x, respectively.

What carries the argument

The load-bearing object is the Reconfigurable Fourier Engine (RFE), composed of four pipelined NTT lanes that switch between 44-bit integer modular arithmetic (NTT) and a custom 55-bit floating-point format (FFT) by reconfiguring the modular multipliers into complex-number multipliers. The pipeline is a multi-path delay commutator (MDC) radix-$2^n$ design, and the paper argues that radix-$2^n$ is the only family that preserves the twiddle factor pattern needed to fold nega-cyclic pre/post-processing into the existing multiplier stages, eliminating extra multipliers. Two supporting mechanisms carry the memory argument: the unified on-the-fly twiddle factor generator (OTF TF Gen), shared across all lanes, produces each stage's twiddle factors from small seeds and step sizes, and an on-chip PRNG generates random masks, errors, and keys. Together they keep the streaming cores fed without large off-chip parameter fetches, which the paper identifies as the bottleneck that capped earlier client accelerators.

What would settle it

Take a prior client-side accelerator, such as the compact RNS-CKKS en/decoding/decryption accelerator, and measure its encode/encrypt and decode/decrypt latency directly at polynomial degree $2^{16}$ with the same 24-level parameters; if the measured latency is higher than the paper's linearly scaled estimate, the 214x and 82x speedups are overstated. On the ABC-FHE side, running the same workload while reducing DRAM bandwidth below the assumed 68.4 GB/s would test whether the streaming design truly avoids a memory bottleneck.

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Extended reading notes

Core claim

The paper's central claim is that client-side CKKS processing under bootstrappable parameters can be implemented as a compact streaming datapath: a reconfigurable Fourier engine (RFE) that executes both integer NTT and complex FFT on the same pipelined lanes, with a modular streaming engine (MSE) for RNS, CRT, and elementwise operations. The RFE uses a radix-$2^n$ multi-path delay commutator pipeline, chosen because only radix-$2^n$ keeps the twiddle-factor pattern needed to merge nega-cyclic pre/post-processing into the multiplier schedule, reaching the theoretical minimum of $P/2 \times \log_2 N$ multipliers. A custom 'NTT-friendly' Montgomery multiplier selects primes of the form $2^{p_{bw}} + k \cdot 2^{n+1} + 1$ so that reduction becomes shift-and-add, cutting modular multiplier area by 41.2% versus vanilla Montgomery and 67.7% versus Barrett. The design generates twiddle factors on the fly from a 26.4 KB seed memory and random masks, errors, and keys from a 128-bit-seed PRNG, replacing over 99.9% of the on-chip storage that would otherwise be needed, and thereby avoiding DRAM traffic that would stall the streaming pipeline. With these pieces, the paper reports the speedups listed above and projects scaling to roughly 0.9 mm$^2$ and 2.1 W in 7nm.

Load-bearing premise

The load-bearing premise is that the prior accelerators' performance can be fairly estimated by scaling their measured latency by the proportion of operations, since they cannot run the bootstrappable parameters ABC-FHE targets; if real memory-bound and pipeline effects make their latency grow faster than that linear scaling, the claimed speedups over them shrink.

Editorial extensions

If this is right

  • Client-side FHE moves from a dominant bottleneck to a minor one: with ABC-FHE's numbers, encode/encrypt and decode/decrypt take milliseconds at $N=2^{16}$, making interactive or edge FHE workloads practical.
  • Bootstrappable parameters become usable on the client: supporting $N$ up to $2^{16}$ with 24 levels means the full CKKS bootstrapping pipeline can run end-to-end, not just small-parameter toy cases.
  • The same hardware can serve encryption and decryption asymmetrically: the two reconfigurable cores can double throughput on one direction or run encrypt and decrypt concurrently, matching the 10:1 workload imbalance the paper measures.
  • On-chip parameter generation removes the need for high-bandwidth memory: because twiddle factors and random values are generated internally, the design runs under LPDDR5-class bandwidth, which is realistic for client devices.
  • The area optimizations compound: twiddle scheduling, NTT-friendly Montgomery multipliers, and NTT/FFT reconfigurability reduce RFE area by 31%, and the resulting 28nm footprint scales to under 1 mm$^2$ in 7nm.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • If the streaming-plus-on-chip-generation design is as effective as claimed, it suggests a broader recipe for FHE client accelerators: minimize off-chip state by generating keys, masks, errors, and twiddle factors on-chip, rather than caching them; this recipe may transfer to BFV/BGV client operations, which share the same NTT structure.
  • The paper's speedup comparison scales prior accelerators by operation proportion, so the 214x and 82x figures are conditional on linear scaling; a direct measurement of the previous chips at $N=2^{16}$ would be the cleanest test of the comparison.
  • The FP55 format selected via the bootstrapping-precision curve (23.39 bits at 43 mantissa bits) is a design parameter worth reusing: the same iterative mantissa-reduction methodology could be applied to other approximate workloads that need a known precision floor.
  • The NTT-friendly prime restriction changes the parameter landscape: a direct security and functionality audit should confirm that the restricted prime set still covers the bootstrapping levels and security margins that CKKS deployments require.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 5 minor

Summary. The paper proposes ABC-FHE, a client-side CKKS accelerator designed for bootstrappable parameters (polynomial degree up to 2^16 and 24 levels). The architecture combines two reconfigurable streaming cores, each containing a reconfigurable Fourier engine that switches between NTT and FFT modes, a modular streaming engine, an on-chip PRNG, and a unified on-the-fly twiddle-factor generator. The authors report synthesis results of 28.638 mm2 area and 5.654 W power in 28 nm at 600 MHz, and cycle-level simulator speedups of up to 1112x and 963x over a CPU for encoding/encryption and decoding/decryption, respectively, and 214x and 82x over prior client-side accelerators [22], [34].

Significance. If the reported results are valid, the paper makes a useful contribution to an under-served part of the FHE stack: client-side operations under bootstrappable parameters. The workload analysis in Section II.D is valuable, and the concrete microarchitectural choices, including the reconfigurable NTT/FFT datapath, on-chip generation of randomness and twiddle factors, and the area-optimized Montgomery multiplier, are significant engineering contributions. The use of a cycle-level simulator plus 28 nm synthesis for area and power is a strength. The main weakness is the comparison methodology against prior accelerators, which rests on an unvalidated linear-scaling assumption; this directly affects the headline 214x and 82x speedup claims.

major comments (3)
  1. [Section V.C, Fig. 5(a)] The reported 214x and 82x improvements over state-of-the-art accelerators are computed by scaling the published latencies of [22] and [34] 'by the proportion of operations' because those designs do not support N=2^16, 24-level parameters. This assumes execution time scales linearly with arithmetic operation count. The paper's own Section I argues that non-streaming designs are DRAM-bandwidth-limited and that [34] fetches parameters from DRAM; under larger N and more levels, memory traffic and stalls should grow at least proportionally to data volume, and likely faster when output per cycle exceeds DRAM bandwidth. No memory model, cycle-level description, or sensitivity analysis for the prior designs is provided to justify the linear rule. Please either re-run the comparison with memory-aware scaling of the prior works, provide a range of speedups under alternative scaling assumptions, or restrict the claims to CPU comparisons. Without this, the SOTA speedups are not established.
  2. [Section III, Fig. 3(c)] The choice of FP55 with a 43-bit mantissa is load-bearing for the area, power, and latency results, but the bootstrapping-precision experiment is only described as 'iteratively reduced the floating-point mantissa bitwidth and evaluated Boot. prec.' No details are given for the precision simulation: what model and dataset are used, what CKKS parameter set and noise budget, how many bootstrapping operations are performed, and how Boot. prec. is computed. Without this, a reader cannot assess whether 43 bits is sufficient or whether the 23.39-bit result is an artifact of a particular test. Please provide the evaluation setup and, ideally, a plot of Boot. prec. versus mantissa width with the 19.29-bit threshold marked.
  3. [Section IV.A, Eqs. (8)-(11)] The NTT-friendly Montgomery multiplier claim needs a clearer statement of the supported prime set. Equation (8) restricts primes to Q = 2^{p_bw} + k*2^{n+1} + 1, and Eq. (11) further restricts k to particular signed sums of three powers of two. The text asserts that the design 'still sufficiently supports 20-40 encryption levels' and mentions 443 primes for N=2^16, but it does not show that the required RNS moduli all satisfy Eqs. (8)-(11) or count how many primes of each bitwidth satisfy the restrictions. Please provide a prime-count verification for the parameter sets used in the evaluation.
minor comments (5)
  1. [Section V heading] The section heading reads 'EVALUTATION'; please correct to 'EVALUATION'.
  2. [Section II.B] The sentence 'NTT and FFT, which perform complex-number and modular computations, respectively' appears to swap the two operations: NTT is modular arithmetic and FFT is complex-number arithmetic.
  3. [Figure 3(c)] The inset graph showing bootstrapping precision versus mantissa bitwidth lacks labeled axes and a legend; the text refers to a 'drop-off point' but the curve is not described clearly.
  4. [Section III] There are several typographical errors, including 'eleminating' (should be 'eliminating') and 'reconfigurablility' (should be 'reconfigurability').
  5. [Section V.C] The statement that prior FPGA and ASIC results were 'normalized to match ABC-FHE's 600 MHz frequency' should clarify whether memory latency is also scaled with frequency or held constant, since this affects the comparison.

Circularity Check

0 steps flagged · score 0.0 of 10

No circularity; the accelerator's speedups are independent simulator measurements against external baselines, and the FP55 precision is a design constraint fit to an external precision threshold.

full rationale

ABC-FHE's central claims are performance measurements from a cycle-level simulator and synthesis results, benchmarked against a CPU running Lattigo and previously published accelerators. The only parameter fit in the design flow is the FP55 mantissa width, chosen by iteratively reducing mantissa bits until the bootstrapping precision stayed above the 19.29-bit threshold established by external prior work [19]; this is a design constraint, not a prediction derived from itself. The SOTA comparisons in Sec. V.C do scale prior latencies 'by the proportion of operations,' which is an extrapolation assumption that could overstate speedups if prior designs are memory-bound, but this is a threat to validity of the comparison, not a circular reduction: the comparison does not use ABC-FHE's own outputs as inputs. No load-bearing self-citation appears; citations to [28] and [29] are background references to server-side accelerators, and the bootstrapping-precision and double-scale premises come from external groups. No uniqueness theorem is imported from the authors' prior work, and the radix-2^n choice is justified by the paper's own multiplier-count analysis rather than by citation. Hence no circular step can be exhibited, and the circularity score is 0.

Assumptions & free parameters 2 free parameters · 4 assumptions · 0 invented entities

The central claim rests on simulation rather than silicon. The main free parameters are the FP55 datapath width (43 mantissa bits), chosen by fitting to a bootstrapping precision threshold, and the number of PNL lanes (8), chosen from a memory-bandwidth analysis. The key axioms include the external precision threshold from [19], the double-scale technique from [1], LPDDR5 bandwidth assumptions, and the ad hoc linear-scaling of prior-work latencies.

free parameters (2)
  • FP55 mantissa bitwidth = 43 bits
    Iteratively reduced until measured Boot. prec. 23.39 bits exceeded the 19.29-bit threshold from [19]; a fitted design parameter rather than a derived constant.
  • PNL lane count P = 8
    Chosen based on LPDDR5 bandwidth analysis (Figure 5b); an engineering choice, not derived from a theorem.
assumptions (4)
  • domain assumption Bootstrapping precision must stay above 19.29 bits to sustain AI model accuracy
    Adopted from SHARP [19]; used to justify the FP55 format. Not re-derived for ABC-FHE's workload.
  • domain assumption Double scale technique allows 36-bit primes with doubled levels
    From [1]; the evaluation uses 36-bit primes and 24 levels based on this external result.
  • domain assumption LPDDR5 bandwidth of 68.4 GB/s is representative of client devices
    Used to size the global scratchpad and justify the 8-lane PNL choice.
  • ad hoc to paper Prior accelerators' latencies scale linearly with operation count
    Section V.C: 'their reported latency was scaled by the proportion of operations for fair comparison'. This linear-scaling assumption is not justified and changes the headline speedups.

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Cite this review

Pith. "Pith review of ABC-FHE : A Resource-Efficient Accelerator Enabling Bootstrappable Parameters for Client-Side Fully Homomorphic Encryption." pith.science (2026). https://pith.science/paper/BVSYRPYR

@misc{pith2026250608461,
  author       = {Pith},
  title        = {Pith review of: ABC-FHE : A Resource-Efficient Accelerator Enabling Bootstrappable Parameters for Client-Side Fully Homomorphic Encryption},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/BVSYRPYR}},
  note         = {Machine review of arXiv:2506.08461}
}
read the original abstract

As the demand for privacy-preserving computation continues to grow, fully homomorphic encryption (FHE)-which enables continuous computation on encrypted data-has become a critical solution. However, its adoption is hindered by significant computational overhead, requiring 10000-fold more computation compared to plaintext processing. Recent advancements in FHE accelerators have successfully improved server-side performance, but client-side computations remain a bottleneck, particularly under bootstrappable parameter configurations, which involve combinations of encoding, encrypt, decoding, and decrypt for large-sized parameters. To address this challenge, we propose ABC-FHE, an area- and power-efficient FHE accelerator that supports bootstrappable parameters on the client side. ABC-FHE employs a streaming architecture to maximize performance density, minimize area usage, and reduce off-chip memory access. Key innovations include a reconfigurable Fourier engine capable of switching between NTT and FFT modes. Additionally, an on-chip pseudo-random number generator and a unified on-the-fly twiddle factor generator significantly reduce memory demands, while optimized task scheduling enhances the CKKS client-side processing, achieving reduced latency. Overall, ABC-FHE occupies a die area of 28.638 mm2 and consumes 5.654 W of power in 28 nm technology. It delivers significant performance improvements, achieving a 1112x speed-up in encoding and encryption execution time compared to a CPU, and 214x over the state-of-the-art client-side accelerator. For decoding and decryption, it achieves a 963x speed-up over the CPU and 82x over the state-of-the-art accelerator.

Figures

Figures reproduced from arXiv: 2506.08461 by the authors.

Figure 1
Figure 1. Execution time breakdown of overall client-side and server-side [PITH_FULL_IMAGE:figures/full_fig_p001_1.png] view at source ↗
Figure 2
Figure 2. Workload analysis of CKKS client-side operations: (a) Operational [PITH_FULL_IMAGE:figures/full_fig_p002_2.png] view at source ↗
Figure 3
Figure 3. Overall architecture of ABC-FHE (a) Top level view (b) Core level view (c) Engine level view. [PITH_FULL_IMAGE:figures/full_fig_p003_3.png] view at source ↗
Figures from the paper (2 more)
Figure 4
Figure 4. Figure 4: (a) Twiddle factor scheduling in NTT signal flow graph (b) Distribution [PITH_FULL_IMAGE:figures/full_fig_p004_4.png]
Figure 5
Figure 5. Figure 5: Performance of ABC-FHE (a) Execution time and speed-up for en [PITH_FULL_IMAGE:figures/full_fig_p006_5.png]

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