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REVIEW 3 major objections 4 minor 54 references

You Only Charge Once 2.0 : A End-to-End Analog Computing-in-Memory Architecture with Reconfigurable Switched Capacitors

T0 review · 3 major / 4 minor · reviewed 2026-08-12 · deepseek-v4-flash

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Pith's one-line read Charge-CIM claims one reconfigurable switched-capacitor fabric can carry an INT8 vector–matrix multiply from input to quantized output in the analog domain, cutting ADC energy by 91.7% in simulation.

desk verdict Clever slice-free charge-domain CIM that unifies DAC/MAC/SA/ADC in one capacitor network, but Phase 5's weighted shift-add lacks a specified switch topology and the input DAC capacitance budget doesn't obviously fit the array. read the letter →

arxiv 2608.11116 v1 pith:CMXUMNP3 submitted 2026-08-11 cs.AR

Zihao Xuan , Yewen Li , Jia Chen , Wei Xuan , Xiao Huo , Fengbin Tu This is my paper · ORCID
classification cs.AR
keywords analogcomputing-in-memorycharge-domaincomputingswitched-capacitorcircuitsADCwallsuccessive-approximationregisterINT8quantizationDNNacceleratorchargeredistribution
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

Charge-CIM is an attempt to remove the 'ADC wall' that dominates the energy and area of analog computing-in-memory (ACiM) accelerators. The paper argues that bit-sliced execution—splitting inputs and weights into bits and converting each partial sum—is the root cause, and that a single reconfigurable switched-capacitor network can instead carry an INT8 vector–matrix multiply (VMM) from input conversion through analog accumulation and shift-add to quantized readout. The same capacitors are reused as the input DAC, the multiplier storage, the column accumulator, the binary-weighted adder, and the capacitive DAC of an embedded SAR ADC, so charge is injected once and only digitized once. In simulation, this cuts ADC energy by 91.7% and improves energy efficiency by 2.71x and throughput by 2.01x over the Cambricon-CIM baseline. If correct, the design would make analog inference accelerators cheaper and more energy-efficient for CNN, Transformer, and LLM workloads.

What carries the argument

The load-bearing object is a reconfigurable switched-capacitor fabric: every memory-and-compute cell (MCC) contains SRAM weight bits and a unit capacitor $C_u = 2.66\,\mathrm{fF}$, and three switch networks ($S_{DAC}$, $S_{ACC}$, $S_{SA}$) rewire those capacitors between phases. In Phases 1–2 the row capacitors form an $N$-bit embedded DAC; in Phase 3 each capacitor conditionally stores $V_{\mathrm{in}}\cdot W$; in Phase 4 column switches average the partial products; in Phase 5 the $S_{SA}$ network regroups columns into binary ratios $1:2:\dots:2^{M-1}$; and in Phase 6 the same groups serve as the capacitive DAC (C-DAC) of a monotonic successive-approximation-register (SAR) ADC. This one-fabric reuse is what lets the design 'charge once' and convert only at the end, avoiding the repeated ADC invocations that follow from bit-slicing.

What would settle it

Fabricate the 256×128 macro in 28\,nm with $2.66\,\mathrm{fF}$ unit capacitors and measure the end-to-end transfer curve while sweeping all 8-bit input and weight codes; if the $S_{SA}$ regrouping cannot produce the $1:2:\dots:2^{M-1}$ capacitance ratios, the measured INL/DNL and end-to-end RMSE should exceed the reported $+1.12/-1.14$ LSB and $1.6\%$, falsifying the central claim.

Watch

Extended reading notes

Core claim

The central claim is that fully analog multi-bit computation is possible without arithmetic slicing: a 256×128 macro of memory-and-compute cells, each holding a unit capacitor and weight bit, can execute an 8-bit-input by 8-bit-weight VMM in six charge-sharing phases. Input bits charge binary-sized capacitor groups ($C_n = 2^n C_u$) that are then shorted row-wise to produce an analog input voltage; a NAND-like switch conditionally retains or discharges that charge according to each weight bit; column-wise charge sharing averages the partial products; reconfigurable $S_{SA}$ switches regroup the same unit capacitors into $1:2:\dots:2^{M-1}$ ratios to implement bit-weighted shift-add; and the same array becomes the capacitive DAC of a monotonic SAR ADC that quantizes in place. The paper derives the end-to-end expression $V_{out,j} = \frac{\sum_{m=0}^{M-1}\sum_{i=0}^{P-1}\sum_{n=0}^{N-1} 2^n X_i[n] \cdot 2^m W_{ij}[m]}{(2^M-1)P \cdot 2^N} V_{DD}$ and reports that the differential readout with inverse coding turns the ADC's natural subtraction into partial-sum addition, halving conversions and reaching pseudo-9-bit resolution. This is the 'You Only Charge Once' path: charge is injected once at the supply in Phase 1 and only leaves during ADC discharge. The paper claims this eliminates the standalone-DAC and intermediate-ADC costs that make up more than half of energy in prior charge-domain CIM.

Load-bearing premise

The design assumes that after column-wise charge sharing, the same unit capacitors can be rewired into exact $1:2:4:\dots$ binary groups for the shift-add step with no charge lost, and that the row has enough room to host both the $2^N$ unit capacitors for input conversion and the 8-bit weight mapping.

Editorial extensions

If this is right

  • Bit-slicing disappears: an 8-bit input and an 8-bit weight contribute in one analog pass, so the number of ADC conversions per output drops from the product of slice counts to one per compute-bar read.
  • The reused capacitor array removes the standalone C-DAC of a conventional ADC, shrinking converter area to 3% of total chip area and reducing ADC energy by 91.7% in the paper's simulation.
  • Differential inverse coding folds partial-sum addition into the SAR comparison, halving the number of readout conversions and lifting the effective readout resolution to pseudo-9-bit.
  • Configurable bit-width and base reformation let the same fabric switch between 8-bit, 4-bit, 2-bit, 1-bit, and non-binary coding without hardware changes.
  • Across nine CNN, Transformer, and LLM benchmarks, the claimed average gains are 2.71x energy efficiency and 2.01x throughput over Cambricon-CIM, with end-to-end VMM RMSE of 1.6% and accuracy loss at most 1.9 percentage points.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • The same one-charge principle, if it holds in silicon, should extend to higher bit widths (e.g., 16-bit) by adding more binary-weighted groups, though the $2^N$ unit-capacitance growth would eventually dominate area; the paper only demonstrates up to 8-bit configurations.
  • The differential in-ADC accumulation could in principle merge partial sums from multiple spatially partitioned arrays, removing digital accumulation trees for large models; the paper applies it only within a macro's paired arrays.
  • Because the arithmetic is fixed by capacitor ratios rather than by a fixed codebook, the fabric could be reprogrammed to non-binary bases (such as the coding-base reformation used by Cambricon-CIM) by reordering input bits; the paper gives one 3:4 example but does not search this design space.
  • A silicon measurement of the Phase 5 regrouping would be the decisive test: if switch parasitics discard charge from unselected capacitors, the reported 1.6% end-to-end RMSE and 4.46 mV peak quantization error would not survive, independent of the architecture-level simulations.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 4 minor

Summary. Charge-CIM is a proposed charge-domain analog computing-in-memory (ACiM) macro architecture that reuses a switched-capacitor network for input digital-to-analog conversion, 1-bit multiplication, column-wise accumulation, binary-weighted shift-and-add across weight-bit columns, and in-situ SAR-ADC quantization. The paper derives an end-to-end VMM expression (Eq. 5), presents a differential readout with 'inverse coding' to accumulate paired partial sums, and evaluates the design with SPICE-based circuit simulation plus Timeloop/Accelergy architecture simulation. Against RAELLA and Cambricon-CIM, it reports 91.7% ADC energy reduction, 2.71x energy efficiency, and 2.01x throughput improvements across nine DNN/LLM benchmarks.

Significance. If the architectural feasibility were fully established, Charge-CIM would be a meaningful step toward eliminating the ADC wall in ACiM by replacing bit-sliced execution with a single charge-processing path. The paper's ideal-equation derivation is internally consistent, the offset-encoding treatment of signed arithmetic is correct, and the evaluation methodology (SPICE extraction, Monte Carlo mismatch, architecture-level simulation, ablation) is appropriate for the field. The claims are falsifiable and the paper provides a clear quantitative comparison. However, the central contribution depends on a physical reconfiguration that is not specified at the switch level; until that is resolved, the results should be treated as conditional.

major comments (3)
  1. [III.A, Phase 5, Eq. (4)] The paper never specifies the switch topology that realizes the binary-weighted regrouping in Phase 5. After Phase 4, all P unit capacitors in a given column are shorted by S_ACC, so each column contains P identical capacitors at V_acc[j][m]. Equation (4) requires the S_SA network to connect exactly 1, 2, ..., 2^{M-1} capacitors from successive bit columns to a common output node and to isolate the remaining P - 2^m capacitors. The text only states that 'S_SA switches configure the shared capacitance ratio between columns'; it does not say whether these are per-capacitor switches, per-column switches, or a ladder network. If S_SA simply shorts whole columns, the output is an unweighted average. If per-capacitor switches are assumed, their area and control overhead are absent from Table III, and the charge on the disconnected capacitors is discarded without a described reset. This is load-bearing: without a concrete S_SA topology, Eq. (4) is an ungrounded mathematical identity and the central slice-free multi-bit claim is not established.
  2. [III.A, Phase 2, Eq. (1) and Table III] The embedded DAC requires C_tot = 2^N C_u per row; for N=8 this is 256 unit capacitors per row. The macro is specified as 256×128 in Table III, giving only 128 columns (and hence 128 MCCs) per row, and Section III.A describes each MCC as containing 'a unit switched capacitor'. No explanation is given for how 256 unit capacitors fit in a 128-column row while also accommodating the weight-bit mapping. If each row truly contains only 128 unit capacitors, the maximum input precision is 7 bits, which would contradict the INT8 VMM claim. The paper should provide a concrete row layout (e.g., multiple unit capacitors per MCC, or a different macro dimension) or revise the precision claims.
  3. [IV-B, Eq. (8)] The inverse-coding scheme states that 'the V_N-side array is driven by pre-inverted inputs (I_inv = -I_N), generating a negative partial sum V_N = -I_N·W_N.' In the charge-domain implementation described in Section III, voltages are inherently non-negative (between 0 and V_DD), so a literal negative partial sum cannot appear on a single-ended capacitor node. The paper should clarify the physical mechanism: e.g., bitwise inversion combined with offset compensation, differential plate swapping, or a negative reference. As written, Eq. (8) is a mathematical identity rather than a demonstrated circuit behavior, and the claim of in-ADC partial-sum addition rests on this mechanism.
minor comments (4)
  1. [III.A(1)] The text says '2N MCCs are grouped via N SDAC switches in a binary ratio (1 : 1 : 2 : ... : 2^{N-1})'; this should be '2^N' (or '2^N - 1 unit capacitors'), since the binary ratio sums to 2^N - 1, not 2N.
  2. [Fig. 13 caption] The caption states 'Cambricon-CIM achieves geometric means of 2.26× and 3.69×, respectively' without specifying what those numbers refer to; the text reports 2.71× and 2.01× improvements for Charge-CIM. Please clarify the comparison direction and the meaning of the geometric means.
  3. [Table III] The MCC row lists '2.66 fF 2.15fJ/act 1.74µm^2' with mixed units; please separate capacitance, energy per activation, and area into distinct columns with clear headers.
  4. [V.A] The statement that the 256×128 macro is split into two 128×128 subarrays operating differentially should be reconciled with the embedded-DAC capacitance requirement per row; as written, it reinforces the concern in Major Comment 2.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: the central VMM derivation is a charge-conservation identity with independently simulated energy/accuracy results; self-citations are background only.

full rationale

We walked the derivation chain. The six-phase operation defines the embedded DAC, multiplication, accumulation, shift-add, and SAR quantization as constructions on a switched-capacitor array; Eqs. (1)-(6) follow from charge conservation and the stated binary capacitor ratios, so the multi-bit VMM expression in Eq. (5) is a direct composition of those definitions rather than a hidden restatement of the claimed result. The offset-encoding equation (7) and inverse-coding equation (8) are exact algebraic identities used to realize signed arithmetic and differential in-ADC accumulation; they are design transformations, not fitted predictions. The 91.7% ADC-energy reduction, 2.7x energy efficiency, 2.0x throughput, and accuracy numbers are produced by SPICE/architecture-level simulation against external baselines (RAELLA and Cambricon-CIM), with noise parameters extracted from circuit simulation and Monte Carlo analysis rather than tuned to match the reported outcomes. The only self-citations are prior work by the same group (YOCO [49] and [48]) cited as background for charge-domain shift-add and ADC-free MAC; they are not load-bearing for the new differential embedded-ADC or inverse-coding contributions, and no uniqueness theorem or ansatz is imported from them. A switch-level topology for Phase 5's binary regroupings is indeed unspecified, but that is a feasibility/completeness risk, not a circularity, because the claimed equation is not made true by fitting a parameter to itself.

Assumptions & free parameters 3 free parameters · 7 assumptions · 0 invented entities

All claims assume ideal charge sharing and realistic circuit non-idealities from simulation. There are no new physical entities. The main free choices are the unit capacitance and the simulated noise and ENOB parameters.

free parameters (3)
  • Unit capacitance C_u = 2.66 fF
    Selected as the balance point between Monte-Carlo mismatch (3sigma approx 1.18 LSB) and area/power (Table IV, Section V-A). The energy, noise, and area numbers used in the comparison all depend on this choice.
  • DAC and MAC noise variances sigma_DAC^2 and sigma_MAC^2 = Not reported numerically; extracted from SPICE/post-layout simulation
    The end-to-end RMSE of 1.6 percent and the DNN accuracy loss use these extracted variances in Eq. (9); they are simulation outputs used to predict accuracy, not independent measurements.
  • ADC ENOB = 8-bit ENOB
    The ADC quantization error model rounds partial sums at 8-bit ENOB; this is a design and calibration target rather than a measured silicon result.
assumptions (7)
  • standard math Ideal charge redistribution with binary-weighted capacitors
    Equations (1)-(5) assume charge conservation and ideal capacitor ratios; no parasitic or nonlinearity model is included in the derivation.
  • domain assumption Analog multiplication by conditional discharge is exact and linear
    Phase 3 assumes V_mul = V_in * W with no threshold loss, charge injection, or body effect; SPICE simulations are used to claim this holds.
  • domain assumption Phase timing and settling error below 0.46 LSB
    The six-phase operation is budgeted to 20 ns with worst-case residual settling error stated but not independently verified.
  • domain assumption Gaussian independent DAC/MAC noise plus kT/C model captures analog errors
    Eq. (9) combines sigma_DAC, sigma_MAC, and thermal noise; this model is used to predict DNN accuracy degradation.
  • domain assumption Differential SAR ADC with inverse coding realizes Eq. (8) without additional offset errors
    The in-ADC addition relies on the differential interface subtracting two arrays whose inputs are pre-inverted; the implementation overhead and error terms are not modeled.
  • domain assumption Baseline architectures are faithfully reconstructed and normalized to 300 mm2
    RAELLA and Cambricon-CIM configurations are taken from their papers and scaled in Timeloop/Accelergy without released models.
  • standard math Offset encoding terms are computed with negligible cost
    Section III-D decomposes the signed dot product into four terms; the digital compensation terms are assumed not to dominate energy.

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Cite this review

Pith. "Pith review of You Only Charge Once 2.0 : A End-to-End Analog Computing-in-Memory Architecture with Reconfigurable Switched Capacitors." pith.science (2026). https://pith.science/paper/CMXUMNP3

@misc{pith2026260811116,
  author       = {Pith},
  title        = {Pith review of: You Only Charge Once 2.0 : A End-to-End Analog Computing-in-Memory Architecture with Reconfigurable Switched Capacitors},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/CMXUMNP3}},
  note         = {Machine review of arXiv:2608.11116}
}
read the original abstract

Analog Computing-in-Memory (ACiM) accelerates deep neural networks by keeping weights inside memory arrays and executing dot products in the analog domain. However, modern ACiM accelerators are often limited by the "ADC wall": analog-to-digital converters consume a large fraction of energy and area, while bit-sliced execution repeatedly invokes these converters. Existing designs reduce this cost with low-resolution readout or time multiplexing, but they either lose output fidelity or introduce serialization overhead. Charge-CIM addresses this bottleneck by using switched-capacitor charge redistribution as a unified computing and conversion substrate. The same capacitor fabric performs input conversion, analog MAC, weighted shift-and-add, and readout quantization, reducing both standalone converter overhead and intermediate ADC invocations. A differential readout path further combines paired partial sums during ADC quantization, providing a highly compact and energy-efficient solution for array integration. With dataflow architecture support, we evaluated Charge-CIM on a suite of DNN benchmarks, from CNNs to Transformer models, and experimental results show that Charge-CIM reduces ADC energy by 91.7% under our evaluation setup and improves energy efficiency by 2.7x and throughput by 2.0x compared to the state-of-the-art charge-domain CIM accelerator.

Figures

Figures reproduced from arXiv: 2608.11116 by the authors.

Figure 1
Figure 1. (Left) Conceptual diagram of a charge-domain Compute-in-Memory [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. Overview of CiM mapping strategies and ADC overhead. (a) Bit slicing for MAC operations. (b) Matrix slicing for large-scale algorithms. (c) Energy [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 4
Figure 4. Details of the core computing circuits, showing the reconfigurable [PITH_FULL_IMAGE:figures/full_fig_p004_4.png] view at source ↗
Figures from the paper (11 more)
Figure 5
Figure 5. Figure 5: Six-phase operation of the proposed charge-based multi-bit VMM and [PITH_FULL_IMAGE:figures/full_fig_p005_5.png]
Figure 7
Figure 7. Figure 7: Hierarchical architecture of the proposed Charge-CIM accelerator: (a) chip, (b) tile, (c) IMA, (d) macro and MCC, (e) six-phase MCC operation, and [PITH_FULL_IMAGE:figures/full_fig_p006_7.png]
Figure 8
Figure 8. Figure 8: MCC operation wave and residual settling error. [PITH_FULL_IMAGE:figures/full_fig_p006_8.png]
Figure 10
Figure 10. Figure 10: Layer-wise producer–consumer dataflow with stationary weights/KV [PITH_FULL_IMAGE:figures/full_fig_p007_10.png]
Figure 11
Figure 11. Figure 11: Post-layout implementation used for circuit simulation: (a) full macro [PITH_FULL_IMAGE:figures/full_fig_p008_11.png]
Figure 12
Figure 12. Figure 12: Evaluation of Charge-CIM accuracy and robustness: (a) embedded [PITH_FULL_IMAGE:figures/full_fig_p009_12.png]
Figure 13
Figure 13. Figure 13: Energy efficiency and throughput normalized to RAELLA across nine DNN models. Cambricon-CIM achieves geometric means of 2.26 [PITH_FULL_IMAGE:figures/full_fig_p010_13.png]
Figure 14
Figure 14. Figure 14: Energy breakdown of RAELLA, Cambricon-CIM (CamCIM), and [PITH_FULL_IMAGE:figures/full_fig_p010_14.png]
Figure 15
Figure 15. Figure 15: Area and power breakdown. E. Power and Area Breakdown [PITH_FULL_IMAGE:figures/full_fig_p010_15.png]
Figure 18
Figure 18. Figure 18: DNN and LLM inference robustness under analog CIM non [PITH_FULL_IMAGE:figures/full_fig_p011_18.png]
Figure 17
Figure 17. Figure 17: Post-layout robustness evaluation of Charge-CIM: (a) supply-voltage [PITH_FULL_IMAGE:figures/full_fig_p011_17.png]

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Pith tools

Reviewed August 12, 2026 · model on record in the stance chip above.