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GENIE-ASI: Generative Instruction and Executable Code for Analog Subcircuit Identification

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arxiv 2508.19393 v1 pith:COL7QNRI submitted 2025-08-26 cs.AR cs.LG

classification cs.ARcs.LG
keywords analoggenie-asisubcircuitdesignf1-scoreidentificationautomationbenchmark
verification ladder T0 review T1 audit T2 compute T3 formal
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Analog subcircuit identification is a core task in analog design, essential for simulation, sizing, and layout. Traditional methods often require extensive human expertise, rule-based encoding, or large labeled datasets. To address these challenges, we propose GENIE-ASI, the first training-free, large language model (LLM)-based methodology for analog subcircuit identification. GENIE-ASI operates in two phases: it first uses in-context learning to derive natural language instructions from a few demonstration examples, then translates these into executable Python code to identify subcircuits in unseen SPICE netlists. In addition, to evaluate LLM-based approaches systematically, we introduce a new benchmark composed of operational amplifier netlists (op-amps) that cover a wide range of subcircuit variants. Experimental results on the proposed benchmark show that GENIE-ASI matches rule-based performance on simple structures (F1-score = 1.0), remains competitive on moderate abstractions (F1-score = 0.81), and shows potential even on complex subcircuits (F1-score = 0.31). These findings demonstrate that LLMs can serve as adaptable, general-purpose tools in analog design automation, opening new research directions for foundation model applications in analog design automation.

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  1. NEMESIS: NEtlist-Driven Modeling and Equation Synthesis with Inversion-Aware SPICE Anchoring

    cs.AR 2026-07 conditional novelty 6.5 of 10

    NEMESIS generates SPICE-verified OTA performance equations from netlist plus schematic via multimodal LLM generation, RAG, and iterative SPICE repair, with <7% average error and ~4622× post-convergence speedup on five...

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