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REVIEW 2 major objections 5 minor 37 references

NEMESIS: NEtlist-Driven Modeling and Equation Synthesis with Inversion-Aware SPICE Anchoring

T0 review · 2 major / 5 minor · reviewed 2026-07-11 · grok-4.5

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Pith's one-line read An LLM framework turns OTA netlists and schematics into SPICE-verified performance equations that stay under 7% error and evaluate thousands of times faster than full SPICE.

desk verdict Clean, usable OTA equation pipeline: multimodal LLM + graph RAG + gm/ID sizing + SPICE repair; the integration is real, the theory is not new, and the range claim is empirical. read the letter →

arxiv 2607.05657 v1 pith:CPTHU6AA submitted 2026-07-06 cs.AR

Subhadip Ghosh , Ramesh Harjani , Sachin S. Sapatnekar This is my paper · ORCID
classification cs.AR
keywords OTAmodelinglargelanguagemodelsSPICEverificationgm/IDsizingequationsynthesismultimodalcircuitunderstandinganalogdesignautomation
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

Designers of operational transconductance amplifiers face a standing tradeoff: hand-derived analytical equations are fast and readable but often inaccurate in modern processes, while repeated SPICE runs are accurate but too slow for large design-space search. NEMESIS claims to close that gap for OTAs by feeding a multimodal LLM both the SPICE netlist and the schematic image, first extracting circuit primitives, then writing explicit device-level equations for the usual performance metrics. Those equations are checked against SPICE at a carefully chosen gm/ID bias point and repaired until they pass a relative-error threshold; once they pass, they remain accurate across the full intended bias range. On five topologies of increasing difficulty in a commercial 65 nm process the resulting equations average under 7% error relative to SPICE and evaluate roughly 4600 times faster than the full testbench suite. A sympathetic reader cares because the same models can be dropped into either an automatic optimizer or a manual design loop, giving both speed and circuit insight without forcing a permanent choice between the two.

What carries the argument

The SPICE-guided repair loop of the Equation Agent: equations are generated once, evaluated against SPICE at a LUT-instantiated gm/ID operating point, and only the failing metrics are locally revised until every metric falls below a relative-error threshold; the same equations are then re-checked across the full assigned gm/ID ranges.

What would settle it

Take any of the five OTA topologies, re-size it at several points near the extremes of the assigned gm/ID ranges that were not used in the original repair, re-extract the operating-point parameters, and check whether any metric’s relative error against SPICE exceeds the claimed 7% average (or the 15% repair threshold); a consistent exceedance would falsify the claim that the repaired equations remain valid across the full bias neighborhood.

Watch

Extended reading notes

Core claim

NEMESIS shows that a single pretrained multimodal LLM, guided by primitive recognition, retrieval of previously verified similar OTAs, and a SPICE-anchored repair loop that respects gm/ID inversion ranges, can generate device-level performance equations for five OTA topologies that stay within 7% average relative error of full SPICE across application-specific bias ranges while delivering post-convergence evaluation speedups of roughly 4600 times.

Load-bearing premise

That equations repaired only at one selected bias point (and, if needed, midpoints of any failing sub-ranges) stay accurate over the whole intended gm/ID range without further structural change—an observation reported for the five tested OTAs rather than a general guarantee.

Editorial extensions

If this is right

  • Once an OTA topology has been through NEMESIS, every subsequent sizing or bias-point evaluation inside an optimizer can replace the full DC/AC/TRAN suite with a single operating-point extraction plus equation evaluation.
  • Manual designers obtain explicit, device-traceable expressions that still track SPICE, so they can see which transistors dominate gain, poles, or slew rate without re-running SPICE at every trial size.
  • Equation memory grows with each successful topology, so later, more complex OTAs start closer to the correct form and need fewer repair iterations.
  • The same workflow can be re-run under a tighter error threshold (e.g., 5%) when higher fidelity is required, trading a modest increase in repair iterations for lower residual error.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • The same primitive-plus-repair pattern could be applied to other fixed-topology analog blocks (comparators, LDOs, bandgaps) whose metrics also admit compact small-signal or large-signal expressions.
  • Because the final equations remain human-readable, they could serve as a natural interface between an LLM-based topology generator and a classical sizing engine, letting topology search stay symbolic while sizing stays numerical.
  • If the secondary mid-range repair step is rarely needed, a practical system could cache only the primary-point equations and treat range-wide accuracy as a cheap post-check rather than a full second optimization loop.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

2 major / 5 minor

Summary. NEMESIS is a multimodal LLM framework that, given an OTA SPICE netlist and schematic image, identifies circuit primitives, generates device-level performance equations (optionally seeded by RAG over an equation memory of structurally similar prior OTAs), assigns primitive-level gm/ID targets and ranges via an estimator agent, sizes devices from precharacterized LUTs, and iteratively repairs only failing equations against HSPICE references until a relative-error threshold is met. On five OTA topologies of increasing complexity in a commercial 65 nm PDK, the final equations achieve average relative error below 7 % across the assigned gm/ID bias ranges (Tables III–IV) and deliver a post-convergence evaluation speedup of roughly 4226–5184 imes versus the full DC/AC/TRAN testbench suite (Table V), while remaining interpretable at the device/node level.

Significance. If the reported accuracy and speedup hold, NEMESIS supplies a practical bridge between hand-crafted analytical models and black-box SPICE evaluation for OTA design-space exploration and manual insight. Strengths include explicit SPICE anchoring of every accepted equation, progressive validation from simple to hard topologies, ablations on multimodal input / retrieval / threshold (Fig. 7, Table VI), open-source release of prompts and scripts, and concrete demonstration that repaired equations remain traceable to small-signal device contributions (Fig. 6). These elements make the work immediately usable by both automated optimizers and human designers, provided the fixed-topology assumption and one-time construction cost are respected.

major comments (2)
  1. [Section III-C / Table IV] Section III-C (and the supporting statement in II-D) reports that equations repaired only at the selected gm/ID point (plus mid-points of any failed sub-ranges) required “no additional repair” over the full application-specific ranges; Table IV then shows mean errors still <7 %. This empirical observation is load-bearing for the abstract claim of accuracy “across biasing ranges.” A short failure-mode analysis—e.g., how far the ranges can be extended before structural terms must change, or results on one additional topology/PDK—would convert the observation into a more robust claim.
  2. [Table III / Section III-D] Table III shows that several metrics (SR+, ICMRmin, BW3dB, UGF) still require 30–44 repair iterations on OTA-2/OTA-3 even after the final average error falls below 7 %. Because each iteration invokes an LLM call (reported 30 s–2 min), the one-time construction cost is non-negligible. The paper should quantify total wall-clock construction time for the five OTAs and discuss whether the iteration counts remain acceptable for larger or more nonlinear circuits; otherwise the practicality claim for repeated DSE is only partially supported.
minor comments (5)
  1. [Title] Title and running header contain an extraneous space (“E quation”); fix for consistency.
  2. [Figure 4] Figure 4 trajectories are informative but the y-axis scale and iteration markers make it hard to judge absolute error magnitude at a glance; consider a log-scale inset or explicit final-error annotation.
  3. [Section II-A] The similarity score (Section II-A) uses λ = 0.6 without sensitivity data; a one-sentence note on robustness to λ would help reproducibility.
  4. [Table V / Abstract] Table V reports speedups to three significant figures while the abstract rounds to ~4622×; align the rounding convention.
  5. [Section III-A] The open-source URL is given; confirm that the repository snapshot matching the paper’s GPT-5.2 prompts and 65 nm LUT scripts will remain frozen for reproducibility.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: LLM-generated equations are accepted only after independent SPICE mismatch checks on the same sized netlist; progressive equation memory reuses prior verified results without tautology.

full rationale

NEMESIS derives candidate performance equations via multimodal LLM prompting (netlist + schematic + optional RAG), then accepts or repairs them solely by comparing equation predictions to external HSPICE references (DC/AC/TRAN testbenches plus .op extraction) under a relative-error threshold. The repair loop is driven by measured discrepancy on the instantiated circuit, not by redefining the target metric as the model output. Equation-memory retrieval seeds later topologies from earlier SPICE-verified equations of simpler OTAs; this is progressive reuse of independently checked results, not a self-definitional loop or fitted-input-as-prediction. gm/ID LUT sizing supplies physically plausible operating points for verification but does not fit the symbolic equations themselves. Ablations and range sweeps confirm accuracy remains SPICE-grounded. No uniqueness theorems, ansatz smuggling, or renaming of known results appear. The central claims (sub-7% average relative error over assigned gm/ID ranges and post-convergence speedup) rest on external SPICE benchmarks and are therefore non-circular.

Assumptions & free parameters 4 free parameters · 5 assumptions · 2 invented entities

The central claim is empirical engineering: LLM-generated equations can be repaired until they match SPICE within a chosen relative-error budget on fixed OTA topologies. Load-bearing choices are the acceptance threshold ε, similarity weight λ, LLM temperature, the gm/ID estimator’s discrete targets/ranges, and the assumption that SPICE testbenches plus .op parameters are the ground truth for the metrics in Table I. No new physical entities are postulated; the framework and equation memory are software constructs.

free parameters (4)
  • relative error threshold ε = 15% (default); also tested at 5%
    Repair stops when equation vs SPICE relative error falls below ε; default ε=15% (Section III-A). Directly controls when equations are accepted and how many iterations run.
  • graph similarity weight λ = 0.6
    Balances WL-hash Jaccard vs motif cosine similarity for equation-memory retrieval (Section II-A).
  • LLM temperature = 0.2
    Sampling temperature for GPT-5.2 generation/repair (Section III-A).
  • primitive-level gm/ID targets and ranges = LLM-chosen per primitive (example: DP gmid=16 range [14,18])
    Assigned by the Estimator Agent (e.g., Fig. 2 for OTA-2) and used both for LUT sizing and for defining the bias neighborhood over which accuracy is claimed.
assumptions (5)
  • domain assumption HSPICE DC/AC/TRAN testbenches on the sized netlist are the ground-truth reference for the metrics in Table I.
    All PASS/FAIL decisions and reported errors are defined relative to these SPICE runs (Section II-D).
  • domain assumption The gm/ID methodology and precharacterized LUTs map inversion level and current to physically plausible W/L in saturation for the target PDK.
    Used to instantiate circuits for verification without manual sizing (Section II-C; cites Jespers/Murmann).
  • domain assumption A pretrained multimodal LLM (GPT-5.2) can identify primitives and propose/repair device-level equations when constrained to netlist instances and LUT symbols, without task-specific fine-tuning.
    Stated as a design choice in the introduction and implemented throughout Section II-B.
  • ad hoc to paper Topology is fixed; only sizing/bias within that topology is modeled.
    Explicit limitation in Section IV; equations are not claimed to transfer across topology changes.
  • domain assumption Standard small-signal/device parameters (gm, gds, gmb, capacitances, etc.) extracted from .op are sufficient inputs for the executable metric equations.
    Equation form m = f_m(x, p.op, p_passive) in Section II-B.
invented entities (2)
  • NEMESIS multimodal equation-generation and SPICE-repair pipeline independent evidence
    purpose: Organize primitive identification, RAG, gm/ID estimation, and iterative equation repair into one OTA modeling framework.
    The system is the paper’s main artifact; independent evidence is the open-source repo and reported SPICE comparisons, not an external physical discovery.
  • Equation memory with bipartite netlist graphs, motif vectors, and WL hashes
    purpose: Retrieve SPICE-verified equations from structurally similar prior OTAs to initialize harder topologies.
    Software data structure introduced in Section II-A; usefulness shown by ablation (repair iterations drop with retrieval) but not a new physical object.

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Cite this review

Pith. "Pith review of NEMESIS: NEtlist-Driven Modeling and Equation Synthesis with Inversion-Aware SPICE Anchoring." pith.science (2026). https://pith.science/paper/CPTHU6AA

@misc{pith2026260705657,
  author       = {Pith},
  title        = {Pith review of: NEMESIS: NEtlist-Driven Modeling and Equation Synthesis with Inversion-Aware SPICE Anchoring},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/CPTHU6AA}},
  note         = {Machine review of arXiv:2607.05657}
}
read the original abstract

This work presents NEMESIS, a multimodal framework for operational transconductance amplifier (OTA) design using large language models (LLMs). NEMESIS strikes a balance between fast, approximate analytical models vs. accurate, computationally expensive SPICE evaluations. Given an OTA netlist and schematic, NEMESIS first identifies circuit primitives and then generates progressively more accurate performance equations. The framework begins with equations retrieved from the prior invocations of NEMESIS to structurally similar OTAs, if available; otherwise, it uses the LLM to derive the initial equations directly from the circuit input. These equations are iteratively refined via a SPICE-based repair loop. In a commercial 65nm PDK, NEMESIS is demonstrated on five OTA topologies, producing SPICE-verified equations across biasing ranges with <7% average relative error and a post-convergence evaluation speedup of ~4622x over full SPICE-based evaluation.

Figures

Figures reproduced from arXiv: 2607.05657 by the authors.

Figure 1
Figure 1. Overview of the proposed NEMESIS framework for automated OTA performance modeling. [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. OTA-2 schematic and sample gm/ID-estimator output. instance names and sizes, preserves external pins as anchor nets to enforce connectivity-driven matching. For each graph, NEMESIS generates a compact structural signature consisting of a motif vector (capturing coarse block-level composition, e.g., shared-gate mirrors and device counts) and a two-iteration Weisfeiler-Lehman (WL) [33] refinement hash (capturing lo￾ca… view at source ↗
Figure 3
Figure 3. Abbreviated prompt templates used in NEMESIS: (a) equation [PITH_FULL_IMAGE:figures/full_fig_p003_3.png] view at source ↗
Figures from the paper (4 more)
Figure 4
Figure 4. Figure 4: Error trajectories across equation repair iterations for OTA-2 for (a) [PITH_FULL_IMAGE:figures/full_fig_p004_4.png]
Figure 5
Figure 5. Figure 5: Accuracy of the converged equations for OTA-2 across representative [PITH_FULL_IMAGE:figures/full_fig_p005_5.png]
Figure 7
Figure 7. Figure 7: Primitive-device mappings predicted by the LLM for OTA-2 under [PITH_FULL_IMAGE:figures/full_fig_p006_7.png]
Figure 6
Figure 6. Figure 6: Evolution of the OTA-2 DC-gain equation across repair iterations 1 [PITH_FULL_IMAGE:figures/full_fig_p006_6.png]

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