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Techniques for combining fast local decoders with global decoders under circuit-level noise

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arxiv 2208.01178 v2 pith:CXNR4BBA submitted 2022-08-02 quant-ph

classification quant-ph
keywords localdecodersverticaldecoderglobalpairssyndromecircuit-level
verification ladder T0 review T1 audit T2 compute T3 formal
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Implementing algorithms on a fault-tolerant quantum computer will require fast decoding throughput and latency times to prevent an exponential increase in buffer times between the applications of gates. In this work we begin by quantifying these requirements. We then introduce the construction of local neural network (NN) decoders using three-dimensional convolutions. These local decoders are adapted to circuit-level noise and can be applied to surface code volumes of arbitrary size. Their application removes errors arising from a certain number of faults, which serves to substantially reduce the syndrome density. Remaining errors can then be corrected by a global decoder, such as Blossom or Union Find, with their implementation significantly accelerated due to the reduced syndrome density. However, in the circuit-level setting, the corrections applied by the local decoder introduce many vertical pairs of highlighted vertices. To obtain a low syndrome density in the presence of vertical pairs, we consider a strategy of performing a syndrome collapse which removes many vertical pairs and reduces the size of the decoding graph used by the global decoder. We also consider a strategy of performing a vertical cleanup, which consists of removing all local vertical pairs prior to implementing the global decoder. Lastly, we estimate the cost of implementing our local decoders on Field Programmable Gate Arrays (FPGAs).

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Cited by 1 Pith paper

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score. Full citation record

  1. Synchronization for Fault-Tolerant Quantum Computers

    quant-ph 2025-06 conditional novelty 5.0 of 10

    Active and Hybrid synchronization policies cut logical error rates by up to 2.4x and 3.4x compared to passive waiting, by distributing idle time across syndrome generation rounds.

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