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Pangu Ultra MoE: How to Train Your Big MoE on Ascend NPUs

T0 review · 4 major / 7 minor · reviewed 2026-08-15 · deepseek-v4-flash

Pith's one-line read A 718-billion-parameter mixture-of-experts model can be trained on Ascend NPUs at 30.0% model FLOPs utilization, with benchmark scores comparable to DeepSeek R1.

desk verdict A credible industrial recipe for training a 718B MoE on Ascend NPUs, but the headline 30% MFU is unauditable without the FLOPs formula and the simulator re-validation on the final model is in-sample. read the letter →

arxiv 2505.04519 v1 pith:D5BVIOYI submitted 2025-05-07 cs.CL

classification cs.CL
keywords MixtureofExpertsAscendNPUmodelFLOPsutilizationexpertparallelismloadbalancingsimulation-basedarchitecturesearchmemoryoptimizationlargelanguagetraining
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper is a system-and-architecture recipe for training a near-trillion-parameter mixture-of-experts language model on Ascend NPUs rather than on GPU clusters. It claims that careful model-shape selection guided by a hardware-aware simulator, together with communication, memory, and load-balancing optimizations, lets a 718-billion-parameter MoE reach 30.0% model FLOPs utilization on 6K Ascend NPUs while producing benchmark scores comparable to DeepSeek R1. The central assertion is that the sparse-model efficiency promised by MoE can be materialized on a non-NVIDIA accelerator stack. If true, it means the practical ceiling on large-model training is not set by the choice of accelerator vendor, and that simulation can replace much of the expensive trial-and-error in choosing model configurations.

What carries the argument

The load-bearing machinery is a two-part design loop. First, a bottom-up simulator models operator throughput, communication, memory, and overlaps on Ascend 910B hardware, validated to 88.9% and 90.1% accuracy on two training runs, and is used to prune a search space of about 10,000 architectures down to the Pangu Ultra MoE configuration. Second, the system-side optimizations turn that configuration into a working 6K-NPU run: hierarchical EP all-to-all communication (a global inter-node AllGather followed by an intra-node All-to-All exchange) to cut inter-node traffic, an adaptive pipe overlap schedule that hides forward/backward communication behind computation, fine-grained recomputation plus tensor swapping to manage activation memory, fused operators, and a planner/executor pair that predicts expert load and physically moves experts across devices. These mechanisms jointly convert sparse-model dynamic routing from a throughput tax into a recovered efficiency gain.

What would settle it

Take the paper's own reported numbers—718B total parameters, roughly 39B activated per token, and 1.46M tokens per second—and recompute the FLOPs used per second, then divide by the number of Ascend NPUs times their peak floating-point throughput; if the resulting 30.0% MFU only holds under a lenient FLOPs formula, the comparison to prior MFU reports fails. Independently, rerunning the evaluation suite with a public harness against officially published DeepSeek R1 scores would settle whether the benchmark parity is real.

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Extended reading notes

Core claim

The paper's central discovery is a repeatable training recipe for large sparse MoE models on Ascend NPUs. It combines simulation-based architecture search that screens roughly 10,000 candidate configurations by predicted throughput and selects 61 layers, hidden size 7680, 256 routed experts plus one shared expert, MLA attention, and a specific 5D parallelism plan (TP = 8, PP = 16, VPP = 2, EP = 4), with system optimizations including hierarchical EP all-to-all communication, adaptive pipe overlap, fine-grained recomputation with tensor swapping, and dynamic device-level expert placement. On this basis the authors report training Pangu Ultra MoE, 718B total parameters with 39B activated per token, at 30.0% MFU and 1.46M tokens per second on 6K Ascend NPUs, up from an 18.9% MFU baseline on 4K NPUs, with benchmark performance comparable to or better than DeepSeek R1 on most evaluated tasks, especially medical benchmarks. The paper also reports that dropless routing outperforms drop-and-pad increasingly as models grow, and that an EP-group auxiliary loss strikes the best performance/efficiency balance among sequence-, micro-batch-, EP-group-, and DP-group-level losses.

Load-bearing premise

The single load-bearing premise is that the efficiency metric behind the 30.0% figure (the share of peak computing power actually used) and the benchmark numbers produced by the authors' own testing are counted with the same conventions used for DeepSeek's published figures; if either convention differs, the headline comparison is not apples-to-apples.

Editorial extensions

If this is right

  • If the 30.0% MFU holds under the same accounting used for GPU reports, near-trillion-parameter MoE training is no longer tied to NVIDIA accelerators; other large vendors' stacks can host frontier-scale runs.
  • Simulation-based architecture search at 85-90% accuracy can substitute for much full-scale hyperparameter experimentation, so future model/hardware co-design can be done before hardware exists in quantity.
  • Dropless routing with device-level expert placement is preferable to token dropping at scale: with capacity factor 1.5, the 718B model dropped 8% of tokens versus 6% for the 20B model, meaning token dropping is increasingly harmful as models grow.
  • The EP-group auxiliary loss offers a middle ground between sequence-level and global-level balancing, yielding near-global-level loss with lower communication cost.
  • The reported system optimizations cumulatively raise MFU by 58.7% over baseline, implying similar headroom may exist on other under-optimized stacks for MoE training.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • Editorial extension: because the paper never states the FLOPs formula behind MFU, a reader who re-derives efficiency from the stated 1.46M tokens per second, 718B parameters, and the Ascend peak compute could get a different number; a standardized formula would be needed for a fair cross-vendor comparison.
  • Editorial extension: the hierarchical all-to-all scheme and dynamic expert placement are developed for training, but the same mechanisms should carry over to MoE inference on the same hardware, where routing is still dynamic and memory is tighter.
  • Editorial extension: the simulator's 85-90% accuracy suggests the architecture-search workflow itself is portable; other accelerator vendors could run the same screening on their own compute-to-memory ratios, and the prediction that larger hidden sizes fit compute-heavy chips is directly testable.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

4 major / 7 minor

Summary. This paper reports the design and training of Pangu Ultra MoE, a 718B-parameter Mixture-of-Experts language model with 61 layers, hidden size 7680, 256 routed experts, top-8 routing, a shared expert, MLA, and MTP, trained on 6K Ascend NPUs. The authors propose a simulation-based architecture search over approximately 10,000 configurations and select a model with 61 layers, hidden size 7680, 256 experts, using parallelism TP=8, PP=16, VPP=2, EP=4, MBS=2. On the systems side, they describe hierarchical EP All-to-All communication, adaptive pipe overlap, fine-grained recomputation, tensor swapping, and a planner/executor for dynamic expert placement. They report 30.0% MFU and 1.46M tokens/sec on 6K Ascend NPUs, a 58.7% relative MFU improvement over their baseline, and benchmark results across C-Eval, MMLU, AIME, GPQA, LiveCodeBench, and medical datasets that are said to be comparable to DeepSeek R1. They also include analyses of auxiliary-loss granularity, drop-and-pad versus dropless training, expert specialization, router scale, and expert co-activation.

Significance. If the reported efficiency and benchmark numbers hold, the paper is a significant engineering contribution: it provides one of the first public accounts of training a near-trillion-parameter MoE to near-frontier quality on a non-NVIDIA accelerator stack, and the system techniques (hierarchical EP all-to-all, adaptive pipe overlap, fine-grained recomputation, tensor swapping, dynamic placement) are described in enough detail to be useful to other systems groups. The authors are also transparent about simulation-accuracy limits and mark which benchmark scores were obtained by their own testing, which is more candid than many industrial reports. However, the paper does not ship code, checkpoints, training logs, or a full data recipe, and the central quantitative claims currently rest on undisclosed accounting choices: no MFU formula, no global batch size or sequence length, no evaluation protocol for asterisked benchmark scores, and an in-sample simulation validation. The methodology is sound in outline, but the headline numbers are not yet auditable.

major comments (4)
  1. [Section 1 / Section 5.1 / Table 5] The paper never states the FLOPs-per-token formula used to compute MFU. For the reported 718B MoE with 256 routed experts, top-8 activation, one shared expert, MLA, MTP, fine-grained recomputation, tensor swapping, and dynamic expert placement, the distinction between counting only activated routed-expert GEMMs and counting attention/shared-expert/MTP/recomputation FLOPs can shift the MFU by tens of percent. Section 5.1 does not report the global batch size, sequence length, total training tokens, or the peak FLOPs of the Ascend 910B used in the denominator, so the TPS value of 1.46M cannot be used to reconstruct or audit the 30.0% figure. In addition, Table 5's cumulative '58.7% relative increase' is presented as a baseline of 1, while the Section 1 baseline of 18.9% MFU is stated on 4K NPUs; because the cluster size and parallelism differ, the relative improvement is not a controlled comparison. The authors should disclose the exact MFU formula and all experimental inputs, or the central claim is not comparable to MFU numbers reported for GPU baselines.
  2. [Section 2.3 / Table 1] The simulation is validated on the final model it selected. The second row of Table 1 uses 'Pangu Ultra MoE Training' itself, giving 90.1% accuracy; this is an in-sample check and does not establish that the simulator correctly ranks the ~10,000 candidate configurations or the eight high-throughput models in Figure 4. The first row (4.2B, 128 NPUs) is out-of-sample but uses GQA, 4 experts, and a 6-layer model, so it does not exercise MLA, 256-expert routing, MTP, or the 6K-NPU communication patterns of the target configuration. The architecture-selection claim needs either a held-out validation on at least one additional 718B-class configuration or an explicit analysis of how simulation error varies across the candidate set, for example by comparing predicted versus measured performance of several selected candidates.
  3. [Section 5.2 / Table 6] The comparison to DeepSeek R1 is not fully auditable. Several DeepSeek numbers are asterisked as obtained by the authors' own testing, but the paper gives no evaluation protocol: prompt templates, decoding settings (temperature, top-p, sampling), answer extraction, number of runs or seeds, and contamination checks are all absent. Without these details and without run-to-run variability, differences such as AIME2024 81.3 versus 79.8 and LiveCodeBench 64.3 versus 65.9 cannot be distinguished from evaluation noise. The claim that Pangu Ultra MoE is comparable to DeepSeek R1 should be treated as provisional; the authors should provide a complete evaluation protocol or rely on official reported scores.
  4. [Section 4.4 / Table 5] The paper claims that dynamic expert placement gives a 'relative 10% improvement in MFU' and reduces device-level load imbalance by 80%-90%, but no ablation or measurement description is provided, and Table 5's cumulative MFU improvements do not list this item. If the Table 5 baseline is the same 18.9% MFU from Section 1, the arithmetic 18.9% x 1.587 = 30.0% already accounts for the full headline gain; adding a further 10% relative improvement would exceed the reported MFU unless it is already concealed inside one of Table 5's categories or the baselines differ. The authors should reconcile these numbers and provide an explicit ablation for the dynamic placement mechanism.
minor comments (7)
  1. [Page 1] The header 'Huawei Proprietary - Restricted Distribution' appears on a public arXiv submission; if the report is intended to be public, this marking should be removed or explained.
  2. [Section 2.4] There are typos: 'memomy access bandwidth' should be 'memory access bandwidth', and 'This prevents any bottleneck from happening' is ungrammatical and should be rephrased.
  3. [Section 4.1] The term 'Tiling = 4' in the CoC discussion is undefined; please explain what tiling denotes and how the 4x reduction in communication exposure is measured.
  4. [Figure 9 / Section 4.5] 'Umpermute' should be 'Unpermute' in the Figure 9 legend and in Section 4.5.
  5. [Section 5.2] The benchmark list in the opening paragraph omits C-SimpleQA, although it appears in Table 6; add it to the list.
  6. [Figure 12] The figure axis labels are rendered as '/uni...' escape sequences in the submitted text; the figure needs to be regenerated so expert IDs are legible.
  7. [References] References [58] and [59] duplicate the same Qwen2.5 technical report, and [51] and [52] duplicate the Megatron-LM citation; consolidate to avoid confusion.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: the post-hoc 718B simulator 're-validation' is in-sample but not load-bearing, and the undisclosed MFU formula is an auditability issue, not a circular derivation.

full rationale

The paper is an empirical systems report, not a derivation from first principles. The architecture-selection chain is: pilot MoE experiments on a 20B model choose expert granularity and shared-expert structure; a simulator built from operator-level hardware measurements and explicit hardware specifications searches roughly 10,000 configurations and selects Model 7; the chosen parallelism is then implemented and measured on 6K Ascend NPUs. The headline 30.0% MFU and 1.46M TPS are measured or engineering-derived quantities on the implemented system, not outputs produced by the simulator itself. The closest candidate for circularity is Section 2.3 and Table 1, where the simulator is 're-validated' on the 718B model after training: the paper explicitly says 'The end-to-end time in the second experiment with 718B experiments is acquired after actual Pangu Ultra MoE training on 6K NPUs, and we carry out simulations afterward to re-validate our simulation method.' This is a post-hoc consistency check, not an out-of-sample prediction, and the forward validation was done on the 4.2B pilot experiment before the architecture search. The 718B agreement therefore does not determine the architecture choice or the MFU claim by construction; it is in-sample evidence of simulator accuracy. The undisclosed FLOPs-per-token formula behind the 30.0% MFU and the asterisked self-run DeepSeek scores in Table 6 are auditability and evaluation-protocol concerns, not cases where a claimed result is equal to its inputs by definition. No load-bearing self-citation, imported uniqueness theorem, or renamed known result was found; the only same-author citation ([60], Pangu Ultra dense) supports an existing fused-operator implementation and is not load-bearing. The derivation chain is therefore self-contained: each quantitative claim is either measured, produced by a simulator with explicitly stated inputs, or validated against a separate small-scale experiment before use.

Assumptions & free parameters 6 free parameters · 4 assumptions · 0 invented entities

The central claim relies on the Ascend NPU hardware model encoded in the simulator, the accuracy of that simulator (validated to 85-90% on two runs), and the assumption that benchmark comparisons and the undisclosed MFU flop-counting convention are standard and fair. The model hyperparameters and parallelism settings are selected by simulation and hand-tuning rather than derived from first principles.

free parameters (6)
  • Model architecture hyperparameters (61 layers, hidden 7680, 256 routed experts, expert intermediate 2048, top-8… = 61/7680/256/2048/8/1
    Selected by the simulator to maximize predicted training and inference throughput on Ascend NPUs; the pilot experiments (expert granularity, shared experts) only fix the MoE structure, not these final numbers.
  • Parallelism strategy (TP=8, PP=16, VPP=2, EP=4, MBS=2) = TP=8, PP=16, VPP=2, EP=4, MBS=2, Tiling=4
    Chosen by the same simulator as the best combination for the selected architecture; several other 5D parallelism combinations were evaluated but not reported in detail.
  • Auxiliary loss coefficient alpha = 1e-4 to 1e-2 tested; final value for Pangu Ultra MoE not stated
    The paper compares alpha=1e-2 and 1e-4 for the 20B baseline and says EP-group is a good compromise, but the final alpha used for the 718B model is not reported.
  • Expert capacity factor = 1.5
    Used in the drop-and-pad comparison experiments (Section 3.2); the capacity factor is a hand-set hyperparameter that directly affects the reported token drop rates.
  • Planner hyperparameters for dynamic expert placement = not specified
    Sliding window size, placement switch interval, and coefficient of variation threshold are not given, yet they determine the claimed 10% relative MFU improvement from load balancing.
  • Memory policy choices (MLA KV-only vs QKV recompute, permute recompute, prob swap) = KV-only recompute, permute recompute, activation recompute, prob swapping
    The combination is stated in Section 4.3 but the memory budgets and thresholds that trigger each policy are not reported, making the policy a hand-tuned configuration.
assumptions (4)
  • domain assumption The simulator's operator-level model of Ascend 910B compute, memory, and network behavior is accurate enough for comparative architecture search.
    Invoked in Section 2.2 and validated to 88.9% and 90.1% on two runs (Table 1). The in-sample validation on the final model limits independent support.
  • domain assumption MFU is computed with a standard FLOPs accounting convention that is comparable to DeepSeek's reported MFU.
    MFU 30.0% is the headline efficiency claim (Section 1, Section 4.5), but the exact FLOPs formula, sequence length, and batch size used in the MFU calculation are not disclosed.
  • domain assumption The evaluation protocol, including author-run benchmark results (marked with asterisks), is consistent across all compared models.
    Table 6 mixes publicly reported scores with the authors' own testing; if prompting or sampling settings differ, the 'comparable to DeepSeek R1' claim could be an artifact.
  • domain assumption The internal training data quality controls and the 3:1 reasoning to non-reasoning sample ratio are sufficient for the model to reach the reported capability.
    Data composition is described only at a high level in Section 5.1, yet the model's benchmark performance depends entirely on it.

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Cite this review

Pith. "Pith review of Pangu Ultra MoE: How to Train Your Big MoE on Ascend NPUs." pith.science (2026). https://pith.science/paper/D5BVIOYI

@misc{pith2026250504519,
  author       = {Pith},
  title        = {Pith review of: Pangu Ultra MoE: How to Train Your Big MoE on Ascend NPUs},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/D5BVIOYI}},
  note         = {Machine review of arXiv:2505.04519}
}
read the original abstract

Sparse large language models (LLMs) with Mixture of Experts (MoE) and close to a trillion parameters are dominating the realm of most capable language models. However, the massive model scale poses significant challenges for the underlying software and hardware systems. In this paper, we aim to uncover a recipe to harness such scale on Ascend NPUs. The key goals are better usage of the computing resources under the dynamic sparse model structures and materializing the expected performance gain on the actual hardware. To select model configurations suitable for Ascend NPUs without repeatedly running the expensive experiments, we leverage simulation to compare the trade-off of various model hyperparameters. This study led to Pangu Ultra MoE, a sparse LLM with 718 billion parameters, and we conducted experiments on the model to verify the simulation results. On the system side, we dig into Expert Parallelism to optimize the communication between NPU devices to reduce the synchronization overhead. We also optimize the memory efficiency within the devices to further reduce the parameter and activation management overhead. In the end, we achieve an MFU of 30.0% when training Pangu Ultra MoE, with performance comparable to that of DeepSeek R1, on 6K Ascend NPUs, and demonstrate that the Ascend system is capable of harnessing all the training stages of the state-of-the-art language models. Extensive experiments indicate that our recipe can lead to efficient training of large-scale sparse language models with MoE. We also study the behaviors of such models for future reference.

Figures

Figures reproduced from arXiv: 2505.04519 by the authors.

Figure 1
Figure 1. Experts number ablation. Since increasing [PITH_FULL_IMAGE:figures/full_fig_p003_1.png] view at source ↗
Figure 3
Figure 3. Simulation workflow for LLM performance and optimal search. [PITH_FULL_IMAGE:figures/full_fig_p004_3.png] view at source ↗
Figure 4
Figure 4. Simulated model normalized throughput of training and inference. [PITH_FULL_IMAGE:figures/full_fig_p006_4.png] view at source ↗
Figures from the paper (10 more)
Figure 5
Figure 5. Figure 5: Comparison of the load balancing auxiliary loss and cross-entropy loss during training across [PITH_FULL_IMAGE:figures/full_fig_p008_5.png]
Figure 6
Figure 6. Figure 6: Training loss curves for the 20B MoE models trained with drop-and-pad and dropless methods. [PITH_FULL_IMAGE:figures/full_fig_p009_6.png]
Figure 7
Figure 7. Figure 7: Analysis of token drop rates. During drop-and-pad training with the expert capacity factor set to [PITH_FULL_IMAGE:figures/full_fig_p010_7.png]
Figure 8
Figure 8. Figure 8: Virtual pipeline stage partitioning matrix (2-row VPP Stages [PITH_FULL_IMAGE:figures/full_fig_p011_8.png]
Figure 9
Figure 9. Figure 9: MoE operator streams. Subfigure (a) shows the forward pass. Subfigure (b) shows the backward [PITH_FULL_IMAGE:figures/full_fig_p013_9.png]
Figure 10
Figure 10. Figure 10: Comparison between before host_bound optimization and after. Compared with permute1, GMM [PITH_FULL_IMAGE:figures/full_fig_p013_10.png]
Figure 11
Figure 11. Figure 11: Overview of dynamic device-level load balancing mechanism. The planner generates and periodi [PITH_FULL_IMAGE:figures/full_fig_p015_11.png]
Figure 12
Figure 12. Figure 12: Expert specialization pattern of Pangu Ultra MoE. Each subgraph represents the token distribution [PITH_FULL_IMAGE:figures/full_fig_p018_12.png]
Figure 13
Figure 13. Figure 13: The outputs of routed and shared experts. We display the outputs after the 30th layer for better [PITH_FULL_IMAGE:figures/full_fig_p019_13.png]
Figure 14
Figure 14. Figure 14: Co-activation among experts in nine layers on a random 0.5% of the C4 validation data. We display [PITH_FULL_IMAGE:figures/full_fig_p019_14.png]

Discussion (0). Continue with ORCID to comment.

Forward citations

Cited by 3 Pith papers

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score. Full citation record

  1. MoX: Efficient MoE Routing on Direct-Connect Topologies

    cs.NI 2026-07 conditional novelty 6.0 of 10

    Static, demand-oblivious routing with token-aware multicast trees and precomputed per-link weights brings MoE traffic on direct-connect fabrics close to ideal switch performance.

  2. DTop-p MoE: Sparsity-Controlled Dynamic Top-p MoE for Foundation Model Pre-training

    cs.AI 2025-12 conditional novelty 6.0 of 10

    A PI-controller-tuned, layerwise-normalized Top-p router trains sparse MoE models that beat Top-k at matched average activated-expert count.

  3. Serving Large Language Models on Huawei CloudMatrix384

    cs.DC 2025-06 conditional novelty 6.0 of 10

    CloudMatrix384 with CloudMatrix-Infer reports prefill 6,688 tokens/s per NPU and decode 1,943 tokens/s per NPU on DeepSeek-R1, exceeding published NVIDIA-based efficiencies.

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    ** 灵活性与动态性**: - **DFT** :测试模式固定,需通过ATE(自动测试设备)执行,测试向量在制造阶段固化。 - **SSI** :支持动态配置测试策略,可在系统运行过程中实时调整测试参数,甚至结合软件驱动实现自适应测试。 典型应用场景: - **复杂SoC的运维监测**:通过SSI实时监控芯片温度、电压、关键信号路径的完整性。 - **车载/航天电子**:在恶劣环境中检测瞬时故障并触发自修复机制。 - **数据中心芯片**:周期性扫描系统状态,预防因老化或软错误导致的宕机。 总结:SSI是DFT的补充而非替代,两者结合可覆盖芯片全生...

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    ** 核心思想** SSI是在系统级(如芯片集成到终端设备后)通过软件驱动或固件实现的测试模式,利用系统自身资源(如处 理器、内存、接口等)执行自测试功能,通常用于运行时故障检测或周期性健康监测。

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    ** 特点** - **动态测试**:在系统运行过程中实时或按需触发测试,支持在线故障诊断(如老化监测、功能异常检测)。- **软件驱动**:依赖软件算法或固件指令生成测试用例,无需额外硬件电路(或仅需少量硬件配合)。- **系统级 覆盖**:可 测试芯片与其他系统组 件(如传感器、电源管理模块)的交互 问题,而不仅是芯片内部结构。- **灵活性高**:测试逻辑可通 过软件更新,适配不同应用场景。

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    ** 典型应用** - 汽车电子中的功能安全(ISO 26262 )要求系统实时自检。- 数据中心芯片的运行时健康监测(如温度、电压 异常检测)。- 物联网设备的低功耗周期性自测试。 **DFT (Design for Test )**

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    ** 核心思想** DFT是在芯片设计 阶段插入硬件结构(如扫描链、BIST电路), 以提升制造缺陷的检测效率,主要用于芯片 量产后的**静态测试**(如ATE测试)。

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    ** 特点** - ** 硬件依赖**:需额外设计测试电路(如扫描触发器、MBIST控制器),占用芯片面积和功耗。- **制造阶段测 试**:主要用于芯片出厂前的缺陷筛查(如stuck-at 故障、延迟故障)。- **结构化测试**:针对预定义的故障模型生成测试向 量,覆盖晶体管级或门级缺陷。- **高覆盖率**:通过自动化工具(如ATPG)生成测试模式,确保缺陷检测率。

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    ** 典型应用** - 芯片量产时的自动化测试(ATE)。- 扫描链测试(Scan Test)、内存BIST(Built-In Self-Test )。- 边界扫描 (Boundary Scan )用于PCB互联测试。 **SSI 与DFT的关键区别** | **维度** | **SSI** | **DFT** | | **测试阶段** | 系统运行时(动态测试)| 芯片制造后(静态测试)| | **实现方式** | 软件/固件驱动,利用系统资源| 硬件结构设计(扫描链、BIST等)| | **测试目标** |功能异常、环境干扰、老化问题|制造缺陷...

Pith tools

Reviewed August 15, 2026 · model on record in the stance chip above.