Design of an FPGA-Based Neutral Atom Rearrangement Accelerator for Quantum Computing

Amr Elsharkawy; Dirk Stober; Jonas Winklmann; Martin Schulz; Xiaorang Guo

REVIEW 3 major objections 5 minor 1 cited by

Design of an FPGA-Based Neutral Atom Rearrangement Accelerator for Quantum Computing

T0 review · 3 major / 5 minor · reviewed 2026-08-12 · deepseek-v4-flash

Challenge this review Re-run · record.json Download PDF Read on arXiv ↗ Review JSON

Pith's one-line read An FPGA-based quadrant rearrangement algorithm computes a defect-free atom-array schedule in about one microsecond, 54× faster than a CPU and 300× faster than a prior FPGA/ARM design.

desk verdict Genuine first FPGA-PL rearrangement scheduler with a clever quadrant-flip trick and plausibly fast 1 µs schedule generation; the four-iteration correctness claim is asserted, not measured, so the headline number is contingent. read the letter →

arxiv 2411.12401 v1 pith:DGC5HGOR submitted 2024-11-19 quant-ph cs.ARcs.ET

Xiaorang Guo , Jonas Winklmann , Dirk Stober , Amr Elsharkawy , Martin Schulz This is my paper · ORCID

classification quant-phcs.ARcs.ET

keywords neutralatomquantumcomputingrearrangementdefect-freearrayFPGAacceleratorquadrant-basedalgorithmshiftkernelhigh-levelsynthesiscontrolsystem

verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

Neutral-atom quantum computers must first compress a stochastically half-filled trap array into a smaller, defect-free array; this paper claims that the computation generating that compression schedule can be finished in about one microsecond on an FPGA. The proposed quadrant-based rearrangement method splits the array into four quadrants, flips each so the target region becomes a corner, and applies one uniform row/column shift schedule to all quadrants in parallel. On a 250 MHz FPGA the design completes the schedule that turns a 50×50 loaded array into a 30×30 compact target array in approximately 1.0 µs, about 54× faster than a CPU implementation and about 300× faster than a prior FPGA/ARM approach. If this holds, schedule analysis stops being a multi-microsecond bottleneck in the control loop, and all control stages—imaging, detection, sorting, pulse generation—can live on one FPGA close to the quantum hardware.

What carries the argument

The load-bearing object is the Shift Kernel, a pipelined engine that represents each row of a quadrant as a bit vector, inspects one bit per clock cycle, and records shift commands; by feeding the same kernel column-wise, it handles vertical moves with identical logic. Around it sit the quadrant-flip preprocessing stage and the Row Combination Unit, which merges the four quadrants' shift commands into one schedule that satisfies the acousto-optic deflector's rule that simultaneous moves must share a direction and step size. The identity that makes this work is that compressing atoms toward the array center is equivalent to compressing each flipped quadrant into its own corner, so a single schedule serves all four quadrants.

What would settle it

A concrete falsifier: find one 50×50 occupancy pattern at 50% filling on which the four-iteration QRM leaves a hole in the central 30×30 target, or whose merged shift commands cannot be executed simultaneously by the acousto-optic deflector.

Watch

Extended reading notes

Core claim

The paper's central claim is that atom compression has a quadrant symmetry that turns a sequential row-then-column sorting problem into four independent, identical subproblems. After flipping each quadrant so its target corner sits at the bottom left, one shift kernel fills all four quadrants, and the recorded moves are flipped back to global coordinates. The hardware consequence is a four-way parallel pipeline: each quadrant runs the same fully pipelined bit-vector shift engine, inspecting one row per clock cycle, then merging its shift commands with the other quadrants into a schedule that respects the acousto-optic deflector's constraint that simultaneous moves share a direction and step size. According to the authors, four iterations of row-wise and column-wise shifts are sufficient to fill the target area, and the complete schedule for a 50×50-to-30×30 rearrangement takes about 1.0 µs at 250 MHz.

Load-bearing premise

The load-bearing premise is that four fixed row-wise/column-wise shift iterations turn any randomly 50%-loaded 50×50 array into a defect-free 30×30 target array; if some loading needs a fifth iteration, the 1.0 µs claim does not apply.

Editorial extensions

If this is right

If the 1.0 µs figure holds, the rearrangement-schedule step is no longer the dominant latency in neutral-atom control, so the repetition rate can be set by imaging and physical atom movement rather than by sorting logic.
The measured scaling from 0.8 µs at 10×10 to 1.9 µs at 90×90 means the accelerator stays useful as arrays grow toward hundreds of atoms.
With LUT and FF usage below about 6.5% even at 90×90, the same FPGA has room to host atom detection, pulse generation, and other control blocks, supporting an all-FPGA control architecture.
The 54× and 300× speedups indicate that quadrant-level parallelism and the hardware pipeline reinforce each other, rather than one being bought at the expense of the other.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

Extending beyond the paper: the fixed four-iteration count is an unproven heuristic, so a worst-case search over random 50% loadings could find inputs that require more iterations and hence more than 1.0 µs.
Extending beyond the paper: the reported time covers only schedule analysis; physical atom movement through the acousto-optic deflector is not included, so the end-to-end cycle time remains larger and the accelerator's real gain is removing the analysis term from that cycle.
Extending beyond the paper: the same quadrant-flip strategy could in principle be ported to GPUs or ASICs, though the shift-register mapping makes FPGAs a natural fit; a comparative study would show whether the speedup is inherent to the algorithm or specific to this hardware implementation.
Extending beyond the paper: validating the algorithm on real fluorescence images rather than random bitmaps would test whether the 50% occupancy model and the four-iteration heuristic survive actual detection noise.

Share X Bluesky LinkedIn Reddit HN

Signed reviews

No signed human review yet.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Desk Editor's Note

read the letter

Quick read on arXiv:2411.12401 (Guo et al., FPGA-based rearrangement accelerator): genuine engineering contribution with a validation gap at its center. The quadrant-flip symmetry trick is the right idea — split the array, flip each quadrant so all four compress into the same corner, then run one uniform shift kernel per quadrant in parallel. I believe the claim that this is the first rearrangement scheduler in FPGA programmable logic; Tetris runs on an ARM core and the others are CPU algorithms. The pipeline is coherent, resource use stays under 7% LUT/FF even at 90×90, and 1.0 µs of schedule generation at 250 MHz is plausible for a fully pipelined bit-serial design. It is also a direct measurement: no fitted parameters, no circularity.

The load-bearing soft spot is the iteration count. Section V-B states "four iterations were used to complete the entire process, ensuring successful rearrangement," with no success-rate data, no final occupancy check, no trial count, and no argument that two row-wise plus two column-wise compaction passes close all holes under p=0.5 binomial loading. This is checkable — they already generate random inputs — so the absence is conspicuous. And it matters quantitatively: latency scales roughly linearly with iterations, so a worst case needing six or eight passes would shrink the headline 1 µs and the 54×/300× speedups proportionally. I do not think the architecture collapses — the quadrant trick and pipelined kernel survive any honest iteration count — but the specific number is hostage to an unverified assumption.

Two smaller things. The 300× comparison is against Tetris on an ARM core at a different clock; it is disclosed, but it is apples-to-oranges. And the random-matrix inputs are fine for timing but are not a substitute for the missing correctness check. Also keep in mind the paper only measures schedule analysis, not the full imaging-to-movement loop; the practical impact is bounded by the rest of that loop.

Who benefits: people building neutral atom control systems and FPGA/HPC quantum integration. It deserves a serious referee — the required fix is a straightforward experiment (success rate versus iteration count over many random trials, plus a bound or fallback), and the contribution is real. Send it out.

Referee Report

3 major / 5 minor

Summary. The paper proposes a quadrant-based rearrangement method (QRM) for neutral atom arrays, in which the initial array is split into four quadrants, each flipped so that the target region is at a common corner, and a unified row-wise/column-wise shift schedule is applied in parallel. The authors implement the schedule analysis on the programmable logic of a Zynq RFSoC FPGA using high-level synthesis, with a fully pipelined shift kernel and four parallel quadrant processing paths. They report that a 50x50 stochastic array with 50% loading can be rearranged into a 30x30 compact target array in approximately 1.0 µs, claiming about 54x speedup over a CPU implementation of the same algorithm and about 300x speedup over a prior FPGA-based Tetris implementation. The paper also presents scaling and resource-utilization results for array sizes from 10x10 to 90x90.

Significance. If the reported latency and correctness hold, the work is a useful step toward closing the feedback loop in neutral atom quantum computers, where image-based defect detection and rearrangement scheduling are currently a bottleneck. The central idea of exploiting quadrant symmetry to reuse one schedule four times is elegant and genuinely hardware-friendly, and the FPGA implementation appears to be a real, synthesizable design with direct timing measurements rather than a simulation. The authors are also honest about the scope: they focus on schedule-generation time, not on the physical atom movement time, and they compare against prior work on different platforms. The main significance depends on whether the generated schedules are actually defect-free for the stochastic inputs claimed, which is exactly where the manuscript is currently weakest.

major comments (3)

[Section V-B] The load-bearing claim that four iterations always produce a defect-free target array is asserted but not demonstrated. The sentence 'In our experiment, four iterations were used to complete the entire process, ensuring successful rearrangement' is the only support for the 1.0 µs result, yet no formal argument, no success-rate statistic, no trial count, and no inspection of the final array occupancy are provided. Since QRM is a heuristic row/column compression in which each pass moves atoms a limited distance toward a corner, it is not self-evident that four passes fill the 30x30 target for every 50%-loading 50x50 input; if some inputs leave holes, the reported 1.0 µs schedule is not a valid rearrangement and the speedup claim collapses. The authors should either prove an invariant that guarantees completion in four iterations or measure the success rate over many random matrices and report the worst case, the mean, and the variance.
[Section V-B and Fig. 7] The performance evaluation reports no variance or trial counts, and the headline speedups compare implementations on different platforms. The 54x CPU-vs-FPGA comparison at 50x50 is meaningful because both run the same QRM algorithm, but the 300x figure against Tetris is an ARM-core implementation on an FPGA, not a programmable-logic implementation, so the speedup conflates algorithmic improvement with platform differences. The paper should report at least the number of repeated trials and the spread of the timing measurements, and should state clearly which comparisons are apples-to-apples and which are indicative only.
[Section III-B and Section IV-C] The correctness of the generated movement schedule is not fully specified. The equivalence between 'compressing all atoms to the center' and 'compressing each flipped quadrant toward its corner' is intuitive but not proven, and the shift kernel description does not show that the emitted movements are collision-free and compatible with the AOD row/column constraint described in Section II-B. In particular, the manual-control mechanism and the merging of shift commands across quadrants are described at the level of examples, without a formal rule that prevents two atoms from being assigned to the same target trap or crossing paths. A precise algorithmic specification, or at least a post-processing check that the final schedule maps distinct atoms to distinct target sites, would make the central claim verifiable.

minor comments (5)

[Section II-A] The heading 'Neural Atom Basics' appears to be a typo and should read 'Neutral Atom Basics.'
[Fig. 7(b)] The x-axis label 'Tetris[3]' is inconsistent with the text, where Tetris is reference [6]; this should be corrected.
[Abstract and Section I] The abstract claims 'the first hardware acceleration work for atom rearrangement,' while the introduction more cautiously claims 'the first work to implement the rearrangement algorithm on the PL part of an FPGA'; the wording should be aligned to avoid overstating the novelty.
[Section IV-C] The signal referred to as 'sen' is written as '~s_en' in Fig. 6; using one name consistently would improve clarity.
[Section V-B] The sentence 'the latency of our design is not directly dependent on the target area we aim to fill' is followed by a statement that the number of movements increases with target size; the relationship between latency, target size, and iteration count should be stated more precisely, since a reader might otherwise find the two sentences contradictory.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: the reported latencies are direct measurements, and the four-iteration success assumption is an unvalidated algorithmic setting, not a fitted input or self-citation-derived claim.

full rationale

The paper's central claims are measured execution times of an FPGA implementation of QRM. The algorithm is defined from input bit matrices, and the reported 1.0 µs, 54×, and 300× speedups are comparisons of measured latencies, not predictions derived from fitted parameters. No equation or parameter is fitted to the target result. The only load-bearing auxiliary assumption, that four row-wise/column-wise iterations always produce a defect-free target array, is asserted in Section V-B ("In our experiment, four iterations were used to complete the entire process, ensuring successful rearrangement") without proof or measured success rate. This is a correctness/validation gap, not circularity: the iteration count is an input setting, and the paper does not define successful rearrangement in terms of four iterations or derive the count from the target result. Self-citations and related-work comparisons are not load-bearing to the latency measurement. Thus no circular step is present, and the analysis is self-contained with respect to the measured speedup claim.

Assumptions & free parameters 1 free parameters · 4 assumptions · 0 invented entities

The central claim rests on the hardware constraint model, the quadrant symmetry assumption, and an unvalidated fixed iteration count. None are fitted parameters, but the iteration count is an unstated tuning choice.

free parameters (1)

Iteration count = 4
The paper states four iterations complete the rearrangement but gives no derivation or statistical validation that this suffices for all stochastic 50% loadings and target sizes. The latency result depends on this fixed count.

assumptions (4)

domain assumption A 2D-AOD can generate only a set of rows and columns, producing cross traps at every intersection; simultaneous atom moves require the same direction and step size.
Stated in Section II-B as the hardware constraint that motivates the shift kernel and merge rules.
ad hoc to paper Compressing all atoms to the array center is equivalent to compressing each flipped quadrant toward its corner, so one uniform schedule can be reused four times.
Section III-B introduces quadrant splitting and flipping without a proof that the merged schedules are equivalent to a valid global rearrangement.
ad hoc to paper Four row-wise and column-wise iterations fill the target area for any 50% random loading.
Section V-B asserts this without presenting success-rate data.
domain assumption Randomly generated matrices have the same distribution as real fluorescence detection output and are sufficient for latency analysis.
Section V-A states this assumption when justifying the use of random input data.

how reviews work

0 comments

Cite this review

Pith. "Pith review of Design of an FPGA-Based Neutral Atom Rearrangement Accelerator for Quantum Computing." pith.science (2026). https://pith.science/paper/DGC5HGOR

@misc{pith2026241112401,
  author       = {Pith},
  title        = {Pith review of: Design of an FPGA-Based Neutral Atom Rearrangement Accelerator for Quantum Computing},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/DGC5HGOR}},
  note         = {Machine review of arXiv:2411.12401}
}

abstract

Neutral atoms have emerged as a promising technology for implementing quantum computers due to their scalability and long coherence times. However, the execution frequency of neutral atom quantum computers is constrained by image processing procedures, particularly the assembly of defect-free atom arrays, which is a crucial step in preparing qubits (atoms) for execution. To optimize this assembly process, we propose a novel quadrant-based rearrangement algorithm that employs a divide-and-conquer strategy and also enables the simultaneous movement of multiple atoms, even across different columns and rows. We implement the algorithm on FPGA to handle each quadrant independently (hardware-level optimization) while maximizing parallelization. To the best of our knowledge, this is the first hardware acceleration work for atom rearrangement, and it significantly reduces the processing time. This achievement also contributes to the ongoing efforts of tightly integrating quantum accelerators into High-Performance Computing (HPC) systems. Tested on a Zynq RFSoC FPGA at 250 MHz, our hardware implementation is able to complete the rearrangement process of a 30$\times$30 compact target array, derived from a 50$\times$50 initial loaded array, in approximately 1.0 $\mu s$. Compared to a comparable CPU implementation and to state-of-the-art FPGA work, we achieved about 54$\times$ and 300$\times$ speedups in the rearrangement analysis time, respectively. Additionally, the FPGA-based acceleration demonstrates good scalability, allowing for seamless adaptation to varying sizes of the atom array, which makes this algorithm a promising solution for large-scale quantum systems.

Figures

Figures reproduced from arXiv: 2411.12401 by the authors.

**Figure 2.** Architectures of atom control systems. (a) Current typical system [PITH_FULL_IMAGE:figures/full_fig_p002_2.png] view at source ↗

**Figure 3.** Illustration of the typical rearrangement algorithm. The blue emphasized line indicates the target line for this move step. Arrows represent the atoms [PITH_FULL_IMAGE:figures/full_fig_p003_3.png] view at source ↗

Figures from the paper (5 more)

**Figure 4.** Figure 4: QRM rearrangement schedule. By splitting the atom array and performing specific flip operations, we can apply a unified rearrangement method to each [PITH_FULL_IMAGE:figures/full_fig_p003_4.png]

**Figure 5.** Figure 5: Complete dataflow of the HLS-accelerated rearrangement module. [PITH_FULL_IMAGE:figures/full_fig_p004_5.png]

**Figure 6.** Figure 6: Row-wise to column-wise shift process for a [PITH_FULL_IMAGE:figures/full_fig_p005_6.png]

**Figure 7.** Figure 7: (a) Comparison of QRM execution time between CPU and FPGA, [PITH_FULL_IMAGE:figures/full_fig_p005_7.png]

**Figure 8.** Figure 8: FPGA resource utilization (percentage) when varying the size of atom [PITH_FULL_IMAGE:figures/full_fig_p006_8.png]

Discussion (0). Continue with ORCID to comment.

Forward citations

Cited by 1 Pith paper

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score. Full citation record

RISC-Q: A Generator for Real-Time Quantum Control System-on-Chips Compatible with RISC-V
cs.AR 2025-05 conditional novelty 6.0 of 10

RISC-Q is an open-source, parameterizable generator for building RISC-V-based quantum control chips, demonstrated on a ZCU216 board at 500 MHz with 16 DACs.

Reference graph

Works this paper leans on

14 extracted references · 9 canonical work pages · cited by 1 Pith paper

[1]

Scaling qubit readout with hardware efficient machine learning architectures,

S. Maurya, C. N. Mude, W. D. Oliver, B. Lienhard, and S. Tannu, “Scaling qubit readout with hardware efficient machine learning architectures,” in Proceedings of the 50th Annual International Symposium on Computer Architecture , ser. ISCA ’23. New York, NY , USA: Association for Computing Machinery, 2023. [Online]. Available: https://doi.org/10.1145/35793...

arXiv 2023
[2]

Hisep-q: A highly scalable and efficient quantum control processor for superconducting qubits,

X. Guo, K. Qin, and M. Schulz, “Hisep-q: A highly scalable and efficient quantum control processor for superconducting qubits,” in 2023 IEEE 41st International Conference on Computer Design (ICCD) , 2023, pp. 86–93

work page 2023
[3]

Defect-free assembly of 2d clusters of more than 100 single-atom quantum systems,

D. Ohl de Mello, D. Sch ¨affner, J. Werkmann, T. Preuschoff, L. Kohfahl, M. Schlosser, and G. Birkl, “Defect-free assembly of 2d clusters of more than 100 single-atom quantum systems,” Phys. Rev. Lett. , vol. 122, p. 203601, May 2019. [Online]. Available: https://link.aps.org/doi/10.1103/PhysRevLett.122.203601

doi:10.1103/physrevlett.122.203601 2019
[4]

Collisional blockade in microscopic optical dipole traps,

N. Schlosser, G. Reymond, and P. Grangier, “Collisional blockade in microscopic optical dipole traps,” Phys. Rev. Lett. , vol. 89, p. 023005, Jun 2002. [Online]. Available: https://link.aps.org/doi/10.1103/ PhysRevLett.89.023005

work page 2002
[5]

Quantum simulation and computing with rydberg-interacting qubits,

M. Morgado and S. Whitlock, “Quantum simulation and computing with rydberg-interacting qubits,” AVS Quantum Science, vol. 3, no. 2, 2021

work page 2021
[6]

Accelerating the assembly of defect-free atomic arrays with maximum parallelisms,

S. Wang, W. Zhang, T. Zhang, S. Mei, Y . Wang, J. Hu, and W. Chen, “Accelerating the assembly of defect-free atomic arrays with maximum parallelisms,” Phys. Rev. Appl., vol. 19, p. 054032, May 2023. [Online]. Available: https://link.aps.org/doi/10.1103/PhysRevApplied.19.054032

doi:10.1103/physrevapplied.19.054032 2023
[7]

A concise review of rydberg atom based quantum computation and quantum simulation,

X. Wu, X. Liang, Y . Tian, F. Yang, C. Chen, Y .-C. Liu, M. K. Tey, and L. You, “A concise review of rydberg atom based quantum computation and quantum simulation,” Chinese Physics B , vol. 30, no. 2, p. 020305, 2021

work page 2021
[8]

Quantum phases of matter on a 256-atom programmable quantum simulator,

S. Ebadi, T. T. Wang, H. Levine, A. Keesling, G. Semeghini, A. Omran, D. Bluvstein, R. Samajdar, H. Pichler, W. W. Ho et al., “Quantum phases of matter on a 256-atom programmable quantum simulator,” Nature, vol. 595, no. 7866, pp. 227–232, 2021

work page 2021

Show all 14 references

[9]

Parallel assembly of arbitrary defect-free atom arrays with a multitweezer algorithm,

W. Tian, W. J. Wee, A. Qu, B. J. M. Lim, P. R. Datla, V . P. W. Koh, and H. Loh, “Parallel assembly of arbitrary defect-free atom arrays with a multitweezer algorithm,” Phys. Rev. Appl., vol. 19, p. 034048, Mar 2023. [Online]. Available: https: //link.aps.org/doi/10.1103/PhysR...

2023 doi
[10]

Coaxpress standard gains endorsement from the aia and emva to achieve global standardization status,

J. I. I. Association, “Coaxpress standard gains endorsement from the aia and emva to achieve global standardization status,” https://www.coaxpress.com/wp-content/uploads/2016/05/CoaXPress- Official-World-Standard 30Mar11.pdf

2016
[11]

Fast quantum gates for neutral atoms,

D. Jaksch, J. I. Cirac, P. Zoller, S. L. Rolston, R. C ˆot´e, and M. D. Lukin, “Fast quantum gates for neutral atoms,” Phys. Rev. Lett. , vol. 85, pp. 2208–2211, Sep 2000. [Online]. Available: https://link.aps.org/doi/10.1103/PhysRevLett.85.2208

doi
[12]

Rydberg-mediated entanglement in a two-dimensional neutral atom qubit array,

T. Graham, M. Kwon, B. Grinkemeyer, Z. Marra, X. Jiang, M. Lichtman, Y . Sun, M. Ebert, and M. Saffman, “Rydberg-mediated entanglement in a two-dimensional neutral atom qubit array,” Physical review letters, vol. 123, no. 23, p. 230501, 2019

2019
[13]

An atom-by-atom assembler of defect-free arbitrary two-dimensional atomic arrays,

D. Barredo, S. de L ´es´eleuc, V . Lienhard, T. Lahaye, and A. Browaeys, “An atom-by-atom assembler of defect-free arbitrary two-dimensional atomic arrays,” Science, vol. 354, no. 6315, pp. 1021–1023, 2016. [Online]. Available: https://www.science.org/doi/abs/10.1126/science.aah3778

2016 doi
[14]

Zcu216 evaluation board user guide (ug1390),

AMD, “Zcu216 evaluation board user guide (ug1390),” https://docs.amd.com/r/en-US/ug1390-zcu216-eval-bd/Introduction, 2023

2023

Pith tools

Reviewed August 12, 2026 · model on record in the stance chip above.

[1] [1]

Scaling qubit readout with hardware efficient machine learning architectures,

S. Maurya, C. N. Mude, W. D. Oliver, B. Lienhard, and S. Tannu, “Scaling qubit readout with hardware efficient machine learning architectures,” in Proceedings of the 50th Annual International Symposium on Computer Architecture , ser. ISCA ’23. New York, NY , USA: Association for Computing Machinery, 2023. [Online]. Available: https://doi.org/10.1145/35793...

arXiv 2023

[2] [2]

Hisep-q: A highly scalable and efficient quantum control processor for superconducting qubits,

X. Guo, K. Qin, and M. Schulz, “Hisep-q: A highly scalable and efficient quantum control processor for superconducting qubits,” in 2023 IEEE 41st International Conference on Computer Design (ICCD) , 2023, pp. 86–93

work page 2023

[3] [3]

Defect-free assembly of 2d clusters of more than 100 single-atom quantum systems,

D. Ohl de Mello, D. Sch ¨affner, J. Werkmann, T. Preuschoff, L. Kohfahl, M. Schlosser, and G. Birkl, “Defect-free assembly of 2d clusters of more than 100 single-atom quantum systems,” Phys. Rev. Lett. , vol. 122, p. 203601, May 2019. [Online]. Available: https://link.aps.org/doi/10.1103/PhysRevLett.122.203601

doi:10.1103/physrevlett.122.203601 2019

[4] [4]

Collisional blockade in microscopic optical dipole traps,

N. Schlosser, G. Reymond, and P. Grangier, “Collisional blockade in microscopic optical dipole traps,” Phys. Rev. Lett. , vol. 89, p. 023005, Jun 2002. [Online]. Available: https://link.aps.org/doi/10.1103/ PhysRevLett.89.023005

work page 2002

[5] [5]

Quantum simulation and computing with rydberg-interacting qubits,

M. Morgado and S. Whitlock, “Quantum simulation and computing with rydberg-interacting qubits,” AVS Quantum Science, vol. 3, no. 2, 2021

work page 2021

[6] [6]

Accelerating the assembly of defect-free atomic arrays with maximum parallelisms,

S. Wang, W. Zhang, T. Zhang, S. Mei, Y . Wang, J. Hu, and W. Chen, “Accelerating the assembly of defect-free atomic arrays with maximum parallelisms,” Phys. Rev. Appl., vol. 19, p. 054032, May 2023. [Online]. Available: https://link.aps.org/doi/10.1103/PhysRevApplied.19.054032

doi:10.1103/physrevapplied.19.054032 2023

[7] [7]

A concise review of rydberg atom based quantum computation and quantum simulation,

X. Wu, X. Liang, Y . Tian, F. Yang, C. Chen, Y .-C. Liu, M. K. Tey, and L. You, “A concise review of rydberg atom based quantum computation and quantum simulation,” Chinese Physics B , vol. 30, no. 2, p. 020305, 2021

work page 2021

[8] [8]

Quantum phases of matter on a 256-atom programmable quantum simulator,

S. Ebadi, T. T. Wang, H. Levine, A. Keesling, G. Semeghini, A. Omran, D. Bluvstein, R. Samajdar, H. Pichler, W. W. Ho et al., “Quantum phases of matter on a 256-atom programmable quantum simulator,” Nature, vol. 595, no. 7866, pp. 227–232, 2021

work page 2021