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Algorithmic Strategies for Sustainable Reuse of Neural Network Accelerators with Permanent Faults

T0 review · 4 major / 5 minor · reviewed 2026-08-11 · deepseek-v4-flash

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Pith's one-line read This paper claims that permanent single stuck-at-bit faults in systolic-array accelerator links and weight registers can be mitigated by scaling, tile rearrangement, and fault-aware fine-tuning, restoring accuracy to near fault-free…

desk verdict The paper's core idea of reusing faulty systolic arrays by integrating the fault into the computation is promising, but the reported recovery for a down-link exponent stuck-at-1 fault directly contradicts its own Table I and methods, so the central evidence is not yet self-consistent. read the letter →

arxiv 2412.16208 v1 pith:DGS5IDV7 submitted 2024-12-17 cs.LG cs.AR

Youssef A. Ait Alama , Sampada Sakpal , Ke Wang , Razvan Bunescu , Avinash Karanth , Ahmed Louri This is my paper · ORCID
classification cs.LGcs.AR
keywords systolicarraystuck-atfaulttoleranceneuralnetworkacceleratorfault-awarefinetuninginvertiblescalinghardwarereusefloating-pointprecision
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper argues that a neural-network accelerator with a permanent stuck-at-bit fault in a link or weight register does not have to be bypassed or discarded. Instead, the faulty value can be incorporated into the computation by scaling and shifting activations and weights, rearranging tile rows and columns, or fine-tuning the network with the fault's exact behavior. The authors build a software simulator of a weight-stationary systolic array with fault injection, and show that on fully connected and convolutional networks (MNIST, CIFAR-10, ImageNet) the proposed techniques restore accuracy to within a fraction of the fault-free baseline while adding about 17.8% inference latency on average. If the claim holds, damaged accelerators, including ones in satellites or data centers where replacement is costly, could be reused instead of decommissioned, with no hardware modification.

What carries the argument

The load-bearing mechanism is the fault operator, a small function that sets one bit of a floating-point value to its stuck-at value and is placed at the exact location of the fault in a simulator of the systolic array's multiply-accumulate dataflow. IScSh works through a tile-wise scaling identity: scaling each activation tile into the interval $[-c,c]$ and each weight tile into $[-1/d,1/d]$ ensures the faulty exponent bit is uniformly zero on the faulty path, while a bias shift handles sign-bit faults in down links, and every step is invertible so the true output is recovered at the end. ETOps exploits the invariance of matrix multiplication under simultaneous row and column swaps when sign flips are tracked. faFT makes the fault part of the differentiable computation graph so gradients flow through the faulty forward pass, with fine-tuning performed off-device while the fault is replicated during the forward pass. The whole evaluation rests on a fault-injection simulator that mirrors a weight-stationary systolic array's time-stepped partial sums.

What would settle it

Take a network with a non-ReLU activation such as tanh or sigmoid, apply IScSh to a down-link exponent stuck-at-0 fault, and measure test accuracy: if the method depends on scale commuting with the nonlinearity, accuracy should fail to recover. Alternatively, run the pipeline after deliberately misreporting the faulty bit position by one bit; recovery should collapse, demonstrating the dependence on exact BIST localization.

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Extended reading notes

Core claim

The central discovery is that single stuck-at-0 or stuck-at-1 faults in specific bit positions of right links, down links, and weight registers can be neutralized by treating the fault as a fixed constraint on the data passing through it. For exponent-range stuck-at-0 faults, Invertible Scaling and Shifting (IScSh) scales tiles of activations and weights so that every value on the faulty path already has the stuck bit set to the required value, then rescales outputs to recover the original result. For sign-bit faults in weight registers, Elementary Tile Operations (ETOps) swap rows of the weight tile and corresponding columns of the activation tile, or invert a column's signs, so that the element in the faulty register matches the stuck sign, and the output is flipped back afterwards. For the most significant mantissa bits, Fault-Aware Fine Tuning (faFT) inserts the bit-stuck operation into the computation graph and backpropagates through it, letting the weights adapt to the actual faulty behavior. The paper reports that these methods match or very closely approach fault-free accuracy for the covered fault classes across float32, float16, and bfloat16.

Load-bearing premise

The whole recovery pipeline assumes the permanent fault is a single bit stuck at 0 or 1 in a link or weight register, that BIST has located the exact PE, bit position, and stuck value, and that the faulted component's data subsequently flows only through paths the algorithms scale, shift, or fine-tune; a wrong diagnosis, a fault in the nonlinear engine or buffer, or a nonlinearity that is not positively homogeneous would break the recovery.

Editorial extensions

If this is right

  • Accelerators with faults in the covered classes can remain in service, deferring replacement and avoiding decommissioning of whole systems.
  • The mitigation is algorithmic, so it can be deployed on existing systolic-array chips by reusing their normalization, activation, and storage units, adding no silicon area.
  • Fault-aware fine tuning preserves the network's full capacity, unlike approaches that zero out faulty PEs, at the cost of about 17.8% extra inference latency on average.
  • The fault-characterization results give designers a map of which bit positions matter most, so future fault-tolerant training or runtime mitigation can focus on exponent and sign bits rather than the whole register.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • The same 'work with the fault, not around it' principle should extend beyond systolic arrays to other structured datapaths with a fixed, known faulty operator, provided that operator's effect can be inverted or learned around.
  • Because the methods require exact fault diagnosis, a natural next step is coupling them with lightweight online fault monitors so mitigation adapts when a second fault appears or when the diagnosed position is uncertain.
  • The characterization results suggest a testable research program: reduced-precision formats such as bfloat16 appear to add inherent robustness, so combining IScSh and faFT with quantized training might yield even cheaper fault-tolerant inference than the paper's float32 results.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

4 major / 5 minor

Summary. The paper proposes to reuse systolic-array accelerators with permanent single stuck-at-bit faults by integrating the faulty behavior algorithmically instead of bypassing or decommissioning hardware. It introduces a CUDA-accelerated PyTorch simulator (S3A) for weight-stationary systolic arrays and three mitigation techniques: Invertible Scaling and Shifting (IScSh) for a subset of exponent and sign faults, Elementary Tile Operations (ETOps) for weight-register sign faults, and Fault-Aware Fine Tuning (faFT) for the most significant mantissa faults. Results are reported on FCN/MNIST, LeNet/CIFAR-10, and AlexNet/VGG16 on ImageNet across float32, float16, and bfloat16, claiming recovery to near fault-free accuracy with an average 17.8% timing overhead. The paper is best seen as a systematic characterization plus analytically constructed mitigation strategies for a clearly bounded fault class, with the caveat that all evidence is generated from the authors' own simulator rather than hardware.

Significance. If the claims hold, the work is significant for sustainable accelerator reuse: it shows a path to keep faulty PEs operational without dedicated redundant hardware, using only scaling/shifting done in existing nonlinear-engines and buffers. The analytical construction of the scaling factors (not fitted to the test results), the public availability of the S3A code, and the explicit fault-scope tables are strengths. The main limitation is that the evidence is entirely from the authors' simulator, which matches native PyTorch only to about four decimal places on average, and the scope is restricted to single known stuck-at faults in links or weight registers. Within that scope, the results would be a useful reference point for the hardware-fault-tolerance community, but the internal inconsistencies and missing evaluation described below must be resolved before the central claim is credible.

major comments (4)
  1. [Section V, Figure 9 vs. Section IV-A, Table I] The reported VGG16/ImageNet recovery for a down-link fault labeled 'Stuck Bit 1 at Bit Position 14' in bfloat16 (accuracy restored from 0.1% to 72.7% by IScSh) directly contradicts the method definition. In bfloat16, bit 14 is the most significant exponent bit, and Section IV-A derives IScSh only for stuck-at-0 exponent faults, while Table I lists '—' (no mitigation) for down-link stuck-at-1 exponent faults. Either the experimental result is mislabeled or the scope table and derivation are incomplete; this is a load-bearing inconsistency for the paper's headline claim.
  2. [Section IV-A, Table III] IScSh as specified for down-link exponent faults does not guarantee that all exponent bits in the claimed range are cleared. Table III says the down-link exponent stuck-at-0 case scales activations to [-1,1] and weights to [-1/d,1/d], and the text explicitly states that scaling activations by c is not needed for down-link faults. With these bounds, partial sums lie in [-1,1], which only ensures that the most significant exponent bit is 0; a lower exponent bit can still be 1 (e.g., bfloat16 0.75 has bit 13 = 1). A stuck-at-0 fault at such a bit would still corrupt the partial sum. The paper does not report recovery per exponent-bit position for down-link faults, so the claimed coverage of the full exponent range is unsupported.
  3. [Section IV-B, Table I, Section V] ETOps is introduced in Section IV-B and assigned in Table I to weight-register sign faults (both stuck-at-0 and stuck-at-1), but no experimental evaluation of ETOps appears in Section V; Figures 8-11 and Table IV cover only IScSh and faFT. Consequently, the paper's claim of validating three mitigation techniques is not supported for the weight-register sign-fault class, and the reader cannot assess whether ETOps actually preserves accuracy.
  4. [Section IV-C, Table IV] The caption of Table IV says the faFT results are for 'worst faults (down link stuck-at-1)', while the text and table columns describe 'the most significant mantissa bit position'. Because Table I assigns down-link stuck-at-1 exponent faults to '—' and faFT is introduced for mantissa faults, the caption creates ambiguity about which fault class was actually fine-tuned. This should be clarified and made consistent with the fault taxonomy.
minor comments (5)
  1. [Section I, Section IV-A] The introduction states that IScSh addresses 'exponent range and the sign bit', but the body limits sign-bit mitigation to down-link sign faults; the broad wording should be scoped to match Table I.
  2. [Section II] The simulator's limited agreement with native PyTorch is acknowledged, but the paper should state explicitly that all reported accuracy numbers are S3A-relative and not necessarily comparable to native PyTorch results.
  3. [Section IV-B] There is a typo in the row-swapping step: 'matching sing element' should be 'matching sign element'.
  4. [Section V] The word 'respectivly' appears in the text describing Figures 10 and 11 and should be corrected to 'respectively'.
  5. [Table I] For clarity, the table would benefit from a footnote explaining that '—' means no mitigation is proposed for that fault class, and that the VGG16 result in Figure 9 is an exception to this table as currently written.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: the mitigation algorithms are constructive (IScSh, ETOps, faFT) and not fitted to the claimed outputs, though the paper contains an internal inconsistency in its flagship VGG16 recovery example.

full rationale

No circular reduction is exhibited in the paper. IScSh (Section IV-A, Eqs. 1-8) chooses the scaling constant c from the faulty bit position (Eqs. 3-4) and tile max-norms so that values crossing the faulty component already have the stuck-at-0 bit value; this is a constructive design guarantee, not a fitted parameter relabeled as a prediction, and the math is invertible so the original output is recovered algebraically. ETOps (Section IV-B) is an exact sign-correction via row swaps and column inversion, and faFT (Section IV-C) inserts the fault operator into the forward graph and fine-tunes on training data before reporting held-out test accuracy. No load-bearing self-citation or imported uniqueness theorem is used; the cited prior work on BIST and range restriction is not the source of the paper's claimed results. One evidence defect is flagged for completeness: Section V, Figure 9 reports IScSh restoring VGG16 on ImageNet from 0.1% to 72.7% for a down-link fault 'Stuck Bit 1 at Bit Position 14' in bfloat16, but Section IV-A derives IScSh only for exponent stuck-at-0 faults and Table I marks down-link exponent stuck-at-1 as '—' (no mitigation). This internal inconsistency undermines the reliability of that specific flagship result, but it is not a circular reduction: the reported number is neither an equation rewritten as itself nor a fitted parameter renamed as a prediction. Similarly, the fact that Table I's algorithm selection was 'informed by the findings from the characterization experiments' is a methodological limitation, not circularity, because the mitigation techniques themselves are deterministic and their accuracy is measured on held-out test data.

Assumptions & free parameters 1 free parameters · 5 assumptions · 0 invented entities

Most of the paper's load-bearing assumptions are domain assumptions about fault model, detection, and simulator fidelity rather than fitted parameters. The only hand-chosen numbers that affect recovery results are the fine-tuning budgets. The scaling constants c and bias b are analytically derived from the faulty bit position and stuck value, not fitted to data.

free parameters (1)
  • faFT fine-tuning budget (training examples, epochs, batch size) = FCN: 1k/20/64; LeNet: 1k/20/4; AlexNet: 20k/5/64; VGG16: 5k/5/40
    Chosen by hand per model, with early stopping; no sensitivity analysis or seeds reported. The faFT recovery results in Table IV are conditional on these settings.
assumptions (5)
  • domain assumption BIST can detect and localize every stuck-at fault, including its PE, bit position, and stuck-at value, with 100% coverage.
    The paper adopts BIST in Section IV and states proven 100% detection coverage for stuck-at permanent faults. All three mitigation algorithms presuppose exact fault localization.
  • domain assumption Fault model is limited to a single permanent stuck-at bit in a right link, down link, or weight register; all other hardware, especially the nonlinear engines, buffers, and control logic used for scaling and shifting, remains fault-free.
    Section II and III define only right-link, down-link, and weight-register faults; IScSh and ETOps move work into the nonlinear engines and GLB, whose fault-free operation is assumed.
  • domain assumption Activation functions in networks where IScSh is applied are positively homogeneous (ReLU family) so that the c-scaling factor commutes with the nonlinearity.
    Equations 5-8 in Section IV-A compute activations after a c-scaled summation and then rescale; this exactly recovers the un-scaled output only when f(c*x)=c*f(x), which ReLU satisfies and sigmoid or tanh do not. The paper only demonstrates ReLU-based networks.
  • domain assumption The PyTorch/CUDA S3A simulator is a faithful enough model of systolic-array arithmetic; the authors report agreement with PyTorch native multiplication to about four decimal places on average.
    Section II states PyTorch does not guarantee bit-wise IEEE results and that S3A establishes precision to four decimal places on average. All characterization and recovery numbers inherit this approximation.
  • domain assumption The unreleased C++ cycle-accurate simulator accurately estimates inference latency overhead.
    Section V reports an average 17.8% timing overhead from a C++ simulator that is described in one sentence and not released, so the overhead figure cannot be independently reproduced.

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Pith. "Pith review of Algorithmic Strategies for Sustainable Reuse of Neural Network Accelerators with Permanent Faults." pith.science (2026). https://pith.science/paper/DGS5IDV7

@misc{pith2026241216208,
  author       = {Pith},
  title        = {Pith review of: Algorithmic Strategies for Sustainable Reuse of Neural Network Accelerators with Permanent Faults},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/DGS5IDV7}},
  note         = {Machine review of arXiv:2412.16208}
}
read the original abstract

Hardware failures are a growing challenge for machine learning accelerators, many of which are based on systolic arrays. When a permanent hardware failure occurs in a systolic array, existing solutions include localizing and isolating the faulty processing element (PE), using a redundant PE for re-execution, or in some extreme cases decommissioning the entire accelerator for further investigation. In this paper, we propose novel algorithmic approaches that mitigate permanent hardware faults in neural network (NN) accelerators by uniquely integrating the behavior of the faulty component instead of bypassing it. In doing so, we aim for a more sustainable use of the accelerator where faulty hardware is neither bypassed nor discarded, instead being given a second life. We first introduce a CUDA-accelerated systolic array simulator in PyTorch, which enabled us to quantify the impact of permanent faults appearing on links connecting two PEs or in weight registers, where one bit is stuck at 0 or 1 in the float32, float16, or bfloat16 representation. We then propose several algorithmic mitigation techniques for a subset of stuck-at faults, such as Invertible Scaling or Shifting of activations and weights, or fine tuning with the faulty behavior. Notably, the proposed techniques do not require any hardware modification, instead relying on existing components of widely used systolic array based accelerators, such as normalization, activation, and storage units. Extensive experimental evaluations using fully connected and convolutional NNs trained on MNIST, CIFAR-10 and ImageNet show that the proposed fault-tolerant approach matches or gets very close to the original fault-free accuracy.

Figures

Figures reproduced from arXiv: 2412.16208 by the authors.

Figure 1
Figure 1. This figure shows snapshots in time for the fourth and fifth time step [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. Tiled matrix multiplication, where matrix [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 3
Figure 3. IEEE 754 float32 representation of 0.15625. (s, e, m), we can represent the number of bits in each range for the different data types as follows: float32 (1, 8, 23), float16 (1, 5, 10) and bfloat16 (1, 8, 7). Note that since bfloat16 use the same number of bits for the exponent as float32, the two formats represent the same range of values [29]. We quantify the effect of a bit flip in each bit position by its locati… view at source ↗
Figures from the paper (8 more)
Figure 4
Figure 4. Figure 4: This figure shows the average test accuracy after a single stuck bit (SB) fault in a right link (left), down link (middle) and weight register (right) [PITH_FULL_IMAGE:figures/full_fig_p004_4.png]
Figure 5
Figure 5. Figure 5: This figure shows the average test accuracy after a single stuck bit (SB) fault in a right link (left), down link (middle) and weight register (right) across [PITH_FULL_IMAGE:figures/full_fig_p004_5.png]
Figure 6
Figure 6. Figure 6: This figure shows the average test accuracy after a single stuck bit (SB) fault in a right link (left), down link (middle) and weight register (right) [PITH_FULL_IMAGE:figures/full_fig_p004_6.png]
Figure 7
Figure 7. Figure 7: Examples of hardware architectures that the proposed fault-tolerant algorithms can be deployed on. (a) A typical accelerator chip that shows the essential [PITH_FULL_IMAGE:figures/full_fig_p007_7.png]
Figure 8
Figure 8. Figure 8: This figure compares the FCN performance of ISc and IScSh with the worst Fault Injection (FI) accuracies for a single stuck bit (SB) fault occurring [PITH_FULL_IMAGE:figures/full_fig_p009_8.png]
Figure 9
Figure 9. Figure 9: This figure compares the VGG16 performance of ISc and IScSh with the worst Fault Injection (FI) accuracies for a single stuck bit (SB) fault occurring [PITH_FULL_IMAGE:figures/full_fig_p009_9.png]
Figure 10
Figure 10. Figure 10: This figure compares the FCN performance before and after faFT for the worst affected mantissa bit position (BP) due to a stuck bit (SB) fault [PITH_FULL_IMAGE:figures/full_fig_p009_10.png]
Figure 11
Figure 11. Figure 11: This figure compares the VGG16 performance of faFT for a single stuck bit (SB) fault occurring in the most significant mantissa bit positions (BP) [PITH_FULL_IMAGE:figures/full_fig_p009_11.png]

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Pith tools

Reviewed August 11, 2026 · model on record in the stance chip above.