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REVIEW 3 major objections 6 minor 58 references

A CPU+DCU Heterogeneous Parallel Framework for Post-Processing Reconstruction in Quantum Circuit Cutting

T0 review · 3 major / 6 minor · reviewed 2026-07-31 · grok-4.5

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Pith's one-line read A CPU+accelerator sparse reconstruction framework turns circuit-cutting’s classical bottleneck into a scalable HPC dataflow over nonzero-probability states.

desk verdict Solid Songshan systems stack for sparse circuit-cutting reconstruction; the hundred-qubit headline is real for structured cases and thin for hard sparse random workloads. read the letter →

arxiv 2607.27947 v1 pith:DICH73GH submitted 2026-07-30 quant-ph cs.DC

Qingqing Jiang , Weidong Liu , Yufu Liu , Ruiqing He , Jiandong Shang , Hengliang Guo , Qiang Chen This is my paper
classification quant-phcs.DC
keywords quantumcircuitcuttingpost-processingreconstructionheterogeneousparallelismsparsestatesCPU+DCUout-of-corestorageMPIredistributionNISQ
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

Quantum circuit cutting lets large circuits run as smaller pieces on limited quantum hardware, but rebuilding the original output distribution can swamp classical machines with computation and memory. This paper argues that the right classical target is not a full dense probability vector and not only a few high-probability samples, but the set of nonzero-probability basis states recovered from subcircuit measurements. It builds that reconstruction as a distributed CPU-plus-accelerator pipeline: integer high/low-word indices for states wider than 64 bits, owner-based MPI routing so identical states merge on one process, device kernels for batched expansion and Kronecker-style probability updates, and a three-level store that spills overflow from device and host memory to disk. On a supercomputer, the method keeps high fidelity, reports large speedups versus serial and CPU-only baselines, and finishes hundred-qubit structured and stressed random instances that in-memory-only runs cannot. A sympathetic reader cares because cutting’s practical limit is often classical post-processing, not only qubit count—and this shows an HPC-shaped path past that wall.

What carries the argument

Sparse nonzero-probability reconstruction as a multi-level cooperative dataflow: a unified high/low-word integer global basis-state index that drives expansion, SplitMix64 owner routing, MPI redistribution, and merging, paired with a three-level store (device memory for batch kernels, host staging/reduction, out-of-core spill buckets) so intermediate sparse contributions never require a dense full-state vector.

What would settle it

Rerun the same cutting and reconstruction pipeline on a hundred-qubit-class instance using noisy, finite-shot subcircuit data (or force subcircuits with more than two cut points) and check whether fidelity stays high and whether hierarchical storage still completes under the same memory budget; systematic collapse of fidelity or new infeasibility would refute the transfer of the central claim.

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Extended reading notes

Core claim

The authors claim that circuit-cutting post-processing can be made scalable on heterogeneous supercomputers by reconstructing and aggregating only nonzero-probability states as a sparse distributed dataflow, rather than materializing dense 2^n vectors or sampling only high-probability strings. With high/low-word integer indexing, owner-based redistribution, CPU+DCU cooperation, and hierarchical out-of-core storage, their framework maintains high reconstruction fidelity while delivering up to about 259× speedup over optimized serial code on linear-cluster states, up to about 4× over homogeneous CPU-parallel code on random circuits, and completion of hundred-qubit-scale reconstruction tasks.

Load-bearing premise

The reported fidelity and completion results rest on noiseless subcircuit measurement data and on cuttings where each subcircuit has at most two cut points; if real noise fills or corrupts the sparse state set, or richer multi-cut fragments dominate, those claims need not carry over.

Editorial extensions

If this is right

  • Classical post-processing, not only quantum qubit limits, becomes a first-class design constraint for practical circuit cutting on HPC-coupled systems.
  • Sparse nonzero-state management plus out-of-core spilling can finish reconstructions that dense full-state or pure in-memory approaches cannot under fixed host memory.
  • Cutting schemes must be chosen for intermediate-state growth and reconstruction order, not only for fitting subcircuits on quantum devices.
  • As node count grows, further gains depend more on communication, redistribution, and spill I/O than on raw accelerator arithmetic.
  • Hundred-qubit structured cases (e.g., GHZ/BV principal states) become classically reconstructible targets for heterogeneous sparse pipelines under the paper’s regime.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • Hybrid quantum–classical schedulers may need cost models that jointly price cut count, sparse intermediate cardinality, and spill bandwidth, not qubit width alone.
  • If noise densifies outputs, the same stack may need noise-aware pruning or error mitigation before expansion, or sparsity benefits will shrink.
  • Owner-hash load imbalance and Alltoallv volume look like the next engineering ceiling once device kernels are no longer the bottleneck.
  • The approach suggests treating other cut-and-knit classical stages (not only probability reconstruction) as sparse index-keyed reductions on supercomputers.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 6 minor

Summary. This systems paper presents a CPU+DCU heterogeneous framework for classical post-processing in quantum circuit cutting. Rather than materializing a dense 2^n probability vector or returning only high-probability samples, it reconstructs and aggregates the nonzero-probability basis states from subcircuit measurement tables. The design combines MPI owner-based sparse-state routing, DCU-accelerated batched Kronecker expansion, a high/low-word integer index for widths beyond 64 bits, and a three-level device/host/out-of-core storage hierarchy. On Songshan, the authors report up to 259 imes end-to-end speedup versus an optimized serial CPU baseline on linear-cluster states, up to 4× versus homogeneous CPU-parallel execution on random circuits (same node count), ~51% strong-scaling efficiency from 60 to 300 nodes on a 53-qubit random instance, high fidelity on small linear-cluster cases and principal states of 118-qubit GHZ/BV, and successful completion of a 104-qubit random instance only when hierarchical spilling is enabled. Code and data are stated to be public.

Significance. Circuit-cutting post-processing is a genuine classical bottleneck as cut count and sparse intermediate state sets grow, and most prior work emphasizes cut selection, approximate sampling, or algorithm-level sparsity rather than distributed heterogeneous execution of the resulting sparse aggregation workload. The paper’s concrete contributions—unified integer indexing with SplitMix64 owner routing, DCU batch expansion, and cooperative out-of-core storage—are appropriate for TPDS-style systems evaluation and are backed by public code, phase breakdowns, and controlled storage-stress and strong-scaling experiments. If the performance and completion claims hold under the stated scope, the work usefully shows that HPC-oriented sparse reconstruction can extend the classical side of circuit cutting beyond single-node memory limits. The main significance is empirical systems evidence, not a new cutting theorem.

major comments (3)
  1. [Abstract; §I Contributions (2); Table III; Fig. 6(b); §VI] Abstract, Contributions (2), and §VI claim the framework “can also complete reconstruction tasks at the hundred-qubit scale,” but the only ~100-qubit unstructured evidence is Table III (104-qubit random): in-memory fail vs hierarchical complete, reporting only peak GiB/rank. There is no reconstructed-state cardinality, runtime, communication/I/O mix, or fidelity for that instance. Fig. 6(b)’s 118-qubit GHZ/BV checks only O(1)-support principal states, for which sparse aggregation is nearly trivial once subcircuit tables exist. Mid-scale hardness is well shown (Table II: ~2×10^10–1.7×10^11 nonzero states at 50–54 qubits), so the headline scale sentence currently bundles easy structured cases with an under-characterized random completion. Either add workload metrics (and ideally fidelity/runtime) for the 104-qubit hierarchical run, or qualify the claim to structured/low-support circuits pl
  2. [Abstract; §V Discussion; §VI] §V (final paragraphs) and §VI correctly state that experiments use noiseless subcircuit measurement data and that the implementation is limited to subcircuits with at most two cut points. Those premises are load-bearing for fidelity and for the sparse-state regime the framework targets: noise and multi-cut fragments can densify or corrupt supports and change intermediate expansion cost. The abstract and contribution list still present fidelity and hundred-qubit completion without that scope. The manuscript should carry the noiseless and ≤2-cut-point limitations into the abstract/claims and, where possible, give at least a small noisy or multi-cut stress case—or an explicit non-claim—so readers do not over-transfer Fig. 4–6 results to end-to-end hardware cutting.
  3. [Abstract; §IV-B; Fig. 4; Fig. 7] Fig. 4(a) reports up to ~259× versus an “optimized serial” baseline using up to five nodes for the heterogeneous side, while Fig. 4(b) fairly isolates DCU benefit at fixed 60 nodes (~1–4×). The large serial number therefore mixes distributed parallelism, integer indexing (Fig. 7), and DCU offload. §IV-B describes this, but the abstract’s “259× … over an optimized serial baseline” is easy to misread as pure accelerator gain. Please state node/process counts beside that number in the abstract and clarify how much of the gain remains after the integer-index serial optimization alone, so the central speedup claim is partitioned consistently with Fig. 4(a) vs 4(b) and Fig. 7.
minor comments (6)
  1. [§II, Eq. (7)] Eq. (7) writes a sum of Kronecker products p1,i ⊗ p2,i for scalar probability terms; for single amplitudes/probabilities this is ordinary multiplication. A short clarification that ⊗ denotes combination of subsystem bit-strings (index concatenation) plus probability multiply would avoid notation confusion.
  2. [Table II] Table II header/body spacing and the “19.99×10^9” style are fine, but units and whether counts are global totals vs per-rank maxima should be stated explicitly in the caption.
  3. [Fig. 5; §IV-C] Fig. 5 strong-scaling efficiency (51.32% at 300 nodes) is useful; adding the communication+I/O share numbers from the text into the figure legend or a small inset table would make the bottleneck argument self-contained.
  4. [§I; §V-C; Fig. 8] Related-work coverage of CutQC/DD, FRA, and sparse tensor cutting is adequate; a one-sentence comparison of target output (full dense vs high-probability sample vs exact nonzero support) in a small table would help readers place SR.
  5. [Throughout] Minor prose/typo cleanup: “Songshan” platform details are clear in Table I; ensure consistent “DCU” expansion on first use in the body, and fix occasional spacing issues around math (e.g., “2 n”, “4 K”) in the compiled text.
  6. [Data and Code Availability] Data/code availability URL is appreciated; please note license and the exact commit or release tag corresponding to the reported numbers for reproducibility.

Circularity Check

0 steps flagged · score 0.0 of 10

No circularity: empirical systems benchmarks, not a self-justifying derivation chain

full rationale

This is an HPC systems paper whose load-bearing claims are measured speedups, fidelity, and completion capability on Songshan, not first-principles predictions derived from fitted inputs. Reconstruction follows the standard circuit-cutting expansion (Pauli/eigenbasis terms and Kronecker products, Eqs. 1–7) taken from the external literature; fidelity (Eq. 8) compares reconstructed distributions to independent theoretical GHZ/BV/linear-cluster structure or shot-limited references. Integer high/low-word indexing, SplitMix64 owner routing, and three-level storage are implementation choices evaluated by runtime and memory metrics against serial and homogeneous-CPU baselines—not quantities defined in terms of the claimed outcomes. There is no fitted parameter re-labeled as a prediction, no uniqueness theorem imported from the authors, and no self-citation that forces the central performance claims. Ordinary author-run evaluation of their own code is not circularity under the stated criteria. Score 0; steps empty.

Assumptions & free parameters 4 free parameters · 5 assumptions · 1 invented entities

The central claims rest on standard circuit-cutting reconstruction identities, an engineering sparse-state execution model, and platform-specific parallel/storage design choices—not on fitted physical constants. Free parameters are runtime/system thresholds and experimental configuration choices that affect performance and completion, not the mathematical definition of reconstructed probabilities.

free parameters (4)
  • Host-memory spill threshold / out-of-core activation threshold = Not numerically standardized in the paper; enabled vs disabled compared on 104-qubit stress test
    Chosen system threshold that triggers spilling intermediate buckets; directly affects whether large instances complete and the I/O share of runtime.
  • Block-granularity parameter for spill read/write/merge
    Controls I/O frequency vs merge overhead; engineering knob affecting scalability measurements.
  • MPI process/node counts and batch sizes for DCU offload = Various; strong-scaling baseline 60 nodes
    Experimental resource layout (e.g., up to 5 nodes for serial comparison, 60–300 nodes for scaling, 10 nodes×4 ranks for storage stress) shapes reported speedups and efficiency.
  • Measurement shot counts for fidelity studies = Varied; exact schedules only partly detailed in text
    Finite shots affect empirical fidelity on linear-cluster states; paper shows more shots improve 30-qubit fidelity toward theory.
assumptions (5)
  • domain assumption Standard wire-cutting reconstruction: original outcome probabilities are recovered from a quasiprobability/Kronecker combination of subcircuit measurement and preparation configurations (Pauli-basis expansion, 4^K terms for K cuts).
    Section II derives and illustrates the cut identities used throughout; framework assumes this classical combination is the correct target.
  • domain assumption Retaining only aggregated states with p(s)>0 yields the intended sparse reconstruction of the original output support (up to numerical/sampling error).
    Core SR strategy in Sections I and III; sound for exact arithmetic on exact subcircuit distributions, approximate under sampling/noise.
  • standard math Deterministic SplitMix64-based owner mapping sends all contributions for a global index to one MPI rank so distributed reduction is correct.
    Section III-B; correctness needs only determinism and full accumulation, not randomness quality beyond load distribution.
  • ad hoc to paper Noiseless (or ideal classical) subcircuit probability tables are a valid test of classical reconstruction fidelity and scalability.
    Explicitly adopted in Discussion; underpins hundred-qubit fidelity/completion claims while deferring noise robustness.
  • ad hoc to paper Each subcircuit involves at most two cut points in the current implementation.
    Stated limitation in Conclusion; scopes the demonstrated method away from more complex cutting graphs.
invented entities (1)
  • CPU+DCU heterogeneous sparse reconstruction framework (SR) with high/low-word indices and three-level cooperative storage independent evidence
    purpose: Name and organize the end-to-end software architecture that performs distributed nonzero-probability reconstruction on Songshan.
    Not a new physical entity; a systems artifact. Independent evidence is the public code link and reported runs, but the ‘entity’ is the implementation itself.

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Cite this review

Pith. "Pith review of A CPU+DCU Heterogeneous Parallel Framework for Post-Processing Reconstruction in Quantum Circuit Cutting." pith.science (2026). https://pith.science/paper/DICH73GH

@misc{pith2026260727947,
  author       = {Pith},
  title        = {Pith review of: A CPU+DCU Heterogeneous Parallel Framework for Post-Processing Reconstruction in Quantum Circuit Cutting},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/DICH73GH}},
  note         = {Machine review of arXiv:2607.27947}
}
abstract

In the NISQ era, limited qubit resources make it difficult to execute large quantum circuits directly on real hardware. Quantum circuit cutting mitigates this limitation by decomposing a large circuit into smaller subcircuits, but it shifts substantial overhead to classical post-processing. As circuit size, complexity, and cut count increase, reconstruction becomes a major computational and storage bottleneck. This paper presents a CPU+DCU heterogeneous parallel framework for circuit-cutting post-processing reconstruction. Instead of constructing a dense $2^n$-dimensional probability vector or returning only high-probability states, the framework reconstructs the nonzero-probability states in the original output distribution from subcircuit measurement results. It combines heterogeneous CPU+DCU execution with a high/low-word integer representation for global basis-state indices beyond 64 bits and a three-level cooperative storage mechanism spanning device memory, host memory, and out-of-core storage. Experiments on the Songshan supercomputer show that the framework maintains high reconstruction fidelity while achieving up to $259\times$ speedup over an optimized serial baseline on linear-cluster states and up to $4\times$ speedup over a homogeneous CPU-parallel method on random circuits. The framework can also complete reconstruction tasks at the hundred-qubit scale. These results demonstrate that HPC-oriented heterogeneous reconstruction can effectively alleviate the classical post-processing bottleneck and improve reconstruction scalability.

Figures

Figures reproduced from arXiv: 2607.27947 by the authors.

Figure 1
Figure 1. Illustration of quantum circuit cutting. [PITH_FULL_IMAGE:figures/full_fig_p003_1.png] view at source ↗
Figure 2
Figure 2. Overall workflow of the proposed CPU+DCU heterogeneous parallel [PITH_FULL_IMAGE:figures/full_fig_p004_2.png] view at source ↗
Figure 3
Figure 3. Schematic of the hierarchical cooperative storage mechanism. Device memory performs DCU-side state expansion and probability computation and [PITH_FULL_IMAGE:figures/full_fig_p006_3.png] view at source ↗
Figures from the paper (5 more)
Figure 5
Figure 5. Figure 5: Strong-scaling results for the post-processing reconstruction of a fixed [PITH_FULL_IMAGE:figures/full_fig_p007_5.png]
Figure 4
Figure 4. Figure 4: Speedup evaluation of the CPU+DCU heterogeneous framework. [PITH_FULL_IMAGE:figures/full_fig_p007_4.png]
Figure 7
Figure 7. Figure 7: Effect of quantum state integer indexing on serial post-processing [PITH_FULL_IMAGE:figures/full_fig_p008_7.png]
Figure 8
Figure 8. Figure 8: Comparison of reconstructed-state counts for DD, FRA, and SR on [PITH_FULL_IMAGE:figures/full_fig_p009_8.png]
Figure 9
Figure 9. Figure 9: Runtime variation of classical post-processing under different numbers [PITH_FULL_IMAGE:figures/full_fig_p010_9.png]

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Works this paper leans on

58 extracted references · 1 linked inside Pith

  1. [1]

    Quantum machine learning,

    J. Biamonte, P. Wittek, N. Pancotti, P. Rebentrost, N. Wiebe, and S. Lloyd, “Quantum machine learning,”Nature, vol. 549, no. 7671, pp. 195–202, 2017

    2017

  2. [2]

    Simulating physics with computers,

    R. P. Feynman, “Simulating physics with computers,”International Journal of Theoretical Physics, vol. 21, no. 6-7, pp. 467–488, 1982

    1982

  3. [3]

    Universal quantum simulators,

    S. Lloyd, “Universal quantum simulators,”Science, vol. 273, no. 5278, pp. 1073–1078, 1996

    1996

  4. [4]

    Towards quantum chemistry on a quantum computer,

    B. P. Lanyon, J. D. Whitfield, G. G. Gillett, M. E. Goggin, M. P. Almeida, I. Kassal, J. D. Biamonte, M. Mohseni, B. J. Powell, M. Bar- bieri, A. Aspuru-Guzik, and A. G. White, “Towards quantum chemistry on a quantum computer,”Nature Chemistry, vol. 2, no. 2, pp. 106–111, 2010

    2010

  5. [5]

    Simulations of many-body fermi systems on a universal quantum computer,

    D. S. Abrams and S. Lloyd, “Simulations of many-body fermi systems on a universal quantum computer,”Physical Review Letters, vol. 79, no. 13, pp. 2586–2589, 1997

    1997

  6. [6]

    Quantum algorithms: an overview,

    A. Montanaro, “Quantum algorithms: an overview,”npj Quantum Infor- mation, vol. 2, no. 1, pp. 1–8, 2016

    2016

  7. [7]

    Algorithms for quantum computation: discrete logarithms and factoring,

    P. W. Shor, “Algorithms for quantum computation: discrete logarithms and factoring,” inProceedings of the 35th Annual Symposium on Foundations of Computer Science, 1994, pp. 124–134

    1994

  8. [8]

    A fast quantum mechanical algorithm for database search,

    L. K. Grover, “A fast quantum mechanical algorithm for database search,” inProceedings of the 28th Annual ACM Symposium on Theory of Computing, 1996, pp. 212–219

    1996

Show all 58 references
  1. [9]

    Quantum computing in the NISQ era and beyond,

    J. Preskill, “Quantum computing in the NISQ era and beyond,”Quan- tum, vol. 2, p. 79, 2018

    2018

  2. [10]

    Near-term quantum computing techniques: Variational quantum algorithms, error mitigation, circuit compilation, benchmark- ing, and classical simulation,

    H.-L. Huang, X.-Y . Xu, C. Guo, G. Tian, S.-J. Wei, X. Sun, W.-S. Bao, and G.-L. Long, “Near-term quantum computing techniques: Variational quantum algorithms, error mitigation, circuit compilation, benchmark- ing, and classical simulation,”Science China Physics, Mechanics & A...

    2023

  3. [11]

    Early fault- tolerant quantum computing,

    A. Katabarwa, K. Gratsea, A. Caesura, and P. D. Johnson, “Early fault- tolerant quantum computing,”PRX Quantum, vol. 5, no. 2, p. 020101, 2024

    2024

  4. [12]

    In- tegrating quantum computing resources into scientific HPC ecosystems,

    T. Beck, A. Baroni, R. Bennink, G. Buchs, E. A. C. P ´erez, M. Eisenbach, R. F. da Silva, M. G. Meena, K. Gottiparthi, P. Groszkowskiet al., “In- tegrating quantum computing resources into scientific HPC ecosystems,” Future Generation Computer Systems, vol. 161, pp. 11–25, 2024

    2024

  5. [13]

    Integration of quantum accel- erators into HPC: Toward a unified quantum platform,

    A. Elsharkawy, X. Guo, and M. Schulz, “Integration of quantum accel- erators into HPC: Toward a unified quantum platform,” in2024 IEEE International Conference on Quantum Computing and Engineering (QCE), vol. 1, 2024, pp. 774–783

    2024

  6. [14]

    Bridging paradigms: De- signing for HPC-quantum convergence,

    A. Shehata, P. Groszkowski, T. Naughton, M. G. Meena, E. Wong, D. Claudino, R. F. Da Silva, and T. Beck, “Bridging paradigms: De- signing for HPC-quantum convergence,”Future Generation Computer Systems, vol. 174, p. 107980, 2026

    2026

  7. [15]

    Trading classical and quantum computational resources,

    S. Bravyi, G. Smith, and J. A. Smolin, “Trading classical and quantum computational resources,”Physical Review X, vol. 6, no. 2, p. 021043, 2016

    2016

  8. [16]

    Circuit knitting with classical communi- cation,

    C. Piveteau and D. Sutter, “Circuit knitting with classical communi- cation,”IEEE Transactions on Information Theory, vol. 70, no. 4, pp. 2734–2745, 2023. IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, VOL. XX, NO. X, MONTH 2026 12

    2023

  9. [17]

    Simulating large quantum circuits on a small quantum computer,

    T. Peng, A. W. Harrow, M. Ozols, and X. Wu, “Simulating large quantum circuits on a small quantum computer,”Physical Review Letters, vol. 125, no. 15, p. 150504, 2020

    2020

  10. [18]

    Quantum circuit cutting for classical shadows,

    D. T. S. Chen, Z. H. Saleem, and M. A. Perlin, “Quantum circuit cutting for classical shadows,”ACM Transactions on Quantum Computing, vol. 5, no. 2, pp. 1–21, 2024

    2024

  11. [19]

    Experimental simulation of larger quantum circuits with fewer superconducting qubits,

    C. Ying, B. Cheng, Y . Zhao, H.-L. Huang, Y .-N. Zhang, M. Gong, Y . Wu, S. Wang, F. Liang, J. Linet al., “Experimental simulation of larger quantum circuits with fewer superconducting qubits,”Physical Review Letters, vol. 130, no. 11, p. 110601, 2023

    2023

  12. [20]

    Constructing a virtual two-qubit gate by sampling single-qubit operations,

    K. Mitarai and K. Fujii, “Constructing a virtual two-qubit gate by sampling single-qubit operations,”New Journal of Physics, vol. 23, no. 2, p. 023021, 2021

    2021

  13. [21]

    Overhead for simulating a non-local channel with local channels by quasiprobability sampling,

    K. Mitarai and K. Fujii, “Overhead for simulating a non-local channel with local channels by quasiprobability sampling,”Quantum, vol. 5, p. 388, 2021

    2021

  14. [22]

    Fast quantum circuit cutting with randomized measurements,

    A. Lowe, M. Medvidovi ´c, A. Hayes, L. J. O’Riordan, T. R. Bromley, J. M. Arrazola, and N. Killoran, “Fast quantum circuit cutting with randomized measurements,”Quantum, vol. 7, p. 934, 2023

    2023

  15. [23]

    Quantum circuit cutting with maximum-likelihood tomography,

    M. A. Perlin, Z. H. Saleem, M. Suchara, and J. C. Osborn, “Quantum circuit cutting with maximum-likelihood tomography,”npj Quantum Information, vol. 7, no. 1, p. 64, 2021

    2021

  16. [24]

    CutQC: Using small quantum computers for large quantum circuit evaluations,

    W. Tang, T. Tomesh, M. Suchara, J. Larson, and M. Martonosi, “CutQC: Using small quantum computers for large quantum circuit evaluations,” inProceedings of the 26th ACM International Conference on Archi- tectural Support for Programming Languages and Operating Systems, 2021, p...

    2021

  17. [25]

    Ap- proximate quantum circuit reconstruction,

    D. Chen, B. Baheri, V . Chaudhary, Q. Guan, N. Xie, and S. Xu, “Ap- proximate quantum circuit reconstruction,” in2022 IEEE International Conference on Quantum Computing and Engineering (QCE), 2022, pp. 509–515

    2022

  18. [26]

    Fast reconstruction algorithm based on HMC sampling,

    H. Lian, J. Xu, Y . Zhu, Z. Fan, Y . Liu, and Z. Shan, “Fast reconstruction algorithm based on HMC sampling,”Scientific Reports, vol. 13, no. 1, p. 17773, 2023

    2023

  19. [27]

    A case for quantum circuit cutting for NISQ applications: Impact of topology, determinism, and sparsity,

    Z. Li, M. Guo, M. Barad, W. Tang, E. Z. Zhang, and Y . Huang, “A case for quantum circuit cutting for NISQ applications: Impact of topology, determinism, and sparsity,”arXiv preprint arXiv:2412.17929, 2024

    2024 arXiv

  20. [28]

    Leveraging state sparsity for more efficient quantum simulations,

    S. Jaques and T. H ¨aner, “Leveraging state sparsity for more efficient quantum simulations,”ACM Transactions on Quantum Computing, vol. 3, no. 3, pp. 1–17, 2022

    2022

  21. [29]

    Kokkos 3: Programming model extensions for the exascale era,

    C. R. Trott, D. Lebrun-Grandi ´e, D. Arndt, J. Ciesko, V . Dang, N. Elling- wood, R. Gayatri, E. Harvey, D. S. Hollman, D. Ibanezet al., “Kokkos 3: Programming model extensions for the exascale era,”IEEE Transactions on Parallel and Distributed Systems, vol. 33, no. 4, pp. 805...

    2021

  22. [30]

    IRIS: A performance- portable framework for cross-platform heterogeneous computing,

    J. Kim, S. Lee, B. Johnston, and J. S. Vetter, “IRIS: A performance- portable framework for cross-platform heterogeneous computing,”IEEE Transactions on Parallel and Distributed Systems, vol. 35, no. 10, pp. 1796–1809, 2024

    2024

  23. [31]

    Co-concurrency mecha- nism for multi-GPUs in distributed heterogeneous environments,

    X. Zhang, Z. Tang, X. Zhang, and K. Li, “Co-concurrency mecha- nism for multi-GPUs in distributed heterogeneous environments,”IEEE Transactions on Parallel and Distributed Systems, vol. 33, no. 12, pp. 4935–4947, 2022

    2022

  24. [32]

    The PETScSF scalable communication layer,

    J. Zhang, J. Brown, S. Balay, J. Faibussowitsch, M. Knepley, O. Marin, R. T. Mills, T. Munson, B. F. Smith, and S. Zampini, “The PETScSF scalable communication layer,”IEEE Transactions on Parallel and Distributed Systems, vol. 33, no. 4, pp. 842–853, 2021

    2021

  25. [33]

    Optimizing the LINPACK algorithm for large-scale PCIe-based CPU-GPU heterogeneous systems,

    G. Tan, C. Shui, Y . Wang, X. Yu, and Y . Yan, “Optimizing the LINPACK algorithm for large-scale PCIe-based CPU-GPU heterogeneous systems,” IEEE Transactions on Parallel and Distributed Systems, vol. 32, no. 9, pp. 2367–2380, 2021

    2021

  26. [34]

    VCSR: An efficient GPU memory-aware sparse format,

    E. Karimi, N. B. Agostini, S. Dong, and D. Kaeli, “VCSR: An efficient GPU memory-aware sparse format,”IEEE Transactions on Parallel and Distributed Systems, vol. 33, no. 12, pp. 3977–3989, 2022

    2022

  27. [35]

    Fast and scalable quantum computing simulation on multi-core and many-core platforms,

    A. Ahmadzadeh and H. Sarbazi-Azad, “Fast and scalable quantum computing simulation on multi-core and many-core platforms,”Quantum Information Processing, vol. 22, no. 5, p. 215, 2023

    2023

  28. [36]

    0.5 petabyte simulation of a 45-qubit quantum circuit,

    T. H ¨aner and D. S. Steiger, “0.5 petabyte simulation of a 45-qubit quantum circuit,” inProceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis, 2017, pp. 1–10

    2017

  29. [37]

    Full-state quantum circuit simulation by using data compression,

    X.-C. Wu, S. Di, E. M. Dasgupta, F. Cappello, H. Finkel, Y . Alexeev, and F. T. Chong, “Full-state quantum circuit simulation by using data compression,” inProceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis, 2019, pp. 1–24

    2019

  30. [38]

    Closing the “quantum supremacy

    Y . Liu, X. Liu, F. Li, H. Fu, Y . Yang, J. Song, P. Zhao, Z. Wang, D. Peng, H. Chenet al., “Closing the “quantum supremacy” gap: Achieving real-time simulation of a random quantum circuit using a new Sunway supercomputer,” inProceedings of the International Conference for Hig...

    2021

  31. [39]

    Quantum supremacy cir- cuit simulation on Sunway TaihuLight,

    R. Li, B. Wu, M. Ying, X. Sun, and G. Yang, “Quantum supremacy cir- cuit simulation on Sunway TaihuLight,”IEEE Transactions on Parallel and Distributed Systems, vol. 31, no. 4, pp. 805–816, 2019

    2019

  32. [40]

    QuEST and high- performance simulation of quantum computers,

    T. Jones, A. Brown, I. Bush, and S. C. Benjamin, “QuEST and high- performance simulation of quantum computers,”Scientific Reports, vol. 9, no. 1, p. 10736, 2019

    2019

  33. [41]

    UniQ: A unified programming model for efficient quantum circuit simulation,

    C. Zhang, H. Wang, Z. Ma, L. Xie, Z. Song, and J. Zhai, “UniQ: A unified programming model for efficient quantum circuit simulation,” inSC22: International Conference for High Performance Computing, Networking, Storage and Analysis, 2022, pp. 1–16

    2022

  34. [42]

    Atlas: Hierarchi- cal partitioning for quantum circuit simulation on GPUs,

    M. Xu, S. Cao, X. Miao, U. A. Acar, and Z. Jia, “Atlas: Hierarchi- cal partitioning for quantum circuit simulation on GPUs,” inSC24: International Conference for High Performance Computing, Networking, Storage and Analysis, 2024, pp. 1–17

    2024

  35. [43]

    Tensor network quantum virtual machine for simulating quan- tum circuits at exascale,

    T. Nguyen, D. Lyakh, E. Dumitrescu, D. Clark, J. Larkin, and A. Mc- Caskey, “Tensor network quantum virtual machine for simulating quan- tum circuits at exascale,”ACM Transactions on Quantum Computing, vol. 4, no. 1, pp. 1–21, 2022

    2022

  36. [44]

    Efficient quantum circuit simulation by tensor network methods on modern GPUs,

    F. Pan, H. Gu, L. Kuang, B. Liu, and P. Zhang, “Efficient quantum circuit simulation by tensor network methods on modern GPUs,”ACM Transactions on Quantum Computing, vol. 5, no. 4, pp. 1–26, 2024

    2024

  37. [45]

    Performance analysis and mod- eling for quantum computing simulation on distributed GPU platforms,

    A. Ahmadzadeh and H. Sarbazi-Azad, “Performance analysis and mod- eling for quantum computing simulation on distributed GPU platforms,” Quantum Information Processing, vol. 23, no. 11, p. 373, 2024

    2024

  38. [46]

    HyQuas: Hybrid partitioner-based quantum circuit simulation system on GPU,

    C. Zhang, Z. Song, H. Wang, K. Rong, and J. Zhai, “HyQuas: Hybrid partitioner-based quantum circuit simulation system on GPU,” inPro- ceedings of the 35th ACM International Conference on Supercomputing, 2021, pp. 443–454

    2021

  39. [47]

    dgQuEST: Accelerating large-scale quantum circuit simulation through hybrid CPU-GPU memory hierarchies,

    T. Feng, S. Chen, X. You, S. Zhong, H. Yang, Z. Luan, and D. Qian, “dgQuEST: Accelerating large-scale quantum circuit simulation through hybrid CPU-GPU memory hierarchies,” inIFIP International Confer- ence on Network and Parallel Computing, 2021, pp. 16–27

    2021

  40. [48]

    Communication-partition co- optimization for quantum circuit simulation on CPU+GPU clusters,

    C. Jiao, W. Zhang, and L. Shen, “Communication-partition co- optimization for quantum circuit simulation on CPU+GPU clusters,” IEEE Transactions on Parallel and Distributed Systems, vol. 37, no. 6, pp. 1280–1294, 2026

    2026

  41. [49]

    QuanPath: Achieving one-step communication for distributed quantum circuit simulation,

    Y . Song, E. H.-M. Sha, Q. Zhuge, W. Xiao, Q. Dai, and L. Xu, “QuanPath: Achieving one-step communication for distributed quantum circuit simulation,”Quantum Information Processing, vol. 23, no. 1, p. 1, 2024

    2024

  42. [50]

    Minimizing communications of quantum circuit simulations on distributed systems,

    L. Xu, E. H.-M. Sha, Y . Song, Y . Chi, and Q. Zhuge, “Minimizing communications of quantum circuit simulations on distributed systems,” IEEE Transactions on Parallel and Distributed Systems, vol. 37, no. 4, pp. 775–786, 2026

    2026

  43. [51]

    Fast splittable pseudorandom number generators,

    G. L. Steele Jr, D. Lea, and C. H. Flood, “Fast splittable pseudorandom number generators,”ACM SIGPLAN Notices, vol. 49, no. 10, pp. 453– 472, 2014

    2014

  44. [52]

    Towards communication-efficient out-of-core graph processing on the GPU,

    Q. Wang, X. Ai, Y . Yan, S. Gong, Y . Zhang, J. Chen, and G. Yu, “Towards communication-efficient out-of-core graph processing on the GPU,”IEEE Transactions on Parallel and Distributed Systems, vol. 36, no. 5, pp. 961–976, 2025

    2025

  45. [53]

    SnuQS: Scaling quantum circuit simulation using storage devices,

    D. Park, H. Kim, J. Kim, T. Kim, and J. Lee, “SnuQS: Scaling quantum circuit simulation using storage devices,” inProceedings of the 36th ACM International Conference on Supercomputing, 2022, pp. 1–13

    2022

  46. [54]

    Cluster-state quantum computation,

    M. A. Nielsen, “Cluster-state quantum computation,”Reports on Math- ematical Physics, vol. 57, no. 1, pp. 147–161, 2006

    2006

  47. [55]

    Going beyond bell’s theorem,

    D. M. Greenberger, M. A. Horne, and A. Zeilinger, “Going beyond bell’s theorem,” inBell’s Theorem, Quantum Theory and Conceptions of the Universe. Springer, 1989, pp. 69–72

    1989

  48. [56]

    Quantum complexity theory,

    E. Bernstein and U. Vazirani, “Quantum complexity theory,” inPro- ceedings of the 25th Annual ACM Symposium on Theory of Computing, 1993, pp. 11–20

    1993

  49. [57]

    Quantum divide and compute: Exploring the effect of different noise sources,

    T. Ayral, F.-M. L. R ´egent, Z. Saleem, Y . Alexeev, and M. Suchara, “Quantum divide and compute: Exploring the effect of different noise sources,”SN Computer Science, vol. 2, no. 3, p. 132, 2021

    2021

  50. [58]

    Error mitigation for short- depth quantum circuits,

    K. Temme, S. Bravyi, and J. M. Gambetta, “Error mitigation for short- depth quantum circuits,”Physical Review Letters, vol. 119, no. 18, p. 180509, 2017

    2017

Pith tools

Reviewed July 31, 2026 · model on record in the stance chip above.